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usbredir: Verify we have 32 bits bulk length cap when redirecting to xhci
[qemu/opensuse.git] / tcg / ppc64 / tcg-target.c
blob833fe0c10b9b44389dffa72c1ba62d09f0e6f2b6
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_U32 0x100
26
27 static uint8_t *tb_ret_addr;
28
29 #define FAST_PATH
30
31 #if TARGET_LONG_BITS == 32
32 #define LD_ADDR LWZU
33 #define CMP_L 0
34 #else
35 #define LD_ADDR LDU
36 #define CMP_L (1<<21)
37 #endif
38
39 #ifndef GUEST_BASE
40 #define GUEST_BASE 0
41 #endif
42
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG 30
45 #else
46 #define TCG_GUEST_BASE_REG 0
47 #endif
48
49 #ifndef NDEBUG
50 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
51 "r0",
52 "r1",
53 "r2",
54 "r3",
55 "r4",
56 "r5",
57 "r6",
58 "r7",
59 "r8",
60 "r9",
61 "r10",
62 "r11",
63 "r12",
64 "r13",
65 "r14",
66 "r15",
67 "r16",
68 "r17",
69 "r18",
70 "r19",
71 "r20",
72 "r21",
73 "r22",
74 "r23",
75 "r24",
76 "r25",
77 "r26",
78 "r27",
79 "r28",
80 "r29",
81 "r30",
82 "r31"
83 };
84 #endif
85
86 static const int tcg_target_reg_alloc_order[] = {
87 TCG_REG_R14,
88 TCG_REG_R15,
89 TCG_REG_R16,
90 TCG_REG_R17,
91 TCG_REG_R18,
92 TCG_REG_R19,
93 TCG_REG_R20,
94 TCG_REG_R21,
95 TCG_REG_R22,
96 TCG_REG_R23,
97 TCG_REG_R28,
98 TCG_REG_R29,
99 TCG_REG_R30,
100 TCG_REG_R31,
101 #ifdef __APPLE__
102 TCG_REG_R2,
103 #endif
104 TCG_REG_R3,
105 TCG_REG_R4,
106 TCG_REG_R5,
107 TCG_REG_R6,
108 TCG_REG_R7,
109 TCG_REG_R8,
110 TCG_REG_R9,
111 TCG_REG_R10,
112 #ifndef __APPLE__
113 TCG_REG_R11,
114 #endif
115 TCG_REG_R12,
116 TCG_REG_R24,
117 TCG_REG_R25,
118 TCG_REG_R26,
119 TCG_REG_R27
120 };
121
122 static const int tcg_target_call_iarg_regs[] = {
123 TCG_REG_R3,
124 TCG_REG_R4,
125 TCG_REG_R5,
126 TCG_REG_R6,
127 TCG_REG_R7,
128 TCG_REG_R8,
129 TCG_REG_R9,
130 TCG_REG_R10
131 };
132
133 static const int tcg_target_call_oarg_regs[] = {
134 TCG_REG_R3
135 };
136
137 static const int tcg_target_callee_save_regs[] = {
138 #ifdef __APPLE__
139 TCG_REG_R11,
140 #endif
141 TCG_REG_R14,
142 TCG_REG_R15,
143 TCG_REG_R16,
144 TCG_REG_R17,
145 TCG_REG_R18,
146 TCG_REG_R19,
147 TCG_REG_R20,
148 TCG_REG_R21,
149 TCG_REG_R22,
150 TCG_REG_R23,
151 TCG_REG_R24,
152 TCG_REG_R25,
153 TCG_REG_R26,
154 TCG_REG_R27, /* currently used for the global env */
155 TCG_REG_R28,
156 TCG_REG_R29,
157 TCG_REG_R30,
158 TCG_REG_R31
159 };
160
161 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
162 {
163 tcg_target_long disp;
164
165 disp = target - (tcg_target_long) pc;
166 if ((disp << 38) >> 38 != disp)
167 tcg_abort ();
168
169 return disp & 0x3fffffc;
170 }
171
172 static void reloc_pc24 (void *pc, tcg_target_long target)
173 {
174 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
175 | reloc_pc24_val (pc, target);
176 }
177
178 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
179 {
180 tcg_target_long disp;
181
182 disp = target - (tcg_target_long) pc;
183 if (disp != (int16_t) disp)
184 tcg_abort ();
185
186 return disp & 0xfffc;
187 }
188
189 static void reloc_pc14 (void *pc, tcg_target_long target)
190 {
191 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
192 | reloc_pc14_val (pc, target);
193 }
194
195 static void patch_reloc (uint8_t *code_ptr, int type,
196 tcg_target_long value, tcg_target_long addend)
197 {
198 value += addend;
199 switch (type) {
200 case R_PPC_REL14:
201 reloc_pc14 (code_ptr, value);
202 break;
203 case R_PPC_REL24:
204 reloc_pc24 (code_ptr, value);
205 break;
206 default:
207 tcg_abort ();
208 }
209 }
210
211 /* parse target specific constraints */
212 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
213 {
214 const char *ct_str;
215
216 ct_str = *pct_str;
217 switch (ct_str[0]) {
218 case 'A': case 'B': case 'C': case 'D':
219 ct->ct |= TCG_CT_REG;
220 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
221 break;
222 case 'r':
223 ct->ct |= TCG_CT_REG;
224 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
225 break;
226 case 'L': /* qemu_ld constraint */
227 ct->ct |= TCG_CT_REG;
228 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
229 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
230 #ifdef CONFIG_SOFTMMU
231 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
232 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
233 #endif
234 break;
235 case 'S': /* qemu_st constraint */
236 ct->ct |= TCG_CT_REG;
237 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
238 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
239 #ifdef CONFIG_SOFTMMU
240 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
241 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
242 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
243 #endif
244 break;
245 case 'Z':
246 ct->ct |= TCG_CT_CONST_U32;
247 break;
248 default:
249 return -1;
250 }
251 ct_str++;
252 *pct_str = ct_str;
253 return 0;
254 }
255
256 /* test if a constant matches the constraint */
257 static int tcg_target_const_match (tcg_target_long val,
258 const TCGArgConstraint *arg_ct)
259 {
260 int ct;
261
262 ct = arg_ct->ct;
263 if (ct & TCG_CT_CONST)
264 return 1;
265 else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
266 return 1;
267 return 0;
268 }
269
270 #define OPCD(opc) ((opc)<<26)
271 #define XO19(opc) (OPCD(19)|((opc)<<1))
272 #define XO30(opc) (OPCD(30)|((opc)<<2))
273 #define XO31(opc) (OPCD(31)|((opc)<<1))
274 #define XO58(opc) (OPCD(58)|(opc))
275 #define XO62(opc) (OPCD(62)|(opc))
276
277 #define B OPCD( 18)
278 #define BC OPCD( 16)
279 #define LBZ OPCD( 34)
280 #define LHZ OPCD( 40)
281 #define LHA OPCD( 42)
282 #define LWZ OPCD( 32)
283 #define STB OPCD( 38)
284 #define STH OPCD( 44)
285 #define STW OPCD( 36)
286
287 #define STD XO62( 0)
288 #define STDU XO62( 1)
289 #define STDX XO31(149)
290
291 #define LD XO58( 0)
292 #define LDX XO31( 21)
293 #define LDU XO58( 1)
294 #define LWA XO58( 2)
295 #define LWAX XO31(341)
296
297 #define ADDIC OPCD( 12)
298 #define ADDI OPCD( 14)
299 #define ADDIS OPCD( 15)
300 #define ORI OPCD( 24)
301 #define ORIS OPCD( 25)
302 #define XORI OPCD( 26)
303 #define XORIS OPCD( 27)
304 #define ANDI OPCD( 28)
305 #define ANDIS OPCD( 29)
306 #define MULLI OPCD( 7)
307 #define CMPLI OPCD( 10)
308 #define CMPI OPCD( 11)
309
310 #define LWZU OPCD( 33)
311 #define STWU OPCD( 37)
312
313 #define RLWINM OPCD( 21)
314
315 #define RLDICL XO30( 0)
316 #define RLDICR XO30( 1)
317 #define RLDIMI XO30( 3)
318
319 #define BCLR XO19( 16)
320 #define BCCTR XO19(528)
321 #define CRAND XO19(257)
322 #define CRANDC XO19(129)
323 #define CRNAND XO19(225)
324 #define CROR XO19(449)
325 #define CRNOR XO19( 33)
326
327 #define EXTSB XO31(954)
328 #define EXTSH XO31(922)
329 #define EXTSW XO31(986)
330 #define ADD XO31(266)
331 #define ADDE XO31(138)
332 #define ADDC XO31( 10)
333 #define AND XO31( 28)
334 #define SUBF XO31( 40)
335 #define SUBFC XO31( 8)
336 #define SUBFE XO31(136)
337 #define OR XO31(444)
338 #define XOR XO31(316)
339 #define MULLW XO31(235)
340 #define MULHWU XO31( 11)
341 #define DIVW XO31(491)
342 #define DIVWU XO31(459)
343 #define CMP XO31( 0)
344 #define CMPL XO31( 32)
345 #define LHBRX XO31(790)
346 #define LWBRX XO31(534)
347 #define STHBRX XO31(918)
348 #define STWBRX XO31(662)
349 #define MFSPR XO31(339)
350 #define MTSPR XO31(467)
351 #define SRAWI XO31(824)
352 #define NEG XO31(104)
353 #define MFCR XO31( 19)
354 #define NOR XO31(124)
355 #define CNTLZW XO31( 26)
356 #define CNTLZD XO31( 58)
357
358 #define MULLD XO31(233)
359 #define MULHD XO31( 73)
360 #define MULHDU XO31( 9)
361 #define DIVD XO31(489)
362 #define DIVDU XO31(457)
363
364 #define LBZX XO31( 87)
365 #define LHZX XO31(279)
366 #define LHAX XO31(343)
367 #define LWZX XO31( 23)
368 #define STBX XO31(215)
369 #define STHX XO31(407)
370 #define STWX XO31(151)
371
372 #define SPR(a,b) ((((a)<<5)|(b))<<11)
373 #define LR SPR(8, 0)
374 #define CTR SPR(9, 0)
375
376 #define SLW XO31( 24)
377 #define SRW XO31(536)
378 #define SRAW XO31(792)
379
380 #define SLD XO31( 27)
381 #define SRD XO31(539)
382 #define SRAD XO31(794)
383 #define SRADI XO31(413<<1)
384
385 #define TW XO31( 4)
386 #define TRAP (TW | TO (31))
387
388 #define RT(r) ((r)<<21)
389 #define RS(r) ((r)<<21)
390 #define RA(r) ((r)<<16)
391 #define RB(r) ((r)<<11)
392 #define TO(t) ((t)<<21)
393 #define SH(s) ((s)<<11)
394 #define MB(b) ((b)<<6)
395 #define ME(e) ((e)<<1)
396 #define BO(o) ((o)<<21)
397 #define MB64(b) ((b)<<5)
398
399 #define LK 1
400
401 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
402 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
403
404 #define BF(n) ((n)<<23)
405 #define BI(n, c) (((c)+((n)*4))<<16)
406 #define BT(n, c) (((c)+((n)*4))<<21)
407 #define BA(n, c) (((c)+((n)*4))<<16)
408 #define BB(n, c) (((c)+((n)*4))<<11)
409
410 #define BO_COND_TRUE BO (12)
411 #define BO_COND_FALSE BO ( 4)
412 #define BO_ALWAYS BO (20)
413
414 enum {
415 CR_LT,
416 CR_GT,
417 CR_EQ,
418 CR_SO
419 };
420
421 static const uint32_t tcg_to_bc[] = {
422 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
423 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
424 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
425 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
426 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
427 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
428 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
429 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
430 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
431 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
432 };
433
434 static void tcg_out_mov (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
435 {
436 tcg_out32 (s, OR | SAB (arg, ret, arg));
437 }
438
439 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
440 {
441 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
442 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
443 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
444 }
445
446 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
447 {
448 if (arg == (int16_t) arg)
449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
450 else {
451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
452 if (arg & 0xffff)
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
454 }
455 }
456
457 static void tcg_out_movi (TCGContext *s, TCGType type,
458 TCGReg ret, tcg_target_long arg)
459 {
460 int32_t arg32 = arg;
461 arg = type == TCG_TYPE_I32 ? arg & 0xffffffff : arg;
462
463 if (arg == arg32) {
464 tcg_out_movi32 (s, ret, arg32);
465 }
466 else {
467 if ((uint64_t) arg >> 32) {
468 uint16_t h16 = arg >> 16;
469 uint16_t l16 = arg;
470
471 tcg_out_movi32 (s, ret, arg >> 32);
472 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
473 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
474 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
475 }
476 else {
477 tcg_out_movi32 (s, ret, arg32);
478 if (arg32 < 0)
479 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
480 }
481 }
482 }
483
484 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
485 {
486 tcg_target_long disp;
487
488 disp = target - (tcg_target_long) s->code_ptr;
489 if ((disp << 38) >> 38 == disp)
490 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
491 else {
492 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
493 tcg_out32 (s, MTSPR | RS (0) | CTR);
494 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
495 }
496 }
497
498 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
499 {
500 #ifdef __APPLE__
501 if (const_arg) {
502 tcg_out_b (s, LK, arg);
503 }
504 else {
505 tcg_out32 (s, MTSPR | RS (arg) | LR);
506 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
507 }
508 #else
509 int reg;
510
511 if (const_arg) {
512 reg = 2;
513 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
514 }
515 else reg = arg;
516
517 tcg_out32 (s, LD | RT (0) | RA (reg));
518 tcg_out32 (s, MTSPR | RA (0) | CTR);
519 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
520 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
521 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
522 #endif
523 }
524
525 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
526 int offset, int op1, int op2)
527 {
528 if (offset == (int16_t) offset)
529 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
530 else {
531 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
532 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
533 }
534 }
535
536 static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
537 int offset, int op1, int op2)
538 {
539 if (offset == (int16_t) (offset & ~3))
540 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
541 else {
542 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
543 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
544 }
545 }
546
547 #if defined (CONFIG_SOFTMMU)
548
549 #include "exec/softmmu_defs.h"
550
551 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
552 int mmu_idx) */
553 static const void * const qemu_ld_helpers[4] = {
554 helper_ldb_mmu,
555 helper_ldw_mmu,
556 helper_ldl_mmu,
557 helper_ldq_mmu,
558 };
559
560 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
561 uintxx_t val, int mmu_idx) */
562 static const void * const qemu_st_helpers[4] = {
563 helper_stb_mmu,
564 helper_stw_mmu,
565 helper_stl_mmu,
566 helper_stq_mmu,
567 };
568
569 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
570 int addr_reg, int s_bits, int offset)
571 {
572 #if TARGET_LONG_BITS == 32
573 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
574
575 tcg_out32 (s, (RLWINM
576 | RA (r0)
577 | RS (addr_reg)
578 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
579 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
580 | ME (31 - CPU_TLB_ENTRY_BITS)
581 )
582 );
583 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
584 tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
585 tcg_out32 (s, (RLWINM
586 | RA (r2)
587 | RS (addr_reg)
588 | SH (0)
589 | MB ((32 - s_bits) & 31)
590 | ME (31 - TARGET_PAGE_BITS)
591 )
592 );
593 #else
594 tcg_out_rld (s, RLDICL, r0, addr_reg,
595 64 - TARGET_PAGE_BITS,
596 64 - CPU_TLB_BITS);
597 tcg_out_rld (s, RLDICR, r0, r0,
598 CPU_TLB_ENTRY_BITS,
599 63 - CPU_TLB_ENTRY_BITS);
600
601 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
602 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
603
604 if (!s_bits) {
605 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
606 }
607 else {
608 tcg_out_rld (s, RLDICL, r2, addr_reg,
609 64 - TARGET_PAGE_BITS,
610 TARGET_PAGE_BITS - s_bits);
611 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
612 }
613 #endif
614 }
615 #endif
616
617 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
618 {
619 int addr_reg, data_reg, r0, r1, rbase, bswap;
620 #ifdef CONFIG_SOFTMMU
621 int r2, mem_index, s_bits, ir;
622 void *label1_ptr, *label2_ptr;
623 #endif
624
625 data_reg = *args++;
626 addr_reg = *args++;
627
628 #ifdef CONFIG_SOFTMMU
629 mem_index = *args;
630 s_bits = opc & 3;
631
632 r0 = 3;
633 r1 = 4;
634 r2 = 0;
635 rbase = 0;
636
637 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
638 offsetof (CPUArchState, tlb_table[mem_index][0].addr_read));
639
640 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
641
642 label1_ptr = s->code_ptr;
643 #ifdef FAST_PATH
644 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
645 #endif
646
647 /* slow path */
648 ir = 3;
649 tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
650 tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
651 tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
652
653 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
654
655 switch (opc) {
656 case 0|4:
657 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
658 break;
659 case 1|4:
660 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
661 break;
662 case 2|4:
663 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
664 break;
665 case 0:
666 case 1:
667 case 2:
668 case 3:
669 if (data_reg != 3)
670 tcg_out_mov (s, TCG_TYPE_I64, data_reg, 3);
671 break;
672 }
673 label2_ptr = s->code_ptr;
674 tcg_out32 (s, B);
675
676 /* label1: fast path */
677 #ifdef FAST_PATH
678 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
679 #endif
680
681 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
682 tcg_out32 (s, (LD
683 | RT (r0)
684 | RA (r0)
685 | (offsetof (CPUTLBEntry, addend)
686 - offsetof (CPUTLBEntry, addr_read))
687 ));
688 /* r0 = env->tlb_table[mem_index][index].addend */
689 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
690 /* r0 = env->tlb_table[mem_index][index].addend + addr */
691
692 #else /* !CONFIG_SOFTMMU */
693 #if TARGET_LONG_BITS == 32
694 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
695 #endif
696 r0 = addr_reg;
697 r1 = 3;
698 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
699 #endif
700
701 #ifdef TARGET_WORDS_BIGENDIAN
702 bswap = 0;
703 #else
704 bswap = 1;
705 #endif
706 switch (opc) {
707 default:
708 case 0:
709 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
710 break;
711 case 0|4:
712 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
713 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
714 break;
715 case 1:
716 if (bswap)
717 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
718 else
719 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
720 break;
721 case 1|4:
722 if (bswap) {
723 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
724 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
725 }
726 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
727 break;
728 case 2:
729 if (bswap)
730 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
731 else
732 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
733 break;
734 case 2|4:
735 if (bswap) {
736 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
737 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
738 }
739 else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
740 break;
741 case 3:
742 #ifdef CONFIG_USE_GUEST_BASE
743 if (bswap) {
744 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
745 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
746 tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1));
747 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
748 }
749 else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
750 #else
751 if (bswap) {
752 tcg_out_movi32 (s, 0, 4);
753 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
754 tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
755 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
756 }
757 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
758 #endif
759 break;
760 }
761
762 #ifdef CONFIG_SOFTMMU
763 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
764 #endif
765 }
766
767 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
768 {
769 int addr_reg, r0, r1, rbase, data_reg, bswap;
770 #ifdef CONFIG_SOFTMMU
771 int r2, mem_index, ir;
772 void *label1_ptr, *label2_ptr;
773 #endif
774
775 data_reg = *args++;
776 addr_reg = *args++;
777
778 #ifdef CONFIG_SOFTMMU
779 mem_index = *args;
780
781 r0 = 3;
782 r1 = 4;
783 r2 = 0;
784 rbase = 0;
785
786 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
787 offsetof (CPUArchState, tlb_table[mem_index][0].addr_write));
788
789 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
790
791 label1_ptr = s->code_ptr;
792 #ifdef FAST_PATH
793 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
794 #endif
795
796 /* slow path */
797 ir = 3;
798 tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
799 tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
800 tcg_out_rld (s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc)));
801 tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
802
803 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
804
805 label2_ptr = s->code_ptr;
806 tcg_out32 (s, B);
807
808 /* label1: fast path */
809 #ifdef FAST_PATH
810 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
811 #endif
812
813 tcg_out32 (s, (LD
814 | RT (r0)
815 | RA (r0)
816 | (offsetof (CPUTLBEntry, addend)
817 - offsetof (CPUTLBEntry, addr_write))
818 ));
819 /* r0 = env->tlb_table[mem_index][index].addend */
820 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
821 /* r0 = env->tlb_table[mem_index][index].addend + addr */
822
823 #else /* !CONFIG_SOFTMMU */
824 #if TARGET_LONG_BITS == 32
825 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
826 #endif
827 r1 = 3;
828 r0 = addr_reg;
829 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
830 #endif
831
832 #ifdef TARGET_WORDS_BIGENDIAN
833 bswap = 0;
834 #else
835 bswap = 1;
836 #endif
837 switch (opc) {
838 case 0:
839 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
840 break;
841 case 1:
842 if (bswap)
843 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
844 else
845 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
846 break;
847 case 2:
848 if (bswap)
849 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
850 else
851 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
852 break;
853 case 3:
854 if (bswap) {
855 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
856 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
857 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
858 tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
859 }
860 else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
861 break;
862 }
863
864 #ifdef CONFIG_SOFTMMU
865 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
866 #endif
867 }
868
869 static void tcg_target_qemu_prologue (TCGContext *s)
870 {
871 int i, frame_size;
872 #ifndef __APPLE__
873 uint64_t addr;
874 #endif
875
876 frame_size = 0
877 + 8 /* back chain */
878 + 8 /* CR */
879 + 8 /* LR */
880 + 8 /* compiler doubleword */
881 + 8 /* link editor doubleword */
882 + 8 /* TOC save area */
883 + TCG_STATIC_CALL_ARGS_SIZE
884 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
885 + CPU_TEMP_BUF_NLONGS * sizeof(long)
886 ;
887 frame_size = (frame_size + 15) & ~15;
888
889 tcg_set_frame (s, TCG_REG_CALL_STACK, frame_size
890 - CPU_TEMP_BUF_NLONGS * sizeof (long),
891 CPU_TEMP_BUF_NLONGS * sizeof (long));
892
893 #ifndef __APPLE__
894 /* First emit adhoc function descriptor */
895 addr = (uint64_t) s->code_ptr + 24;
896 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
897 s->code_ptr += 16; /* skip TOC and environment pointer */
898 #endif
899
900 /* Prologue */
901 tcg_out32 (s, MFSPR | RT (0) | LR);
902 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
903 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
904 tcg_out32 (s, (STD
905 | RS (tcg_target_callee_save_regs[i])
906 | RA (1)
907 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
908 )
909 );
910 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
911
912 #ifdef CONFIG_USE_GUEST_BASE
913 if (GUEST_BASE) {
914 tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
915 tcg_regset_set_reg (s->reserved_regs, TCG_GUEST_BASE_REG);
916 }
917 #endif
918
919 tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
920 tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
921 tcg_out32 (s, BCCTR | BO_ALWAYS);
922
923 /* Epilogue */
924 tb_ret_addr = s->code_ptr;
925
926 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
927 tcg_out32 (s, (LD
928 | RT (tcg_target_callee_save_regs[i])
929 | RA (1)
930 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
931 )
932 );
933 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
934 tcg_out32 (s, MTSPR | RS (0) | LR);
935 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
936 tcg_out32 (s, BCLR | BO_ALWAYS);
937 }
938
939 static void tcg_out_ld (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
940 tcg_target_long arg2)
941 {
942 if (type == TCG_TYPE_I32)
943 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
944 else
945 tcg_out_ldsta (s, ret, arg1, arg2, LD, LDX);
946 }
947
948 static void tcg_out_st (TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
949 tcg_target_long arg2)
950 {
951 if (type == TCG_TYPE_I32)
952 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
953 else
954 tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX);
955 }
956
957 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
958 {
959 if (!si && rt == ra)
960 return;
961
962 if (si == (int16_t) si)
963 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
964 else {
965 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
966 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
967 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
968 }
969 }
970
971 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
972 {
973 /* XXX: suboptimal */
974 if (si == (int16_t) si
975 || ((((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0))
976 ppc_addi32 (s, rt, ra, si);
977 else {
978 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
979 tcg_out32 (s, ADD | RT (rt) | RA (ra));
980 }
981 }
982
983 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
984 int const_arg2, int cr, int arch64)
985 {
986 int imm;
987 uint32_t op;
988
989 switch (cond) {
990 case TCG_COND_EQ:
991 case TCG_COND_NE:
992 if (const_arg2) {
993 if ((int16_t) arg2 == arg2) {
994 op = CMPI;
995 imm = 1;
996 break;
997 }
998 else if ((uint16_t) arg2 == arg2) {
999 op = CMPLI;
1000 imm = 1;
1001 break;
1002 }
1003 }
1004 op = CMPL;
1005 imm = 0;
1006 break;
1007
1008 case TCG_COND_LT:
1009 case TCG_COND_GE:
1010 case TCG_COND_LE:
1011 case TCG_COND_GT:
1012 if (const_arg2) {
1013 if ((int16_t) arg2 == arg2) {
1014 op = CMPI;
1015 imm = 1;
1016 break;
1017 }
1018 }
1019 op = CMP;
1020 imm = 0;
1021 break;
1022
1023 case TCG_COND_LTU:
1024 case TCG_COND_GEU:
1025 case TCG_COND_LEU:
1026 case TCG_COND_GTU:
1027 if (const_arg2) {
1028 if ((uint16_t) arg2 == arg2) {
1029 op = CMPLI;
1030 imm = 1;
1031 break;
1032 }
1033 }
1034 op = CMPL;
1035 imm = 0;
1036 break;
1037
1038 default:
1039 tcg_abort ();
1040 }
1041 op |= BF (cr) | (arch64 << 21);
1042
1043 if (imm)
1044 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1045 else {
1046 if (const_arg2) {
1047 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
1048 tcg_out32 (s, op | RA (arg1) | RB (0));
1049 }
1050 else
1051 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1052 }
1053
1054 }
1055
1056 static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond,
1057 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1058 int const_arg2)
1059 {
1060 int crop, sh, arg;
1061
1062 switch (cond) {
1063 case TCG_COND_EQ:
1064 if (const_arg2) {
1065 if (!arg2) {
1066 arg = arg1;
1067 }
1068 else {
1069 arg = 0;
1070 if ((uint16_t) arg2 == arg2) {
1071 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1072 }
1073 else {
1074 tcg_out_movi (s, type, 0, arg2);
1075 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1076 }
1077 }
1078 }
1079 else {
1080 arg = 0;
1081 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1082 }
1083
1084 if (type == TCG_TYPE_I64) {
1085 tcg_out32 (s, CNTLZD | RS (arg) | RA (0));
1086 tcg_out_rld (s, RLDICL, arg0, 0, 58, 6);
1087 }
1088 else {
1089 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1090 tcg_out32 (s, (RLWINM
1091 | RA (arg0)
1092 | RS (0)
1093 | SH (27)
1094 | MB (5)
1095 | ME (31)
1096 )
1097 );
1098 }
1099 break;
1100
1101 case TCG_COND_NE:
1102 if (const_arg2) {
1103 if (!arg2) {
1104 arg = arg1;
1105 }
1106 else {
1107 arg = 0;
1108 if ((uint16_t) arg2 == arg2) {
1109 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1110 }
1111 else {
1112 tcg_out_movi (s, type, 0, arg2);
1113 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1114 }
1115 }
1116 }
1117 else {
1118 arg = 0;
1119 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1120 }
1121
1122 if (arg == arg1 && arg1 == arg0) {
1123 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1124 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1125 }
1126 else {
1127 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1128 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1129 }
1130 break;
1131
1132 case TCG_COND_GT:
1133 case TCG_COND_GTU:
1134 sh = 30;
1135 crop = 0;
1136 goto crtest;
1137
1138 case TCG_COND_LT:
1139 case TCG_COND_LTU:
1140 sh = 29;
1141 crop = 0;
1142 goto crtest;
1143
1144 case TCG_COND_GE:
1145 case TCG_COND_GEU:
1146 sh = 31;
1147 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1148 goto crtest;
1149
1150 case TCG_COND_LE:
1151 case TCG_COND_LEU:
1152 sh = 31;
1153 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1154 crtest:
1155 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type == TCG_TYPE_I64);
1156 if (crop) tcg_out32 (s, crop);
1157 tcg_out32 (s, MFCR | RT (0));
1158 tcg_out32 (s, (RLWINM
1159 | RA (arg0)
1160 | RS (0)
1161 | SH (sh)
1162 | MB (31)
1163 | ME (31)
1164 )
1165 );
1166 break;
1167
1168 default:
1169 tcg_abort ();
1170 }
1171 }
1172
1173 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1174 {
1175 TCGLabel *l = &s->labels[label_index];
1176
1177 if (l->has_value)
1178 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1179 else {
1180 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1181
1182 /* Thanks to Andrzej Zaborowski */
1183 tcg_out32 (s, bc | (val & 0xfffc));
1184 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1185 }
1186 }
1187
1188 static void tcg_out_brcond (TCGContext *s, TCGCond cond,
1189 TCGArg arg1, TCGArg arg2, int const_arg2,
1190 int label_index, int arch64)
1191 {
1192 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
1193 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1194 }
1195
1196 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1197 {
1198 TCGContext s;
1199 unsigned long patch_size;
1200
1201 s.code_ptr = (uint8_t *) jmp_addr;
1202 tcg_out_b (&s, 0, addr);
1203 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1204 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1205 }
1206
1207 static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
1208 const int *const_args)
1209 {
1210 int c;
1211
1212 switch (opc) {
1213 case INDEX_op_exit_tb:
1214 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1215 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1216 break;
1217 case INDEX_op_goto_tb:
1218 if (s->tb_jmp_offset) {
1219 /* direct jump method */
1220
1221 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1222 s->code_ptr += 28;
1223 }
1224 else {
1225 tcg_abort ();
1226 }
1227 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1228 break;
1229 case INDEX_op_br:
1230 {
1231 TCGLabel *l = &s->labels[args[0]];
1232
1233 if (l->has_value) {
1234 tcg_out_b (s, 0, l->u.value);
1235 }
1236 else {
1237 uint32_t val = *(uint32_t *) s->code_ptr;
1238
1239 /* Thanks to Andrzej Zaborowski */
1240 tcg_out32 (s, B | (val & 0x3fffffc));
1241 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1242 }
1243 }
1244 break;
1245 case INDEX_op_call:
1246 tcg_out_call (s, args[0], const_args[0]);
1247 break;
1248 case INDEX_op_movi_i32:
1249 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1250 break;
1251 case INDEX_op_movi_i64:
1252 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1253 break;
1254 case INDEX_op_ld8u_i32:
1255 case INDEX_op_ld8u_i64:
1256 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1257 break;
1258 case INDEX_op_ld8s_i32:
1259 case INDEX_op_ld8s_i64:
1260 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1261 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1262 break;
1263 case INDEX_op_ld16u_i32:
1264 case INDEX_op_ld16u_i64:
1265 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1266 break;
1267 case INDEX_op_ld16s_i32:
1268 case INDEX_op_ld16s_i64:
1269 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1270 break;
1271 case INDEX_op_ld_i32:
1272 case INDEX_op_ld32u_i64:
1273 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1274 break;
1275 case INDEX_op_ld32s_i64:
1276 tcg_out_ldsta (s, args[0], args[1], args[2], LWA, LWAX);
1277 break;
1278 case INDEX_op_ld_i64:
1279 tcg_out_ldsta (s, args[0], args[1], args[2], LD, LDX);
1280 break;
1281 case INDEX_op_st8_i32:
1282 case INDEX_op_st8_i64:
1283 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1284 break;
1285 case INDEX_op_st16_i32:
1286 case INDEX_op_st16_i64:
1287 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1288 break;
1289 case INDEX_op_st_i32:
1290 case INDEX_op_st32_i64:
1291 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1292 break;
1293 case INDEX_op_st_i64:
1294 tcg_out_ldsta (s, args[0], args[1], args[2], STD, STDX);
1295 break;
1296
1297 case INDEX_op_add_i32:
1298 if (const_args[2])
1299 ppc_addi32 (s, args[0], args[1], args[2]);
1300 else
1301 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1302 break;
1303 case INDEX_op_sub_i32:
1304 if (const_args[2])
1305 ppc_addi32 (s, args[0], args[1], -args[2]);
1306 else
1307 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1308 break;
1309
1310 case INDEX_op_and_i64:
1311 case INDEX_op_and_i32:
1312 if (const_args[2]) {
1313 if ((args[2] & 0xffff) == args[2])
1314 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1315 else if ((args[2] & 0xffff0000) == args[2])
1316 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1317 | ((args[2] >> 16) & 0xffff));
1318 else {
1319 tcg_out_movi (s, (opc == INDEX_op_and_i32
1320 ? TCG_TYPE_I32
1321 : TCG_TYPE_I64),
1322 0, args[2]);
1323 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1324 }
1325 }
1326 else
1327 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1328 break;
1329 case INDEX_op_or_i64:
1330 case INDEX_op_or_i32:
1331 if (const_args[2]) {
1332 if (args[2] & 0xffff) {
1333 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1334 | (args[2] & 0xffff));
1335 if (args[2] >> 16)
1336 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1337 | ((args[2] >> 16) & 0xffff));
1338 }
1339 else {
1340 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1341 | ((args[2] >> 16) & 0xffff));
1342 }
1343 }
1344 else
1345 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1346 break;
1347 case INDEX_op_xor_i64:
1348 case INDEX_op_xor_i32:
1349 if (const_args[2]) {
1350 if ((args[2] & 0xffff) == args[2])
1351 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1352 | (args[2] & 0xffff));
1353 else if ((args[2] & 0xffff0000) == args[2])
1354 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1355 | ((args[2] >> 16) & 0xffff));
1356 else {
1357 tcg_out_movi (s, (opc == INDEX_op_and_i32
1358 ? TCG_TYPE_I32
1359 : TCG_TYPE_I64),
1360 0, args[2]);
1361 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1362 }
1363 }
1364 else
1365 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1366 break;
1367
1368 case INDEX_op_mul_i32:
1369 if (const_args[2]) {
1370 if (args[2] == (int16_t) args[2])
1371 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1372 | (args[2] & 0xffff));
1373 else {
1374 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1375 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1376 }
1377 }
1378 else
1379 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1380 break;
1381
1382 case INDEX_op_div_i32:
1383 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1384 break;
1385
1386 case INDEX_op_divu_i32:
1387 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1388 break;
1389
1390 case INDEX_op_rem_i32:
1391 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1392 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1393 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1394 break;
1395
1396 case INDEX_op_remu_i32:
1397 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1398 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1399 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1400 break;
1401
1402 case INDEX_op_shl_i32:
1403 if (const_args[2]) {
1404 tcg_out32 (s, (RLWINM
1405 | RA (args[0])
1406 | RS (args[1])
1407 | SH (args[2])
1408 | MB (0)
1409 | ME (31 - args[2])
1410 )
1411 );
1412 }
1413 else
1414 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1415 break;
1416 case INDEX_op_shr_i32:
1417 if (const_args[2]) {
1418 tcg_out32 (s, (RLWINM
1419 | RA (args[0])
1420 | RS (args[1])
1421 | SH (32 - args[2])
1422 | MB (args[2])
1423 | ME (31)
1424 )
1425 );
1426 }
1427 else
1428 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1429 break;
1430 case INDEX_op_sar_i32:
1431 if (const_args[2])
1432 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1433 else
1434 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1435 break;
1436
1437 case INDEX_op_brcond_i32:
1438 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
1439 break;
1440
1441 case INDEX_op_brcond_i64:
1442 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
1443 break;
1444
1445 case INDEX_op_neg_i32:
1446 case INDEX_op_neg_i64:
1447 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1448 break;
1449
1450 case INDEX_op_not_i32:
1451 case INDEX_op_not_i64:
1452 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
1453 break;
1454
1455 case INDEX_op_add_i64:
1456 if (const_args[2])
1457 ppc_addi64 (s, args[0], args[1], args[2]);
1458 else
1459 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1460 break;
1461 case INDEX_op_sub_i64:
1462 if (const_args[2])
1463 ppc_addi64 (s, args[0], args[1], -args[2]);
1464 else
1465 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1466 break;
1467
1468 case INDEX_op_shl_i64:
1469 if (const_args[2])
1470 tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
1471 else
1472 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1473 break;
1474 case INDEX_op_shr_i64:
1475 if (const_args[2])
1476 tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
1477 else
1478 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1479 break;
1480 case INDEX_op_sar_i64:
1481 if (const_args[2]) {
1482 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1483 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1484 }
1485 else
1486 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1487 break;
1488
1489 case INDEX_op_mul_i64:
1490 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1491 break;
1492 case INDEX_op_div_i64:
1493 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1494 break;
1495 case INDEX_op_divu_i64:
1496 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1497 break;
1498 case INDEX_op_rem_i64:
1499 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1500 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1501 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1502 break;
1503 case INDEX_op_remu_i64:
1504 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1505 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1506 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1507 break;
1508
1509 case INDEX_op_qemu_ld8u:
1510 tcg_out_qemu_ld (s, args, 0);
1511 break;
1512 case INDEX_op_qemu_ld8s:
1513 tcg_out_qemu_ld (s, args, 0 | 4);
1514 break;
1515 case INDEX_op_qemu_ld16u:
1516 tcg_out_qemu_ld (s, args, 1);
1517 break;
1518 case INDEX_op_qemu_ld16s:
1519 tcg_out_qemu_ld (s, args, 1 | 4);
1520 break;
1521 case INDEX_op_qemu_ld32:
1522 case INDEX_op_qemu_ld32u:
1523 tcg_out_qemu_ld (s, args, 2);
1524 break;
1525 case INDEX_op_qemu_ld32s:
1526 tcg_out_qemu_ld (s, args, 2 | 4);
1527 break;
1528 case INDEX_op_qemu_ld64:
1529 tcg_out_qemu_ld (s, args, 3);
1530 break;
1531 case INDEX_op_qemu_st8:
1532 tcg_out_qemu_st (s, args, 0);
1533 break;
1534 case INDEX_op_qemu_st16:
1535 tcg_out_qemu_st (s, args, 1);
1536 break;
1537 case INDEX_op_qemu_st32:
1538 tcg_out_qemu_st (s, args, 2);
1539 break;
1540 case INDEX_op_qemu_st64:
1541 tcg_out_qemu_st (s, args, 3);
1542 break;
1543
1544 case INDEX_op_ext8s_i32:
1545 case INDEX_op_ext8s_i64:
1546 c = EXTSB;
1547 goto gen_ext;
1548 case INDEX_op_ext16s_i32:
1549 case INDEX_op_ext16s_i64:
1550 c = EXTSH;
1551 goto gen_ext;
1552 case INDEX_op_ext32s_i64:
1553 c = EXTSW;
1554 goto gen_ext;
1555 gen_ext:
1556 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1557 break;
1558
1559 case INDEX_op_ext32u_i64:
1560 tcg_out_rld (s, RLDICL, args[0], args[1], 0, 32);
1561 break;
1562
1563 case INDEX_op_setcond_i32:
1564 tcg_out_setcond (s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1565 const_args[2]);
1566 break;
1567 case INDEX_op_setcond_i64:
1568 tcg_out_setcond (s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1569 const_args[2]);
1570 break;
1571
1572 default:
1573 tcg_dump_ops (s);
1574 tcg_abort ();
1575 }
1576 }
1577
1578 static const TCGTargetOpDef ppc_op_defs[] = {
1579 { INDEX_op_exit_tb, { } },
1580 { INDEX_op_goto_tb, { } },
1581 { INDEX_op_call, { "ri" } },
1582 { INDEX_op_br, { } },
1583
1584 { INDEX_op_mov_i32, { "r", "r" } },
1585 { INDEX_op_mov_i64, { "r", "r" } },
1586 { INDEX_op_movi_i32, { "r" } },
1587 { INDEX_op_movi_i64, { "r" } },
1588
1589 { INDEX_op_ld8u_i32, { "r", "r" } },
1590 { INDEX_op_ld8s_i32, { "r", "r" } },
1591 { INDEX_op_ld16u_i32, { "r", "r" } },
1592 { INDEX_op_ld16s_i32, { "r", "r" } },
1593 { INDEX_op_ld_i32, { "r", "r" } },
1594 { INDEX_op_ld_i64, { "r", "r" } },
1595 { INDEX_op_st8_i32, { "r", "r" } },
1596 { INDEX_op_st8_i64, { "r", "r" } },
1597 { INDEX_op_st16_i32, { "r", "r" } },
1598 { INDEX_op_st16_i64, { "r", "r" } },
1599 { INDEX_op_st_i32, { "r", "r" } },
1600 { INDEX_op_st_i64, { "r", "r" } },
1601 { INDEX_op_st32_i64, { "r", "r" } },
1602
1603 { INDEX_op_ld8u_i64, { "r", "r" } },
1604 { INDEX_op_ld8s_i64, { "r", "r" } },
1605 { INDEX_op_ld16u_i64, { "r", "r" } },
1606 { INDEX_op_ld16s_i64, { "r", "r" } },
1607 { INDEX_op_ld32u_i64, { "r", "r" } },
1608 { INDEX_op_ld32s_i64, { "r", "r" } },
1609
1610 { INDEX_op_add_i32, { "r", "r", "ri" } },
1611 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1612 { INDEX_op_div_i32, { "r", "r", "r" } },
1613 { INDEX_op_divu_i32, { "r", "r", "r" } },
1614 { INDEX_op_rem_i32, { "r", "r", "r" } },
1615 { INDEX_op_remu_i32, { "r", "r", "r" } },
1616 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1617 { INDEX_op_and_i32, { "r", "r", "ri" } },
1618 { INDEX_op_or_i32, { "r", "r", "ri" } },
1619 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1620
1621 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1622 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1623 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1624
1625 { INDEX_op_brcond_i32, { "r", "ri" } },
1626 { INDEX_op_brcond_i64, { "r", "ri" } },
1627
1628 { INDEX_op_neg_i32, { "r", "r" } },
1629 { INDEX_op_not_i32, { "r", "r" } },
1630
1631 { INDEX_op_add_i64, { "r", "r", "ri" } },
1632 { INDEX_op_sub_i64, { "r", "r", "ri" } },
1633 { INDEX_op_and_i64, { "r", "r", "rZ" } },
1634 { INDEX_op_or_i64, { "r", "r", "rZ" } },
1635 { INDEX_op_xor_i64, { "r", "r", "rZ" } },
1636
1637 { INDEX_op_shl_i64, { "r", "r", "ri" } },
1638 { INDEX_op_shr_i64, { "r", "r", "ri" } },
1639 { INDEX_op_sar_i64, { "r", "r", "ri" } },
1640
1641 { INDEX_op_mul_i64, { "r", "r", "r" } },
1642 { INDEX_op_div_i64, { "r", "r", "r" } },
1643 { INDEX_op_divu_i64, { "r", "r", "r" } },
1644 { INDEX_op_rem_i64, { "r", "r", "r" } },
1645 { INDEX_op_remu_i64, { "r", "r", "r" } },
1646
1647 { INDEX_op_neg_i64, { "r", "r" } },
1648 { INDEX_op_not_i64, { "r", "r" } },
1649
1650 { INDEX_op_qemu_ld8u, { "r", "L" } },
1651 { INDEX_op_qemu_ld8s, { "r", "L" } },
1652 { INDEX_op_qemu_ld16u, { "r", "L" } },
1653 { INDEX_op_qemu_ld16s, { "r", "L" } },
1654 { INDEX_op_qemu_ld32, { "r", "L" } },
1655 { INDEX_op_qemu_ld32u, { "r", "L" } },
1656 { INDEX_op_qemu_ld32s, { "r", "L" } },
1657 { INDEX_op_qemu_ld64, { "r", "L" } },
1658
1659 { INDEX_op_qemu_st8, { "S", "S" } },
1660 { INDEX_op_qemu_st16, { "S", "S" } },
1661 { INDEX_op_qemu_st32, { "S", "S" } },
1662 { INDEX_op_qemu_st64, { "S", "S" } },
1663
1664 { INDEX_op_ext8s_i32, { "r", "r" } },
1665 { INDEX_op_ext16s_i32, { "r", "r" } },
1666 { INDEX_op_ext8s_i64, { "r", "r" } },
1667 { INDEX_op_ext16s_i64, { "r", "r" } },
1668 { INDEX_op_ext32s_i64, { "r", "r" } },
1669 { INDEX_op_ext32u_i64, { "r", "r" } },
1670
1671 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1672 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
1673
1674 { -1 },
1675 };
1676
1677 static void tcg_target_init (TCGContext *s)
1678 {
1679 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1680 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1681 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1682 (1 << TCG_REG_R0) |
1683 #ifdef __APPLE__
1684 (1 << TCG_REG_R2) |
1685 #endif
1686 (1 << TCG_REG_R3) |
1687 (1 << TCG_REG_R4) |
1688 (1 << TCG_REG_R5) |
1689 (1 << TCG_REG_R6) |
1690 (1 << TCG_REG_R7) |
1691 (1 << TCG_REG_R8) |
1692 (1 << TCG_REG_R9) |
1693 (1 << TCG_REG_R10) |
1694 (1 << TCG_REG_R11) |
1695 (1 << TCG_REG_R12)
1696 );
1697
1698 tcg_regset_clear (s->reserved_regs);
1699 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1700 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1701 #ifndef __APPLE__
1702 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1703 #endif
1704 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1705
1706 tcg_add_target_add_op_defs (ppc_op_defs);
1707 }
Patch queue for openSUSE QEMU