hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licensed under the GNU GPL v2.
   7  *
   8  * Contributions after 2012-01-13 are licensed under the terms of the
   9  * GNU GPL, version 2 or (at your option) any later version.
  10  */
  11
  12 #include "sysbus.h"
  13 #include "arm-misc.h"
  14 #include "devices.h"
  15 #include "net.h"
  16 #include "sysemu.h"
  17 #include "boards.h"
  18 #include "pc.h"
  19 #include "qemu-timer.h"
  20 #include "ptimer.h"
  21 #include "block.h"
  22 #include "flash.h"
  23 #include "console.h"
  24 #include "i2c.h"
  25 #include "blockdev.h"
  26 #include "exec-memory.h"
  27
  28 #define MP_MISC_BASE            0x80002000
  29 #define MP_MISC_SIZE            0x00001000
  30
  31 #define MP_ETH_BASE             0x80008000
  32 #define MP_ETH_SIZE             0x00001000
  33
  34 #define MP_WLAN_BASE            0x8000C000
  35 #define MP_WLAN_SIZE            0x00000800
  36
  37 #define MP_UART1_BASE           0x8000C840
  38 #define MP_UART2_BASE           0x8000C940
  39
  40 #define MP_GPIO_BASE            0x8000D000
  41 #define MP_GPIO_SIZE            0x00001000
  42
  43 #define MP_FLASHCFG_BASE        0x90006000
  44 #define MP_FLASHCFG_SIZE        0x00001000
  45
  46 #define MP_AUDIO_BASE           0x90007000
  47
  48 #define MP_PIC_BASE             0x90008000
  49 #define MP_PIC_SIZE             0x00001000
  50
  51 #define MP_PIT_BASE             0x90009000
  52 #define MP_PIT_SIZE             0x00001000
  53
  54 #define MP_LCD_BASE             0x9000c000
  55 #define MP_LCD_SIZE             0x00001000
  56
  57 #define MP_SRAM_BASE            0xC0000000
  58 #define MP_SRAM_SIZE            0x00020000
  59
  60 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  61 #define MP_FLASH_SIZE_MAX       32*1024*1024
  62
  63 #define MP_TIMER1_IRQ           4
  64 #define MP_TIMER2_IRQ           5
  65 #define MP_TIMER3_IRQ           6
  66 #define MP_TIMER4_IRQ           7
  67 #define MP_EHCI_IRQ             8
  68 #define MP_ETH_IRQ              9
  69 #define MP_UART1_IRQ            11
  70 #define MP_UART2_IRQ            11
  71 #define MP_GPIO_IRQ             12
  72 #define MP_RTC_IRQ              28
  73 #define MP_AUDIO_IRQ            30
  74
  75 /* Wolfson 8750 I2C address */
  76 #define MP_WM_ADDR              0x1A
  77
  78 /* Ethernet register offsets */
  79 #define MP_ETH_SMIR             0x010
  80 #define MP_ETH_PCXR             0x408
  81 #define MP_ETH_SDCMR            0x448
  82 #define MP_ETH_ICR              0x450
  83 #define MP_ETH_IMR              0x458
  84 #define MP_ETH_FRDP0            0x480
  85 #define MP_ETH_FRDP1            0x484
  86 #define MP_ETH_FRDP2            0x488
  87 #define MP_ETH_FRDP3            0x48C
  88 #define MP_ETH_CRDP0            0x4A0
  89 #define MP_ETH_CRDP1            0x4A4
  90 #define MP_ETH_CRDP2            0x4A8
  91 #define MP_ETH_CRDP3            0x4AC
  92 #define MP_ETH_CTDP0            0x4E0
  93 #define MP_ETH_CTDP1            0x4E4
  94 #define MP_ETH_CTDP2            0x4E8
  95 #define MP_ETH_CTDP3            0x4EC
  96
  97 /* MII PHY access */
  98 #define MP_ETH_SMIR_DATA        0x0000FFFF
  99 #define MP_ETH_SMIR_ADDR        0x03FF0000
 100 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 101 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 102
 103 /* PHY registers */
 104 #define MP_ETH_PHY1_BMSR        0x00210000
 105 #define MP_ETH_PHY1_PHYSID1     0x00410000
 106 #define MP_ETH_PHY1_PHYSID2     0x00610000
 107
 108 #define MP_PHY_BMSR_LINK        0x0004
 109 #define MP_PHY_BMSR_AUTONEG     0x0008
 110
 111 #define MP_PHY_88E3015          0x01410E20
 112
 113 /* TX descriptor status */
 114 #define MP_ETH_TX_OWN           (1 << 31)
 115
 116 /* RX descriptor status */
 117 #define MP_ETH_RX_OWN           (1 << 31)
 118
 119 /* Interrupt cause/mask bits */
 120 #define MP_ETH_IRQ_RX_BIT       0
 121 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 122 #define MP_ETH_IRQ_TXHI_BIT     2
 123 #define MP_ETH_IRQ_TXLO_BIT     3
 124
 125 /* Port config bits */
 126 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 127
 128 /* SDMA command bits */
 129 #define MP_ETH_CMD_TXHI         (1 << 23)
 130 #define MP_ETH_CMD_TXLO         (1 << 22)
 131
 132 typedef struct mv88w8618_tx_desc {
 133     uint32_t cmdstat;
 134     uint16_t res;
 135     uint16_t bytes;
 136     uint32_t buffer;
 137     uint32_t next;
 138 } mv88w8618_tx_desc;
 139
 140 typedef struct mv88w8618_rx_desc {
 141     uint32_t cmdstat;
 142     uint16_t bytes;
 143     uint16_t buffer_size;
 144     uint32_t buffer;
 145     uint32_t next;
 146 } mv88w8618_rx_desc;
 147
 148 typedef struct mv88w8618_eth_state {
 149     SysBusDevice busdev;
 150     MemoryRegion iomem;
 151     qemu_irq irq;
 152     uint32_t smir;
 153     uint32_t icr;
 154     uint32_t imr;
 155     int mmio_index;
 156     uint32_t vlan_header;
 157     uint32_t tx_queue[2];
 158     uint32_t rx_queue[4];
 159     uint32_t frx_queue[4];
 160     uint32_t cur_rx[4];
 161     NICState *nic;
 162     NICConf conf;
 163 } mv88w8618_eth_state;
 164
 165 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 166 {
 167     cpu_to_le32s(&desc->cmdstat);
 168     cpu_to_le16s(&desc->bytes);
 169     cpu_to_le16s(&desc->buffer_size);
 170     cpu_to_le32s(&desc->buffer);
 171     cpu_to_le32s(&desc->next);
 172     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 173 }
 174
 175 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 176 {
 177     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 178     le32_to_cpus(&desc->cmdstat);
 179     le16_to_cpus(&desc->bytes);
 180     le16_to_cpus(&desc->buffer_size);
 181     le32_to_cpus(&desc->buffer);
 182     le32_to_cpus(&desc->next);
 183 }
 184
 185 static int eth_can_receive(VLANClientState *nc)
 186 {
 187     return 1;
 188 }
 189
 190 static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
 191 {
 192     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 193     uint32_t desc_addr;
 194     mv88w8618_rx_desc desc;
 195     int i;
 196
 197     for (i = 0; i < 4; i++) {
 198         desc_addr = s->cur_rx[i];
 199         if (!desc_addr) {
 200             continue;
 201         }
 202         do {
 203             eth_rx_desc_get(desc_addr, &desc);
 204             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 205                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 206                                           buf, size);
 207                 desc.bytes = size + s->vlan_header;
 208                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 209                 s->cur_rx[i] = desc.next;
 210
 211                 s->icr |= MP_ETH_IRQ_RX;
 212                 if (s->icr & s->imr) {
 213                     qemu_irq_raise(s->irq);
 214                 }
 215                 eth_rx_desc_put(desc_addr, &desc);
 216                 return size;
 217             }
 218             desc_addr = desc.next;
 219         } while (desc_addr != s->rx_queue[i]);
 220     }
 221     return size;
 222 }
 223
 224 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 225 {
 226     cpu_to_le32s(&desc->cmdstat);
 227     cpu_to_le16s(&desc->res);
 228     cpu_to_le16s(&desc->bytes);
 229     cpu_to_le32s(&desc->buffer);
 230     cpu_to_le32s(&desc->next);
 231     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 232 }
 233
 234 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 235 {
 236     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 237     le32_to_cpus(&desc->cmdstat);
 238     le16_to_cpus(&desc->res);
 239     le16_to_cpus(&desc->bytes);
 240     le32_to_cpus(&desc->buffer);
 241     le32_to_cpus(&desc->next);
 242 }
 243
 244 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 245 {
 246     uint32_t desc_addr = s->tx_queue[queue_index];
 247     mv88w8618_tx_desc desc;
 248     uint32_t next_desc;
 249     uint8_t buf[2048];
 250     int len;
 251
 252     do {
 253         eth_tx_desc_get(desc_addr, &desc);
 254         next_desc = desc.next;
 255         if (desc.cmdstat & MP_ETH_TX_OWN) {
 256             len = desc.bytes;
 257             if (len < 2048) {
 258                 cpu_physical_memory_read(desc.buffer, buf, len);
 259                 qemu_send_packet(&s->nic->nc, buf, len);
 260             }
 261             desc.cmdstat &= ~MP_ETH_TX_OWN;
 262             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 263             eth_tx_desc_put(desc_addr, &desc);
 264         }
 265         desc_addr = next_desc;
 266     } while (desc_addr != s->tx_queue[queue_index]);
 267 }
 268
 269 static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
 270                                    unsigned size)
 271 {
 272     mv88w8618_eth_state *s = opaque;
 273
 274     switch (offset) {
 275     case MP_ETH_SMIR:
 276         if (s->smir & MP_ETH_SMIR_OPCODE) {
 277             switch (s->smir & MP_ETH_SMIR_ADDR) {
 278             case MP_ETH_PHY1_BMSR:
 279                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 280                        MP_ETH_SMIR_RDVALID;
 281             case MP_ETH_PHY1_PHYSID1:
 282                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 283             case MP_ETH_PHY1_PHYSID2:
 284                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 285             default:
 286                 return MP_ETH_SMIR_RDVALID;
 287             }
 288         }
 289         return 0;
 290
 291     case MP_ETH_ICR:
 292         return s->icr;
 293
 294     case MP_ETH_IMR:
 295         return s->imr;
 296
 297     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 298         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 299
 300     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 301         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 302
 303     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 304         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 305
 306     default:
 307         return 0;
 308     }
 309 }
 310
 311 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 312                                 uint64_t value, unsigned size)
 313 {
 314     mv88w8618_eth_state *s = opaque;
 315
 316     switch (offset) {
 317     case MP_ETH_SMIR:
 318         s->smir = value;
 319         break;
 320
 321     case MP_ETH_PCXR:
 322         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 323         break;
 324
 325     case MP_ETH_SDCMR:
 326         if (value & MP_ETH_CMD_TXHI) {
 327             eth_send(s, 1);
 328         }
 329         if (value & MP_ETH_CMD_TXLO) {
 330             eth_send(s, 0);
 331         }
 332         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 333             qemu_irq_raise(s->irq);
 334         }
 335         break;
 336
 337     case MP_ETH_ICR:
 338         s->icr &= value;
 339         break;
 340
 341     case MP_ETH_IMR:
 342         s->imr = value;
 343         if (s->icr & s->imr) {
 344             qemu_irq_raise(s->irq);
 345         }
 346         break;
 347
 348     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 349         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 350         break;
 351
 352     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 353         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 354             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 355         break;
 356
 357     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 358         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 359         break;
 360     }
 361 }
 362
 363 static const MemoryRegionOps mv88w8618_eth_ops = {
 364     .read = mv88w8618_eth_read,
 365     .write = mv88w8618_eth_write,
 366     .endianness = DEVICE_NATIVE_ENDIAN,
 367 };
 368
 369 static void eth_cleanup(VLANClientState *nc)
 370 {
 371     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 372
 373     s->nic = NULL;
 374 }
 375
 376 static NetClientInfo net_mv88w8618_info = {
 377     .type = NET_CLIENT_TYPE_NIC,
 378     .size = sizeof(NICState),
 379     .can_receive = eth_can_receive,
 380     .receive = eth_receive,
 381     .cleanup = eth_cleanup,
 382 };
 383
 384 static int mv88w8618_eth_init(SysBusDevice *dev)
 385 {
 386     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 387
 388     sysbus_init_irq(dev, &s->irq);
 389     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 390                           dev->qdev.info->name, dev->qdev.id, s);
 391     memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
 392                           MP_ETH_SIZE);
 393     sysbus_init_mmio(dev, &s->iomem);
 394     return 0;
 395 }
 396
 397 static const VMStateDescription mv88w8618_eth_vmsd = {
 398     .name = "mv88w8618_eth",
 399     .version_id = 1,
 400     .minimum_version_id = 1,
 401     .minimum_version_id_old = 1,
 402     .fields = (VMStateField[]) {
 403         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 404         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 405         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 406         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 407         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 408         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 409         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 410         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 411         VMSTATE_END_OF_LIST()
 412     }
 413 };
 414
 415 static SysBusDeviceInfo mv88w8618_eth_info = {
 416     .init = mv88w8618_eth_init,
 417     .qdev.name = "mv88w8618_eth",
 418     .qdev.size = sizeof(mv88w8618_eth_state),
 419     .qdev.vmsd = &mv88w8618_eth_vmsd,
 420     .qdev.props = (Property[]) {
 421         DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 422         DEFINE_PROP_END_OF_LIST(),
 423     },
 424 };
 425
 426 /* LCD register offsets */
 427 #define MP_LCD_IRQCTRL          0x180
 428 #define MP_LCD_IRQSTAT          0x184
 429 #define MP_LCD_SPICTRL          0x1ac
 430 #define MP_LCD_INST             0x1bc
 431 #define MP_LCD_DATA             0x1c0
 432
 433 /* Mode magics */
 434 #define MP_LCD_SPI_DATA         0x00100011
 435 #define MP_LCD_SPI_CMD          0x00104011
 436 #define MP_LCD_SPI_INVALID      0x00000000
 437
 438 /* Commmands */
 439 #define MP_LCD_INST_SETPAGE0    0xB0
 440 /* ... */
 441 #define MP_LCD_INST_SETPAGE7    0xB7
 442
 443 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 444
 445 typedef struct musicpal_lcd_state {
 446     SysBusDevice busdev;
 447     MemoryRegion iomem;
 448     uint32_t brightness;
 449     uint32_t mode;
 450     uint32_t irqctrl;
 451     uint32_t page;
 452     uint32_t page_off;
 453     DisplayState *ds;
 454     uint8_t video_ram[128*64/8];
 455 } musicpal_lcd_state;
 456
 457 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 458 {
 459     switch (s->brightness) {
 460     case 7:
 461         return col;
 462     case 0:
 463         return 0;
 464     default:
 465         return (col * s->brightness) / 7;
 466     }
 467 }
 468
 469 #define SET_LCD_PIXEL(depth, type) \
 470 static inline void glue(set_lcd_pixel, depth) \
 471         (musicpal_lcd_state *s, int x, int y, type col) \
 472 { \
 473     int dx, dy; \
 474     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 475 \
 476     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 477         for (dx = 0; dx < 3; dx++, pixel++) \
 478             *pixel = col; \
 479 }
 480 SET_LCD_PIXEL(8, uint8_t)
 481 SET_LCD_PIXEL(16, uint16_t)
 482 SET_LCD_PIXEL(32, uint32_t)
 483
 484 #include "pixel_ops.h"
 485
 486 static void lcd_refresh(void *opaque)
 487 {
 488     musicpal_lcd_state *s = opaque;
 489     int x, y, col;
 490
 491     switch (ds_get_bits_per_pixel(s->ds)) {
 492     case 0:
 493         return;
 494 #define LCD_REFRESH(depth, func) \
 495     case depth: \
 496         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 497                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 498                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 499         for (x = 0; x < 128; x++) { \
 500             for (y = 0; y < 64; y++) { \
 501                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 502                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 503                 } else { \
 504                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 505                 } \
 506             } \
 507         } \
 508         break;
 509     LCD_REFRESH(8, rgb_to_pixel8)
 510     LCD_REFRESH(16, rgb_to_pixel16)
 511     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 512                      rgb_to_pixel32bgr : rgb_to_pixel32))
 513     default:
 514         hw_error("unsupported colour depth %i\n",
 515                   ds_get_bits_per_pixel(s->ds));
 516     }
 517
 518     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 519 }
 520
 521 static void lcd_invalidate(void *opaque)
 522 {
 523 }
 524
 525 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 526 {
 527     musicpal_lcd_state *s = opaque;
 528     s->brightness &= ~(1 << irq);
 529     s->brightness |= level << irq;
 530 }
 531
 532 static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
 533                                   unsigned size)
 534 {
 535     musicpal_lcd_state *s = opaque;
 536
 537     switch (offset) {
 538     case MP_LCD_IRQCTRL:
 539         return s->irqctrl;
 540
 541     default:
 542         return 0;
 543     }
 544 }
 545
 546 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 547                                uint64_t value, unsigned size)
 548 {
 549     musicpal_lcd_state *s = opaque;
 550
 551     switch (offset) {
 552     case MP_LCD_IRQCTRL:
 553         s->irqctrl = value;
 554         break;
 555
 556     case MP_LCD_SPICTRL:
 557         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 558             s->mode = value;
 559         } else {
 560             s->mode = MP_LCD_SPI_INVALID;
 561         }
 562         break;
 563
 564     case MP_LCD_INST:
 565         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 566             s->page = value - MP_LCD_INST_SETPAGE0;
 567             s->page_off = 0;
 568         }
 569         break;
 570
 571     case MP_LCD_DATA:
 572         if (s->mode == MP_LCD_SPI_CMD) {
 573             if (value >= MP_LCD_INST_SETPAGE0 &&
 574                 value <= MP_LCD_INST_SETPAGE7) {
 575                 s->page = value - MP_LCD_INST_SETPAGE0;
 576                 s->page_off = 0;
 577             }
 578         } else if (s->mode == MP_LCD_SPI_DATA) {
 579             s->video_ram[s->page*128 + s->page_off] = value;
 580             s->page_off = (s->page_off + 1) & 127;
 581         }
 582         break;
 583     }
 584 }
 585
 586 static const MemoryRegionOps musicpal_lcd_ops = {
 587     .read = musicpal_lcd_read,
 588     .write = musicpal_lcd_write,
 589     .endianness = DEVICE_NATIVE_ENDIAN,
 590 };
 591
 592 static int musicpal_lcd_init(SysBusDevice *dev)
 593 {
 594     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 595
 596     s->brightness = 7;
 597
 598     memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
 599                           "musicpal-lcd", MP_LCD_SIZE);
 600     sysbus_init_mmio(dev, &s->iomem);
 601
 602     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 603                                  NULL, NULL, s);
 604     qemu_console_resize(s->ds, 128*3, 64*3);
 605
 606     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 607
 608     return 0;
 609 }
 610
 611 static const VMStateDescription musicpal_lcd_vmsd = {
 612     .name = "musicpal_lcd",
 613     .version_id = 1,
 614     .minimum_version_id = 1,
 615     .minimum_version_id_old = 1,
 616     .fields = (VMStateField[]) {
 617         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 618         VMSTATE_UINT32(mode, musicpal_lcd_state),
 619         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 620         VMSTATE_UINT32(page, musicpal_lcd_state),
 621         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 622         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 623         VMSTATE_END_OF_LIST()
 624     }
 625 };
 626
 627 static SysBusDeviceInfo musicpal_lcd_info = {
 628     .init = musicpal_lcd_init,
 629     .qdev.name = "musicpal_lcd",
 630     .qdev.size = sizeof(musicpal_lcd_state),
 631     .qdev.vmsd = &musicpal_lcd_vmsd,
 632 };
 633
 634 /* PIC register offsets */
 635 #define MP_PIC_STATUS           0x00
 636 #define MP_PIC_ENABLE_SET       0x08
 637 #define MP_PIC_ENABLE_CLR       0x0C
 638
 639 typedef struct mv88w8618_pic_state
 640 {
 641     SysBusDevice busdev;
 642     MemoryRegion iomem;
 643     uint32_t level;
 644     uint32_t enabled;
 645     qemu_irq parent_irq;
 646 } mv88w8618_pic_state;
 647
 648 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 649 {
 650     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 651 }
 652
 653 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 654 {
 655     mv88w8618_pic_state *s = opaque;
 656
 657     if (level) {
 658         s->level |= 1 << irq;
 659     } else {
 660         s->level &= ~(1 << irq);
 661     }
 662     mv88w8618_pic_update(s);
 663 }
 664
 665 static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
 666                                    unsigned size)
 667 {
 668     mv88w8618_pic_state *s = opaque;
 669
 670     switch (offset) {
 671     case MP_PIC_STATUS:
 672         return s->level & s->enabled;
 673
 674     default:
 675         return 0;
 676     }
 677 }
 678
 679 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 680                                 uint64_t value, unsigned size)
 681 {
 682     mv88w8618_pic_state *s = opaque;
 683
 684     switch (offset) {
 685     case MP_PIC_ENABLE_SET:
 686         s->enabled |= value;
 687         break;
 688
 689     case MP_PIC_ENABLE_CLR:
 690         s->enabled &= ~value;
 691         s->level &= ~value;
 692         break;
 693     }
 694     mv88w8618_pic_update(s);
 695 }
 696
 697 static void mv88w8618_pic_reset(DeviceState *d)
 698 {
 699     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
 700                                          sysbus_from_qdev(d));
 701
 702     s->level = 0;
 703     s->enabled = 0;
 704 }
 705
 706 static const MemoryRegionOps mv88w8618_pic_ops = {
 707     .read = mv88w8618_pic_read,
 708     .write = mv88w8618_pic_write,
 709     .endianness = DEVICE_NATIVE_ENDIAN,
 710 };
 711
 712 static int mv88w8618_pic_init(SysBusDevice *dev)
 713 {
 714     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 715
 716     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 717     sysbus_init_irq(dev, &s->parent_irq);
 718     memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
 719                           "musicpal-pic", MP_PIC_SIZE);
 720     sysbus_init_mmio(dev, &s->iomem);
 721     return 0;
 722 }
 723
 724 static const VMStateDescription mv88w8618_pic_vmsd = {
 725     .name = "mv88w8618_pic",
 726     .version_id = 1,
 727     .minimum_version_id = 1,
 728     .minimum_version_id_old = 1,
 729     .fields = (VMStateField[]) {
 730         VMSTATE_UINT32(level, mv88w8618_pic_state),
 731         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 732         VMSTATE_END_OF_LIST()
 733     }
 734 };
 735
 736 static SysBusDeviceInfo mv88w8618_pic_info = {
 737     .init = mv88w8618_pic_init,
 738     .qdev.name = "mv88w8618_pic",
 739     .qdev.size = sizeof(mv88w8618_pic_state),
 740     .qdev.reset = mv88w8618_pic_reset,
 741     .qdev.vmsd = &mv88w8618_pic_vmsd,
 742 };
 743
 744 /* PIT register offsets */
 745 #define MP_PIT_TIMER1_LENGTH    0x00
 746 /* ... */
 747 #define MP_PIT_TIMER4_LENGTH    0x0C
 748 #define MP_PIT_CONTROL          0x10
 749 #define MP_PIT_TIMER1_VALUE     0x14
 750 /* ... */
 751 #define MP_PIT_TIMER4_VALUE     0x20
 752 #define MP_BOARD_RESET          0x34
 753
 754 /* Magic board reset value (probably some watchdog behind it) */
 755 #define MP_BOARD_RESET_MAGIC    0x10000
 756
 757 typedef struct mv88w8618_timer_state {
 758     ptimer_state *ptimer;
 759     uint32_t limit;
 760     int freq;
 761     qemu_irq irq;
 762 } mv88w8618_timer_state;
 763
 764 typedef struct mv88w8618_pit_state {
 765     SysBusDevice busdev;
 766     MemoryRegion iomem;
 767     mv88w8618_timer_state timer[4];
 768 } mv88w8618_pit_state;
 769
 770 static void mv88w8618_timer_tick(void *opaque)
 771 {
 772     mv88w8618_timer_state *s = opaque;
 773
 774     qemu_irq_raise(s->irq);
 775 }
 776
 777 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 778                                  uint32_t freq)
 779 {
 780     QEMUBH *bh;
 781
 782     sysbus_init_irq(dev, &s->irq);
 783     s->freq = freq;
 784
 785     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 786     s->ptimer = ptimer_init(bh);
 787 }
 788
 789 static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
 790                                    unsigned size)
 791 {
 792     mv88w8618_pit_state *s = opaque;
 793     mv88w8618_timer_state *t;
 794
 795     switch (offset) {
 796     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 797         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 798         return ptimer_get_count(t->ptimer);
 799
 800     default:
 801         return 0;
 802     }
 803 }
 804
 805 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 806                                 uint64_t value, unsigned size)
 807 {
 808     mv88w8618_pit_state *s = opaque;
 809     mv88w8618_timer_state *t;
 810     int i;
 811
 812     switch (offset) {
 813     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 814         t = &s->timer[offset >> 2];
 815         t->limit = value;
 816         if (t->limit > 0) {
 817             ptimer_set_limit(t->ptimer, t->limit, 1);
 818         } else {
 819             ptimer_stop(t->ptimer);
 820         }
 821         break;
 822
 823     case MP_PIT_CONTROL:
 824         for (i = 0; i < 4; i++) {
 825             t = &s->timer[i];
 826             if (value & 0xf && t->limit > 0) {
 827                 ptimer_set_limit(t->ptimer, t->limit, 0);
 828                 ptimer_set_freq(t->ptimer, t->freq);
 829                 ptimer_run(t->ptimer, 0);
 830             } else {
 831                 ptimer_stop(t->ptimer);
 832             }
 833             value >>= 4;
 834         }
 835         break;
 836
 837     case MP_BOARD_RESET:
 838         if (value == MP_BOARD_RESET_MAGIC) {
 839             qemu_system_reset_request();
 840         }
 841         break;
 842     }
 843 }
 844
 845 static void mv88w8618_pit_reset(DeviceState *d)
 846 {
 847     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
 848                                          sysbus_from_qdev(d));
 849     int i;
 850
 851     for (i = 0; i < 4; i++) {
 852         ptimer_stop(s->timer[i].ptimer);
 853         s->timer[i].limit = 0;
 854     }
 855 }
 856
 857 static const MemoryRegionOps mv88w8618_pit_ops = {
 858     .read = mv88w8618_pit_read,
 859     .write = mv88w8618_pit_write,
 860     .endianness = DEVICE_NATIVE_ENDIAN,
 861 };
 862
 863 static int mv88w8618_pit_init(SysBusDevice *dev)
 864 {
 865     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 866     int i;
 867
 868     /* Letting them all run at 1 MHz is likely just a pragmatic
 869      * simplification. */
 870     for (i = 0; i < 4; i++) {
 871         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 872     }
 873
 874     memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
 875                           "musicpal-pit", MP_PIT_SIZE);
 876     sysbus_init_mmio(dev, &s->iomem);
 877     return 0;
 878 }
 879
 880 static const VMStateDescription mv88w8618_timer_vmsd = {
 881     .name = "timer",
 882     .version_id = 1,
 883     .minimum_version_id = 1,
 884     .minimum_version_id_old = 1,
 885     .fields = (VMStateField[]) {
 886         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 887         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 888         VMSTATE_END_OF_LIST()
 889     }
 890 };
 891
 892 static const VMStateDescription mv88w8618_pit_vmsd = {
 893     .name = "mv88w8618_pit",
 894     .version_id = 1,
 895     .minimum_version_id = 1,
 896     .minimum_version_id_old = 1,
 897     .fields = (VMStateField[]) {
 898         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 899                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 900         VMSTATE_END_OF_LIST()
 901     }
 902 };
 903
 904 static SysBusDeviceInfo mv88w8618_pit_info = {
 905     .init = mv88w8618_pit_init,
 906     .qdev.name  = "mv88w8618_pit",
 907     .qdev.size  = sizeof(mv88w8618_pit_state),
 908     .qdev.reset = mv88w8618_pit_reset,
 909     .qdev.vmsd  = &mv88w8618_pit_vmsd,
 910 };
 911
 912 /* Flash config register offsets */
 913 #define MP_FLASHCFG_CFGR0    0x04
 914
 915 typedef struct mv88w8618_flashcfg_state {
 916     SysBusDevice busdev;
 917     MemoryRegion iomem;
 918     uint32_t cfgr0;
 919 } mv88w8618_flashcfg_state;
 920
 921 static uint64_t mv88w8618_flashcfg_read(void *opaque,
 922                                         target_phys_addr_t offset,
 923                                         unsigned size)
 924 {
 925     mv88w8618_flashcfg_state *s = opaque;
 926
 927     switch (offset) {
 928     case MP_FLASHCFG_CFGR0:
 929         return s->cfgr0;
 930
 931     default:
 932         return 0;
 933     }
 934 }
 935
 936 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 937                                      uint64_t value, unsigned size)
 938 {
 939     mv88w8618_flashcfg_state *s = opaque;
 940
 941     switch (offset) {
 942     case MP_FLASHCFG_CFGR0:
 943         s->cfgr0 = value;
 944         break;
 945     }
 946 }
 947
 948 static const MemoryRegionOps mv88w8618_flashcfg_ops = {
 949     .read = mv88w8618_flashcfg_read,
 950     .write = mv88w8618_flashcfg_write,
 951     .endianness = DEVICE_NATIVE_ENDIAN,
 952 };
 953
 954 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 955 {
 956     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 957
 958     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 959     memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
 960                           "musicpal-flashcfg", MP_FLASHCFG_SIZE);
 961     sysbus_init_mmio(dev, &s->iomem);
 962     return 0;
 963 }
 964
 965 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
 966     .name = "mv88w8618_flashcfg",
 967     .version_id = 1,
 968     .minimum_version_id = 1,
 969     .minimum_version_id_old = 1,
 970     .fields = (VMStateField[]) {
 971         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
 972         VMSTATE_END_OF_LIST()
 973     }
 974 };
 975
 976 static SysBusDeviceInfo mv88w8618_flashcfg_info = {
 977     .init = mv88w8618_flashcfg_init,
 978     .qdev.name  = "mv88w8618_flashcfg",
 979     .qdev.size  = sizeof(mv88w8618_flashcfg_state),
 980     .qdev.vmsd  = &mv88w8618_flashcfg_vmsd,
 981 };
 982
 983 /* Misc register offsets */
 984 #define MP_MISC_BOARD_REVISION  0x18
 985
 986 #define MP_BOARD_REVISION       0x31
 987
 988 static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
 989                                    unsigned size)
 990 {
 991     switch (offset) {
 992     case MP_MISC_BOARD_REVISION:
 993         return MP_BOARD_REVISION;
 994
 995     default:
 996         return 0;
 997     }
 998 }
 999
1000 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1001                                 uint64_t value, unsigned size)
1002 {
1003 }
1004
1005 static const MemoryRegionOps musicpal_misc_ops = {
1006     .read = musicpal_misc_read,
1007     .write = musicpal_misc_write,
1008     .endianness = DEVICE_NATIVE_ENDIAN,
1009 };
1010
1011 static void musicpal_misc_init(SysBusDevice *dev)
1012 {
1013     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1014
1015     memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
1016                           "musicpal-misc", MP_MISC_SIZE);
1017     sysbus_add_memory(dev, MP_MISC_BASE, iomem);
1018 }
1019
1020 /* WLAN register offsets */
1021 #define MP_WLAN_MAGIC1          0x11c
1022 #define MP_WLAN_MAGIC2          0x124
1023
1024 static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
1025                                     unsigned size)
1026 {
1027     switch (offset) {
1028     /* Workaround to allow loading the binary-only wlandrv.ko crap
1029      * from the original Freecom firmware. */
1030     case MP_WLAN_MAGIC1:
1031         return ~3;
1032     case MP_WLAN_MAGIC2:
1033         return -1;
1034
1035     default:
1036         return 0;
1037     }
1038 }
1039
1040 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1041                                  uint64_t value, unsigned size)
1042 {
1043 }
1044
1045 static const MemoryRegionOps mv88w8618_wlan_ops = {
1046     .read = mv88w8618_wlan_read,
1047     .write =mv88w8618_wlan_write,
1048     .endianness = DEVICE_NATIVE_ENDIAN,
1049 };
1050
1051 static int mv88w8618_wlan_init(SysBusDevice *dev)
1052 {
1053     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1054
1055     memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
1056                           "musicpal-wlan", MP_WLAN_SIZE);
1057     sysbus_init_mmio(dev, iomem);
1058     return 0;
1059 }
1060
1061 /* GPIO register offsets */
1062 #define MP_GPIO_OE_LO           0x008
1063 #define MP_GPIO_OUT_LO          0x00c
1064 #define MP_GPIO_IN_LO           0x010
1065 #define MP_GPIO_IER_LO          0x014
1066 #define MP_GPIO_IMR_LO          0x018
1067 #define MP_GPIO_ISR_LO          0x020
1068 #define MP_GPIO_OE_HI           0x508
1069 #define MP_GPIO_OUT_HI          0x50c
1070 #define MP_GPIO_IN_HI           0x510
1071 #define MP_GPIO_IER_HI          0x514
1072 #define MP_GPIO_IMR_HI          0x518
1073 #define MP_GPIO_ISR_HI          0x520
1074
1075 /* GPIO bits & masks */
1076 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1077 #define MP_GPIO_I2C_DATA_BIT    29
1078 #define MP_GPIO_I2C_CLOCK_BIT   30
1079
1080 /* LCD brightness bits in GPIO_OE_HI */
1081 #define MP_OE_LCD_BRIGHTNESS    0x0007
1082
1083 typedef struct musicpal_gpio_state {
1084     SysBusDevice busdev;
1085     MemoryRegion iomem;
1086     uint32_t lcd_brightness;
1087     uint32_t out_state;
1088     uint32_t in_state;
1089     uint32_t ier;
1090     uint32_t imr;
1091     uint32_t isr;
1092     qemu_irq irq;
1093     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1094 } musicpal_gpio_state;
1095
1096 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1097     int i;
1098     uint32_t brightness;
1099
1100     /* compute brightness ratio */
1101     switch (s->lcd_brightness) {
1102     case 0x00000007:
1103         brightness = 0;
1104         break;
1105
1106     case 0x00020000:
1107         brightness = 1;
1108         break;
1109
1110     case 0x00020001:
1111         brightness = 2;
1112         break;
1113
1114     case 0x00040000:
1115         brightness = 3;
1116         break;
1117
1118     case 0x00010006:
1119         brightness = 4;
1120         break;
1121
1122     case 0x00020005:
1123         brightness = 5;
1124         break;
1125
1126     case 0x00040003:
1127         brightness = 6;
1128         break;
1129
1130     case 0x00030004:
1131     default:
1132         brightness = 7;
1133     }
1134
1135     /* set lcd brightness GPIOs  */
1136     for (i = 0; i <= 2; i++) {
1137         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1138     }
1139 }
1140
1141 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1142 {
1143     musicpal_gpio_state *s = opaque;
1144     uint32_t mask = 1 << pin;
1145     uint32_t delta = level << pin;
1146     uint32_t old = s->in_state & mask;
1147
1148     s->in_state &= ~mask;
1149     s->in_state |= delta;
1150
1151     if ((old ^ delta) &&
1152         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1153         s->isr = mask;
1154         qemu_irq_raise(s->irq);
1155     }
1156 }
1157
1158 static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
1159                                    unsigned size)
1160 {
1161     musicpal_gpio_state *s = opaque;
1162
1163     switch (offset) {
1164     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1165         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1166
1167     case MP_GPIO_OUT_LO:
1168         return s->out_state & 0xFFFF;
1169     case MP_GPIO_OUT_HI:
1170         return s->out_state >> 16;
1171
1172     case MP_GPIO_IN_LO:
1173         return s->in_state & 0xFFFF;
1174     case MP_GPIO_IN_HI:
1175         return s->in_state >> 16;
1176
1177     case MP_GPIO_IER_LO:
1178         return s->ier & 0xFFFF;
1179     case MP_GPIO_IER_HI:
1180         return s->ier >> 16;
1181
1182     case MP_GPIO_IMR_LO:
1183         return s->imr & 0xFFFF;
1184     case MP_GPIO_IMR_HI:
1185         return s->imr >> 16;
1186
1187     case MP_GPIO_ISR_LO:
1188         return s->isr & 0xFFFF;
1189     case MP_GPIO_ISR_HI:
1190         return s->isr >> 16;
1191
1192     default:
1193         return 0;
1194     }
1195 }
1196
1197 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1198                                 uint64_t value, unsigned size)
1199 {
1200     musicpal_gpio_state *s = opaque;
1201     switch (offset) {
1202     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1203         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1204                          (value & MP_OE_LCD_BRIGHTNESS);
1205         musicpal_gpio_brightness_update(s);
1206         break;
1207
1208     case MP_GPIO_OUT_LO:
1209         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1210         break;
1211     case MP_GPIO_OUT_HI:
1212         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1213         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1214                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1215         musicpal_gpio_brightness_update(s);
1216         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1217         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1218         break;
1219
1220     case MP_GPIO_IER_LO:
1221         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1222         break;
1223     case MP_GPIO_IER_HI:
1224         s->ier = (s->ier & 0xFFFF) | (value << 16);
1225         break;
1226
1227     case MP_GPIO_IMR_LO:
1228         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1229         break;
1230     case MP_GPIO_IMR_HI:
1231         s->imr = (s->imr & 0xFFFF) | (value << 16);
1232         break;
1233     }
1234 }
1235
1236 static const MemoryRegionOps musicpal_gpio_ops = {
1237     .read = musicpal_gpio_read,
1238     .write = musicpal_gpio_write,
1239     .endianness = DEVICE_NATIVE_ENDIAN,
1240 };
1241
1242 static void musicpal_gpio_reset(DeviceState *d)
1243 {
1244     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1245                                          sysbus_from_qdev(d));
1246
1247     s->lcd_brightness = 0;
1248     s->out_state = 0;
1249     s->in_state = 0xffffffff;
1250     s->ier = 0;
1251     s->imr = 0;
1252     s->isr = 0;
1253 }
1254
1255 static int musicpal_gpio_init(SysBusDevice *dev)
1256 {
1257     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1258
1259     sysbus_init_irq(dev, &s->irq);
1260
1261     memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
1262                           "musicpal-gpio", MP_GPIO_SIZE);
1263     sysbus_init_mmio(dev, &s->iomem);
1264
1265     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1266
1267     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1268
1269     return 0;
1270 }
1271
1272 static const VMStateDescription musicpal_gpio_vmsd = {
1273     .name = "musicpal_gpio",
1274     .version_id = 1,
1275     .minimum_version_id = 1,
1276     .minimum_version_id_old = 1,
1277     .fields = (VMStateField[]) {
1278         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1279         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1280         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1281         VMSTATE_UINT32(ier, musicpal_gpio_state),
1282         VMSTATE_UINT32(imr, musicpal_gpio_state),
1283         VMSTATE_UINT32(isr, musicpal_gpio_state),
1284         VMSTATE_END_OF_LIST()
1285     }
1286 };
1287
1288 static SysBusDeviceInfo musicpal_gpio_info = {
1289     .init = musicpal_gpio_init,
1290     .qdev.name  = "musicpal_gpio",
1291     .qdev.size  = sizeof(musicpal_gpio_state),
1292     .qdev.reset = musicpal_gpio_reset,
1293     .qdev.vmsd  = &musicpal_gpio_vmsd,
1294 };
1295
1296 /* Keyboard codes & masks */
1297 #define KEY_RELEASED            0x80
1298 #define KEY_CODE                0x7f
1299
1300 #define KEYCODE_TAB             0x0f
1301 #define KEYCODE_ENTER           0x1c
1302 #define KEYCODE_F               0x21
1303 #define KEYCODE_M               0x32
1304
1305 #define KEYCODE_EXTENDED        0xe0
1306 #define KEYCODE_UP              0x48
1307 #define KEYCODE_DOWN            0x50
1308 #define KEYCODE_LEFT            0x4b
1309 #define KEYCODE_RIGHT           0x4d
1310
1311 #define MP_KEY_WHEEL_VOL       (1 << 0)
1312 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1313 #define MP_KEY_WHEEL_NAV       (1 << 2)
1314 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1315 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1316 #define MP_KEY_BTN_MENU        (1 << 5)
1317 #define MP_KEY_BTN_VOLUME      (1 << 6)
1318 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1319
1320 typedef struct musicpal_key_state {
1321     SysBusDevice busdev;
1322     MemoryRegion iomem;
1323     uint32_t kbd_extended;
1324     uint32_t pressed_keys;
1325     qemu_irq out[8];
1326 } musicpal_key_state;
1327
1328 static void musicpal_key_event(void *opaque, int keycode)
1329 {
1330     musicpal_key_state *s = opaque;
1331     uint32_t event = 0;
1332     int i;
1333
1334     if (keycode == KEYCODE_EXTENDED) {
1335         s->kbd_extended = 1;
1336         return;
1337     }
1338
1339     if (s->kbd_extended) {
1340         switch (keycode & KEY_CODE) {
1341         case KEYCODE_UP:
1342             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1343             break;
1344
1345         case KEYCODE_DOWN:
1346             event = MP_KEY_WHEEL_NAV;
1347             break;
1348
1349         case KEYCODE_LEFT:
1350             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1351             break;
1352
1353         case KEYCODE_RIGHT:
1354             event = MP_KEY_WHEEL_VOL;
1355             break;
1356         }
1357     } else {
1358         switch (keycode & KEY_CODE) {
1359         case KEYCODE_F:
1360             event = MP_KEY_BTN_FAVORITS;
1361             break;
1362
1363         case KEYCODE_TAB:
1364             event = MP_KEY_BTN_VOLUME;
1365             break;
1366
1367         case KEYCODE_ENTER:
1368             event = MP_KEY_BTN_NAVIGATION;
1369             break;
1370
1371         case KEYCODE_M:
1372             event = MP_KEY_BTN_MENU;
1373             break;
1374         }
1375         /* Do not repeat already pressed buttons */
1376         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1377             event = 0;
1378         }
1379     }
1380
1381     if (event) {
1382         /* Raise GPIO pin first if repeating a key */
1383         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1384             for (i = 0; i <= 7; i++) {
1385                 if (event & (1 << i)) {
1386                     qemu_set_irq(s->out[i], 1);
1387                 }
1388             }
1389         }
1390         for (i = 0; i <= 7; i++) {
1391             if (event & (1 << i)) {
1392                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1393             }
1394         }
1395         if (keycode & KEY_RELEASED) {
1396             s->pressed_keys &= ~event;
1397         } else {
1398             s->pressed_keys |= event;
1399         }
1400     }
1401
1402     s->kbd_extended = 0;
1403 }
1404
1405 static int musicpal_key_init(SysBusDevice *dev)
1406 {
1407     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1408
1409     memory_region_init(&s->iomem, "dummy", 0);
1410     sysbus_init_mmio(dev, &s->iomem);
1411
1412     s->kbd_extended = 0;
1413     s->pressed_keys = 0;
1414
1415     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1416
1417     qemu_add_kbd_event_handler(musicpal_key_event, s);
1418
1419     return 0;
1420 }
1421
1422 static const VMStateDescription musicpal_key_vmsd = {
1423     .name = "musicpal_key",
1424     .version_id = 1,
1425     .minimum_version_id = 1,
1426     .minimum_version_id_old = 1,
1427     .fields = (VMStateField[]) {
1428         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1429         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1430         VMSTATE_END_OF_LIST()
1431     }
1432 };
1433
1434 static SysBusDeviceInfo musicpal_key_info = {
1435     .init = musicpal_key_init,
1436     .qdev.name  = "musicpal_key",
1437     .qdev.size  = sizeof(musicpal_key_state),
1438     .qdev.vmsd  = &musicpal_key_vmsd,
1439 };
1440
1441 static struct arm_boot_info musicpal_binfo = {
1442     .loader_start = 0x0,
1443     .board_id = 0x20e,
1444 };
1445
1446 static void musicpal_init(ram_addr_t ram_size,
1447                const char *boot_device,
1448                const char *kernel_filename, const char *kernel_cmdline,
1449                const char *initrd_filename, const char *cpu_model)
1450 {
1451     CPUState *env;
1452     qemu_irq *cpu_pic;
1453     qemu_irq pic[32];
1454     DeviceState *dev;
1455     DeviceState *i2c_dev;
1456     DeviceState *lcd_dev;
1457     DeviceState *key_dev;
1458     DeviceState *wm8750_dev;
1459     SysBusDevice *s;
1460     i2c_bus *i2c;
1461     int i;
1462     unsigned long flash_size;
1463     DriveInfo *dinfo;
1464     MemoryRegion *address_space_mem = get_system_memory();
1465     MemoryRegion *ram = g_new(MemoryRegion, 1);
1466     MemoryRegion *sram = g_new(MemoryRegion, 1);
1467
1468     if (!cpu_model) {
1469         cpu_model = "arm926";
1470     }
1471     env = cpu_init(cpu_model);
1472     if (!env) {
1473         fprintf(stderr, "Unable to find CPU definition\n");
1474         exit(1);
1475     }
1476     cpu_pic = arm_pic_init_cpu(env);
1477
1478     /* For now we use a fixed - the original - RAM size */
1479     memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
1480     vmstate_register_ram_global(ram);
1481     memory_region_add_subregion(address_space_mem, 0, ram);
1482
1483     memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
1484     vmstate_register_ram_global(sram);
1485     memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
1486
1487     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1488                                cpu_pic[ARM_PIC_CPU_IRQ]);
1489     for (i = 0; i < 32; i++) {
1490         pic[i] = qdev_get_gpio_in(dev, i);
1491     }
1492     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1493                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1494                           pic[MP_TIMER4_IRQ], NULL);
1495
1496     if (serial_hds[0]) {
1497         serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1498                        1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
1499     }
1500     if (serial_hds[1]) {
1501         serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1502                        1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
1503     }
1504
1505     /* Register flash */
1506     dinfo = drive_get(IF_PFLASH, 0, 0);
1507     if (dinfo) {
1508         flash_size = bdrv_getlength(dinfo->bdrv);
1509         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1510             flash_size != 32*1024*1024) {
1511             fprintf(stderr, "Invalid flash image size\n");
1512             exit(1);
1513         }
1514
1515         /*
1516          * The original U-Boot accesses the flash at 0xFE000000 instead of
1517          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1518          * image is smaller than 32 MB.
1519          */
1520 #ifdef TARGET_WORDS_BIGENDIAN
1521         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1522                               "musicpal.flash", flash_size,
1523                               dinfo->bdrv, 0x10000,
1524                               (flash_size + 0xffff) >> 16,
1525                               MP_FLASH_SIZE_MAX / flash_size,
1526                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1527                               0x5555, 0x2AAA, 1);
1528 #else
1529         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1530                               "musicpal.flash", flash_size,
1531                               dinfo->bdrv, 0x10000,
1532                               (flash_size + 0xffff) >> 16,
1533                               MP_FLASH_SIZE_MAX / flash_size,
1534                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1535                               0x5555, 0x2AAA, 0);
1536 #endif
1537
1538     }
1539     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1540
1541     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1542     dev = qdev_create(NULL, "mv88w8618_eth");
1543     qdev_set_nic_properties(dev, &nd_table[0]);
1544     qdev_init_nofail(dev);
1545     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1546     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1547
1548     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1549
1550     musicpal_misc_init(sysbus_from_qdev(dev));
1551
1552     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1553     i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1554     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1555
1556     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1557     key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
1558
1559     /* I2C read data */
1560     qdev_connect_gpio_out(i2c_dev, 0,
1561                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1562     /* I2C data */
1563     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1564     /* I2C clock */
1565     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1566
1567     for (i = 0; i < 3; i++) {
1568         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1569     }
1570     for (i = 0; i < 4; i++) {
1571         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1572     }
1573     for (i = 4; i < 8; i++) {
1574         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1575     }
1576
1577     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1578     dev = qdev_create(NULL, "mv88w8618_audio");
1579     s = sysbus_from_qdev(dev);
1580     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1581     qdev_init_nofail(dev);
1582     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1583     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1584
1585     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1586     musicpal_binfo.kernel_filename = kernel_filename;
1587     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1588     musicpal_binfo.initrd_filename = initrd_filename;
1589     arm_load_kernel(env, &musicpal_binfo);
1590 }
1591
1592 static QEMUMachine musicpal_machine = {
1593     .name = "musicpal",
1594     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1595     .init = musicpal_init,
1596 };
1597
1598 static void musicpal_machine_init(void)
1599 {
1600     qemu_register_machine(&musicpal_machine);
1601 }
1602
1603 machine_init(musicpal_machine_init);
1604
1605 static void musicpal_register_devices(void)
1606 {
1607     sysbus_register_withprop(&mv88w8618_pic_info);
1608     sysbus_register_withprop(&mv88w8618_pit_info);
1609     sysbus_register_withprop(&mv88w8618_flashcfg_info);
1610     sysbus_register_withprop(&mv88w8618_eth_info);
1611     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1612                         mv88w8618_wlan_init);
1613     sysbus_register_withprop(&musicpal_lcd_info);
1614     sysbus_register_withprop(&musicpal_gpio_info);
1615     sysbus_register_withprop(&musicpal_key_info);
1616 }
1617
1618 device_init(musicpal_register_devices)