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Introduce qemu_madvise()
[qemu/opensuse.git] / hw / vmware_vga.c
blob3d25c14da9d305605f45eca66b879a3225271ae8
1 /*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "loader.h"
26 #include "console.h"
27 #include "pci.h"
28 #include "vmware_vga.h"
29
30 #define VERBOSE
31 #undef DIRECT_VRAM
32 #define HW_RECT_ACCEL
33 #define HW_FILL_ACCEL
34 #define HW_MOUSE_ACCEL
35
36 # include "vga_int.h"
37
38 struct vmsvga_state_s {
39 VGACommonState vga;
40
41 int width;
42 int height;
43 int invalidated;
44 int depth;
45 int bypp;
46 int enable;
47 int config;
48 struct {
49 int id;
50 int x;
51 int y;
52 int on;
53 } cursor;
54
55 target_phys_addr_t vram_base;
56
57 int index;
58 int scratch_size;
59 uint32_t *scratch;
60 int new_width;
61 int new_height;
62 uint32_t guest;
63 uint32_t svgaid;
64 uint32_t wred;
65 uint32_t wgreen;
66 uint32_t wblue;
67 int syncing;
68 int fb_size;
69
70 ram_addr_t fifo_offset;
71 uint8_t *fifo_ptr;
72 unsigned int fifo_size;
73 target_phys_addr_t fifo_base;
74
75 union {
76 uint32_t *fifo;
77 struct __attribute__((__packed__)) {
78 uint32_t min;
79 uint32_t max;
80 uint32_t next_cmd;
81 uint32_t stop;
82 /* Add registers here when adding capabilities. */
83 uint32_t fifo[0];
84 } *cmd;
85 };
86
87 #define REDRAW_FIFO_LEN 512
88 struct vmsvga_rect_s {
89 int x, y, w, h;
90 } redraw_fifo[REDRAW_FIFO_LEN];
91 int redraw_fifo_first, redraw_fifo_last;
92 };
93
94 struct pci_vmsvga_state_s {
95 PCIDevice card;
96 struct vmsvga_state_s chip;
97 };
98
99 #define SVGA_MAGIC 0x900000UL
100 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
101 #define SVGA_ID_0 SVGA_MAKE_ID(0)
102 #define SVGA_ID_1 SVGA_MAKE_ID(1)
103 #define SVGA_ID_2 SVGA_MAKE_ID(2)
104
105 #define SVGA_LEGACY_BASE_PORT 0x4560
106 #define SVGA_INDEX_PORT 0x0
107 #define SVGA_VALUE_PORT 0x1
108 #define SVGA_BIOS_PORT 0x2
109
110 #define SVGA_VERSION_2
111
112 #ifdef SVGA_VERSION_2
113 # define SVGA_ID SVGA_ID_2
114 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
115 # define SVGA_IO_MUL 1
116 # define SVGA_FIFO_SIZE 0x10000
117 # define SVGA_MEM_BASE 0xe0000000
118 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
119 #else
120 # define SVGA_ID SVGA_ID_1
121 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
122 # define SVGA_IO_MUL 4
123 # define SVGA_FIFO_SIZE 0x10000
124 # define SVGA_MEM_BASE 0xe0000000
125 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
126 #endif
127
128 enum {
129 /* ID 0, 1 and 2 registers */
130 SVGA_REG_ID = 0,
131 SVGA_REG_ENABLE = 1,
132 SVGA_REG_WIDTH = 2,
133 SVGA_REG_HEIGHT = 3,
134 SVGA_REG_MAX_WIDTH = 4,
135 SVGA_REG_MAX_HEIGHT = 5,
136 SVGA_REG_DEPTH = 6,
137 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
138 SVGA_REG_PSEUDOCOLOR = 8,
139 SVGA_REG_RED_MASK = 9,
140 SVGA_REG_GREEN_MASK = 10,
141 SVGA_REG_BLUE_MASK = 11,
142 SVGA_REG_BYTES_PER_LINE = 12,
143 SVGA_REG_FB_START = 13,
144 SVGA_REG_FB_OFFSET = 14,
145 SVGA_REG_VRAM_SIZE = 15,
146 SVGA_REG_FB_SIZE = 16,
147
148 /* ID 1 and 2 registers */
149 SVGA_REG_CAPABILITIES = 17,
150 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
151 SVGA_REG_MEM_SIZE = 19,
152 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
153 SVGA_REG_SYNC = 21, /* Write to force synchronization */
154 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
155 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
156 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
157 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
158 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
159 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
160 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
161 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
162 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
163 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
164 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
165
166 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
167 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
168 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
169 };
170
171 #define SVGA_CAP_NONE 0
172 #define SVGA_CAP_RECT_FILL (1 << 0)
173 #define SVGA_CAP_RECT_COPY (1 << 1)
174 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
175 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
176 #define SVGA_CAP_RASTER_OP (1 << 4)
177 #define SVGA_CAP_CURSOR (1 << 5)
178 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
179 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
180 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
181 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
182 #define SVGA_CAP_GLYPH (1 << 10)
183 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
184 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
185 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
186 #define SVGA_CAP_3D (1 << 14)
187 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
188 #define SVGA_CAP_MULTIMON (1 << 16)
189 #define SVGA_CAP_PITCHLOCK (1 << 17)
190
191 /*
192 * FIFO offsets (seen as an array of 32-bit words)
193 */
194 enum {
195 /*
196 * The original defined FIFO offsets
197 */
198 SVGA_FIFO_MIN = 0,
199 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
200 SVGA_FIFO_NEXT_CMD,
201 SVGA_FIFO_STOP,
202
203 /*
204 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
205 */
206 SVGA_FIFO_CAPABILITIES = 4,
207 SVGA_FIFO_FLAGS,
208 SVGA_FIFO_FENCE,
209 SVGA_FIFO_3D_HWVERSION,
210 SVGA_FIFO_PITCHLOCK,
211 };
212
213 #define SVGA_FIFO_CAP_NONE 0
214 #define SVGA_FIFO_CAP_FENCE (1 << 0)
215 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
216 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
217
218 #define SVGA_FIFO_FLAG_NONE 0
219 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
220
221 /* These values can probably be changed arbitrarily. */
222 #define SVGA_SCRATCH_SIZE 0x8000
223 #define SVGA_MAX_WIDTH 2360
224 #define SVGA_MAX_HEIGHT 1770
225
226 #ifdef VERBOSE
227 # define GUEST_OS_BASE 0x5001
228 static const char *vmsvga_guest_id[] = {
229 [0x00] = "Dos",
230 [0x01] = "Windows 3.1",
231 [0x02] = "Windows 95",
232 [0x03] = "Windows 98",
233 [0x04] = "Windows ME",
234 [0x05] = "Windows NT",
235 [0x06] = "Windows 2000",
236 [0x07] = "Linux",
237 [0x08] = "OS/2",
238 [0x09] = "an unknown OS",
239 [0x0a] = "BSD",
240 [0x0b] = "Whistler",
241 [0x0c] = "an unknown OS",
242 [0x0d] = "an unknown OS",
243 [0x0e] = "an unknown OS",
244 [0x0f] = "an unknown OS",
245 [0x10] = "an unknown OS",
246 [0x11] = "an unknown OS",
247 [0x12] = "an unknown OS",
248 [0x13] = "an unknown OS",
249 [0x14] = "an unknown OS",
250 [0x15] = "Windows 2003",
251 };
252 #endif
253
254 enum {
255 SVGA_CMD_INVALID_CMD = 0,
256 SVGA_CMD_UPDATE = 1,
257 SVGA_CMD_RECT_FILL = 2,
258 SVGA_CMD_RECT_COPY = 3,
259 SVGA_CMD_DEFINE_BITMAP = 4,
260 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
261 SVGA_CMD_DEFINE_PIXMAP = 6,
262 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
263 SVGA_CMD_RECT_BITMAP_FILL = 8,
264 SVGA_CMD_RECT_PIXMAP_FILL = 9,
265 SVGA_CMD_RECT_BITMAP_COPY = 10,
266 SVGA_CMD_RECT_PIXMAP_COPY = 11,
267 SVGA_CMD_FREE_OBJECT = 12,
268 SVGA_CMD_RECT_ROP_FILL = 13,
269 SVGA_CMD_RECT_ROP_COPY = 14,
270 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
271 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
272 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
273 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
274 SVGA_CMD_DEFINE_CURSOR = 19,
275 SVGA_CMD_DISPLAY_CURSOR = 20,
276 SVGA_CMD_MOVE_CURSOR = 21,
277 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
278 SVGA_CMD_DRAW_GLYPH = 23,
279 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
280 SVGA_CMD_UPDATE_VERBOSE = 25,
281 SVGA_CMD_SURFACE_FILL = 26,
282 SVGA_CMD_SURFACE_COPY = 27,
283 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
284 SVGA_CMD_FRONT_ROP_FILL = 29,
285 SVGA_CMD_FENCE = 30,
286 };
287
288 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
289 enum {
290 SVGA_CURSOR_ON_HIDE = 0,
291 SVGA_CURSOR_ON_SHOW = 1,
292 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
293 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
294 };
295
296 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
297 int x, int y, int w, int h)
298 {
299 #ifndef DIRECT_VRAM
300 int line;
301 int bypl;
302 int width;
303 int start;
304 uint8_t *src;
305 uint8_t *dst;
306
307 if (x + w > s->width) {
308 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
309 __FUNCTION__, x, w);
310 x = MIN(x, s->width);
311 w = s->width - x;
312 }
313
314 if (y + h > s->height) {
315 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
316 __FUNCTION__, y, h);
317 y = MIN(y, s->height);
318 h = s->height - y;
319 }
320
321 line = h;
322 bypl = s->bypp * s->width;
323 width = s->bypp * w;
324 start = s->bypp * x + bypl * y;
325 src = s->vga.vram_ptr + start;
326 dst = ds_get_data(s->vga.ds) + start;
327
328 for (; line > 0; line --, src += bypl, dst += bypl)
329 memcpy(dst, src, width);
330 #endif
331
332 dpy_update(s->vga.ds, x, y, w, h);
333 }
334
335 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
336 {
337 #ifndef DIRECT_VRAM
338 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
339 #endif
340
341 dpy_update(s->vga.ds, 0, 0, s->width, s->height);
342 }
343
344 #ifdef DIRECT_VRAM
345 # define vmsvga_update_rect_delayed vmsvga_update_rect
346 #else
347 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
348 int x, int y, int w, int h)
349 {
350 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
351 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
352 rect->x = x;
353 rect->y = y;
354 rect->w = w;
355 rect->h = h;
356 }
357 #endif
358
359 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
360 {
361 struct vmsvga_rect_s *rect;
362 if (s->invalidated) {
363 s->redraw_fifo_first = s->redraw_fifo_last;
364 return;
365 }
366 /* Overlapping region updates can be optimised out here - if someone
367 * knows a smart algorithm to do that, please share. */
368 while (s->redraw_fifo_first != s->redraw_fifo_last) {
369 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
370 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
371 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
372 }
373 }
374
375 #ifdef HW_RECT_ACCEL
376 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
377 int x0, int y0, int x1, int y1, int w, int h)
378 {
379 # ifdef DIRECT_VRAM
380 uint8_t *vram = ds_get_data(s->ds);
381 # else
382 uint8_t *vram = s->vga.vram_ptr;
383 # endif
384 int bypl = s->bypp * s->width;
385 int width = s->bypp * w;
386 int line = h;
387 uint8_t *ptr[2];
388
389 # ifdef DIRECT_VRAM
390 if (s->ds->dpy_copy)
391 qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
392 else
393 # endif
394 {
395 if (y1 > y0) {
396 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
397 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
398 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
399 memmove(ptr[1], ptr[0], width);
400 } else {
401 ptr[0] = vram + s->bypp * x0 + bypl * y0;
402 ptr[1] = vram + s->bypp * x1 + bypl * y1;
403 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
404 memmove(ptr[1], ptr[0], width);
405 }
406 }
407
408 vmsvga_update_rect_delayed(s, x1, y1, w, h);
409 }
410 #endif
411
412 #ifdef HW_FILL_ACCEL
413 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
414 uint32_t c, int x, int y, int w, int h)
415 {
416 # ifdef DIRECT_VRAM
417 uint8_t *vram = ds_get_data(s->ds);
418 # else
419 uint8_t *vram = s->vga.vram_ptr;
420 # endif
421 int bypp = s->bypp;
422 int bypl = bypp * s->width;
423 int width = bypp * w;
424 int line = h;
425 int column;
426 uint8_t *fst = vram + bypp * x + bypl * y;
427 uint8_t *dst;
428 uint8_t *src;
429 uint8_t col[4];
430
431 # ifdef DIRECT_VRAM
432 if (s->ds->dpy_fill)
433 s->ds->dpy_fill(s->ds, x, y, w, h, c);
434 else
435 # endif
436 {
437 col[0] = c;
438 col[1] = c >> 8;
439 col[2] = c >> 16;
440 col[3] = c >> 24;
441
442 if (line --) {
443 dst = fst;
444 src = col;
445 for (column = width; column > 0; column --) {
446 *(dst ++) = *(src ++);
447 if (src - col == bypp)
448 src = col;
449 }
450 dst = fst;
451 for (; line > 0; line --) {
452 dst += bypl;
453 memcpy(dst, fst, width);
454 }
455 }
456 }
457
458 vmsvga_update_rect_delayed(s, x, y, w, h);
459 }
460 #endif
461
462 struct vmsvga_cursor_definition_s {
463 int width;
464 int height;
465 int id;
466 int bpp;
467 int hot_x;
468 int hot_y;
469 uint32_t mask[1024];
470 uint32_t image[4096];
471 };
472
473 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
474 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
475
476 #ifdef HW_MOUSE_ACCEL
477 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
478 struct vmsvga_cursor_definition_s *c)
479 {
480 QEMUCursor *qc;
481 int i, pixels;
482
483 qc = cursor_alloc(c->width, c->height);
484 qc->hot_x = c->hot_x;
485 qc->hot_y = c->hot_y;
486 switch (c->bpp) {
487 case 1:
488 cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image,
489 1, (void*)c->mask);
490 #ifdef DEBUG
491 cursor_print_ascii_art(qc, "vmware/mono");
492 #endif
493 break;
494 case 32:
495 /* fill alpha channel from mask, set color to zero */
496 cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask,
497 1, (void*)c->mask);
498 /* add in rgb values */
499 pixels = c->width * c->height;
500 for (i = 0; i < pixels; i++) {
501 qc->data[i] |= c->image[i] & 0xffffff;
502 }
503 #ifdef DEBUG
504 cursor_print_ascii_art(qc, "vmware/32bit");
505 #endif
506 break;
507 default:
508 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
509 __FUNCTION__, c->bpp);
510 cursor_put(qc);
511 qc = cursor_builtin_left_ptr();
512 }
513
514 if (s->vga.ds->cursor_define)
515 s->vga.ds->cursor_define(qc);
516 cursor_put(qc);
517 }
518 #endif
519
520 #define CMD(f) le32_to_cpu(s->cmd->f)
521
522 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
523 {
524 int num;
525 if (!s->config || !s->enable)
526 return 0;
527 num = CMD(next_cmd) - CMD(stop);
528 if (num < 0)
529 num += CMD(max) - CMD(min);
530 return num >> 2;
531 }
532
533 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
534 {
535 uint32_t cmd = s->fifo[CMD(stop) >> 2];
536 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
537 if (CMD(stop) >= CMD(max))
538 s->cmd->stop = s->cmd->min;
539 return cmd;
540 }
541
542 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
543 {
544 return le32_to_cpu(vmsvga_fifo_read_raw(s));
545 }
546
547 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
548 {
549 uint32_t cmd, colour;
550 int args, len;
551 int x, y, dx, dy, width, height;
552 struct vmsvga_cursor_definition_s cursor;
553 uint32_t cmd_start;
554
555 len = vmsvga_fifo_length(s);
556 while (len > 0) {
557 /* May need to go back to the start of the command if incomplete */
558 cmd_start = s->cmd->stop;
559
560 switch (cmd = vmsvga_fifo_read(s)) {
561 case SVGA_CMD_UPDATE:
562 case SVGA_CMD_UPDATE_VERBOSE:
563 len -= 5;
564 if (len < 0)
565 goto rewind;
566
567 x = vmsvga_fifo_read(s);
568 y = vmsvga_fifo_read(s);
569 width = vmsvga_fifo_read(s);
570 height = vmsvga_fifo_read(s);
571 vmsvga_update_rect_delayed(s, x, y, width, height);
572 break;
573
574 case SVGA_CMD_RECT_FILL:
575 len -= 6;
576 if (len < 0)
577 goto rewind;
578
579 colour = vmsvga_fifo_read(s);
580 x = vmsvga_fifo_read(s);
581 y = vmsvga_fifo_read(s);
582 width = vmsvga_fifo_read(s);
583 height = vmsvga_fifo_read(s);
584 #ifdef HW_FILL_ACCEL
585 vmsvga_fill_rect(s, colour, x, y, width, height);
586 break;
587 #else
588 args = 0;
589 goto badcmd;
590 #endif
591
592 case SVGA_CMD_RECT_COPY:
593 len -= 7;
594 if (len < 0)
595 goto rewind;
596
597 x = vmsvga_fifo_read(s);
598 y = vmsvga_fifo_read(s);
599 dx = vmsvga_fifo_read(s);
600 dy = vmsvga_fifo_read(s);
601 width = vmsvga_fifo_read(s);
602 height = vmsvga_fifo_read(s);
603 #ifdef HW_RECT_ACCEL
604 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
605 break;
606 #else
607 args = 0;
608 goto badcmd;
609 #endif
610
611 case SVGA_CMD_DEFINE_CURSOR:
612 len -= 8;
613 if (len < 0)
614 goto rewind;
615
616 cursor.id = vmsvga_fifo_read(s);
617 cursor.hot_x = vmsvga_fifo_read(s);
618 cursor.hot_y = vmsvga_fifo_read(s);
619 cursor.width = x = vmsvga_fifo_read(s);
620 cursor.height = y = vmsvga_fifo_read(s);
621 vmsvga_fifo_read(s);
622 cursor.bpp = vmsvga_fifo_read(s);
623
624 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
625 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
626 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image)
627 goto badcmd;
628
629 len -= args;
630 if (len < 0)
631 goto rewind;
632
633 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
634 cursor.mask[args] = vmsvga_fifo_read_raw(s);
635 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
636 cursor.image[args] = vmsvga_fifo_read_raw(s);
637 #ifdef HW_MOUSE_ACCEL
638 vmsvga_cursor_define(s, &cursor);
639 break;
640 #else
641 args = 0;
642 goto badcmd;
643 #endif
644
645 /*
646 * Other commands that we at least know the number of arguments
647 * for so we can avoid FIFO desync if driver uses them illegally.
648 */
649 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
650 len -= 6;
651 if (len < 0)
652 goto rewind;
653
654 vmsvga_fifo_read(s);
655 vmsvga_fifo_read(s);
656 vmsvga_fifo_read(s);
657 x = vmsvga_fifo_read(s);
658 y = vmsvga_fifo_read(s);
659 args = x * y;
660 goto badcmd;
661 case SVGA_CMD_RECT_ROP_FILL:
662 args = 6;
663 goto badcmd;
664 case SVGA_CMD_RECT_ROP_COPY:
665 args = 7;
666 goto badcmd;
667 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
668 len -= 4;
669 if (len < 0)
670 goto rewind;
671
672 vmsvga_fifo_read(s);
673 vmsvga_fifo_read(s);
674 args = 7 + (vmsvga_fifo_read(s) >> 2);
675 goto badcmd;
676 case SVGA_CMD_SURFACE_ALPHA_BLEND:
677 args = 12;
678 goto badcmd;
679
680 /*
681 * Other commands that are not listed as depending on any
682 * CAPABILITIES bits, but are not described in the README either.
683 */
684 case SVGA_CMD_SURFACE_FILL:
685 case SVGA_CMD_SURFACE_COPY:
686 case SVGA_CMD_FRONT_ROP_FILL:
687 case SVGA_CMD_FENCE:
688 case SVGA_CMD_INVALID_CMD:
689 break; /* Nop */
690
691 default:
692 args = 0;
693 badcmd:
694 len -= args;
695 if (len < 0)
696 goto rewind;
697 while (args --)
698 vmsvga_fifo_read(s);
699 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
700 __FUNCTION__, cmd);
701 break;
702
703 rewind:
704 s->cmd->stop = cmd_start;
705 break;
706 }
707 }
708
709 s->syncing = 0;
710 }
711
712 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
713 {
714 struct vmsvga_state_s *s = opaque;
715 return s->index;
716 }
717
718 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
719 {
720 struct vmsvga_state_s *s = opaque;
721 s->index = index;
722 }
723
724 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
725 {
726 uint32_t caps;
727 struct vmsvga_state_s *s = opaque;
728 switch (s->index) {
729 case SVGA_REG_ID:
730 return s->svgaid;
731
732 case SVGA_REG_ENABLE:
733 return s->enable;
734
735 case SVGA_REG_WIDTH:
736 return s->width;
737
738 case SVGA_REG_HEIGHT:
739 return s->height;
740
741 case SVGA_REG_MAX_WIDTH:
742 return SVGA_MAX_WIDTH;
743
744 case SVGA_REG_MAX_HEIGHT:
745 return SVGA_MAX_HEIGHT;
746
747 case SVGA_REG_DEPTH:
748 return s->depth;
749
750 case SVGA_REG_BITS_PER_PIXEL:
751 return (s->depth + 7) & ~7;
752
753 case SVGA_REG_PSEUDOCOLOR:
754 return 0x0;
755
756 case SVGA_REG_RED_MASK:
757 return s->wred;
758 case SVGA_REG_GREEN_MASK:
759 return s->wgreen;
760 case SVGA_REG_BLUE_MASK:
761 return s->wblue;
762
763 case SVGA_REG_BYTES_PER_LINE:
764 return ((s->depth + 7) >> 3) * s->new_width;
765
766 case SVGA_REG_FB_START:
767 return s->vram_base;
768
769 case SVGA_REG_FB_OFFSET:
770 return 0x0;
771
772 case SVGA_REG_VRAM_SIZE:
773 return s->vga.vram_size;
774
775 case SVGA_REG_FB_SIZE:
776 return s->fb_size;
777
778 case SVGA_REG_CAPABILITIES:
779 caps = SVGA_CAP_NONE;
780 #ifdef HW_RECT_ACCEL
781 caps |= SVGA_CAP_RECT_COPY;
782 #endif
783 #ifdef HW_FILL_ACCEL
784 caps |= SVGA_CAP_RECT_FILL;
785 #endif
786 #ifdef HW_MOUSE_ACCEL
787 if (s->vga.ds->mouse_set)
788 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
789 SVGA_CAP_CURSOR_BYPASS;
790 #endif
791 return caps;
792
793 case SVGA_REG_MEM_START:
794 return s->fifo_base;
795
796 case SVGA_REG_MEM_SIZE:
797 return s->fifo_size;
798
799 case SVGA_REG_CONFIG_DONE:
800 return s->config;
801
802 case SVGA_REG_SYNC:
803 case SVGA_REG_BUSY:
804 return s->syncing;
805
806 case SVGA_REG_GUEST_ID:
807 return s->guest;
808
809 case SVGA_REG_CURSOR_ID:
810 return s->cursor.id;
811
812 case SVGA_REG_CURSOR_X:
813 return s->cursor.x;
814
815 case SVGA_REG_CURSOR_Y:
816 return s->cursor.x;
817
818 case SVGA_REG_CURSOR_ON:
819 return s->cursor.on;
820
821 case SVGA_REG_HOST_BITS_PER_PIXEL:
822 return (s->depth + 7) & ~7;
823
824 case SVGA_REG_SCRATCH_SIZE:
825 return s->scratch_size;
826
827 case SVGA_REG_MEM_REGS:
828 case SVGA_REG_NUM_DISPLAYS:
829 case SVGA_REG_PITCHLOCK:
830 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
831 return 0;
832
833 default:
834 if (s->index >= SVGA_SCRATCH_BASE &&
835 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
836 return s->scratch[s->index - SVGA_SCRATCH_BASE];
837 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
838 }
839
840 return 0;
841 }
842
843 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
844 {
845 struct vmsvga_state_s *s = opaque;
846 switch (s->index) {
847 case SVGA_REG_ID:
848 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
849 s->svgaid = value;
850 break;
851
852 case SVGA_REG_ENABLE:
853 s->enable = value;
854 s->config &= !!value;
855 s->width = -1;
856 s->height = -1;
857 s->invalidated = 1;
858 s->vga.invalidate(&s->vga);
859 if (s->enable) {
860 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
861 vga_dirty_log_stop(&s->vga);
862 } else {
863 vga_dirty_log_start(&s->vga);
864 }
865 break;
866
867 case SVGA_REG_WIDTH:
868 s->new_width = value;
869 s->invalidated = 1;
870 break;
871
872 case SVGA_REG_HEIGHT:
873 s->new_height = value;
874 s->invalidated = 1;
875 break;
876
877 case SVGA_REG_DEPTH:
878 case SVGA_REG_BITS_PER_PIXEL:
879 if (value != s->depth) {
880 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
881 s->config = 0;
882 }
883 break;
884
885 case SVGA_REG_CONFIG_DONE:
886 if (value) {
887 s->fifo = (uint32_t *) s->fifo_ptr;
888 /* Check range and alignment. */
889 if ((CMD(min) | CMD(max) |
890 CMD(next_cmd) | CMD(stop)) & 3)
891 break;
892 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
893 break;
894 if (CMD(max) > SVGA_FIFO_SIZE)
895 break;
896 if (CMD(max) < CMD(min) + 10 * 1024)
897 break;
898 }
899 s->config = !!value;
900 break;
901
902 case SVGA_REG_SYNC:
903 s->syncing = 1;
904 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
905 break;
906
907 case SVGA_REG_GUEST_ID:
908 s->guest = value;
909 #ifdef VERBOSE
910 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
911 ARRAY_SIZE(vmsvga_guest_id))
912 printf("%s: guest runs %s.\n", __FUNCTION__,
913 vmsvga_guest_id[value - GUEST_OS_BASE]);
914 #endif
915 break;
916
917 case SVGA_REG_CURSOR_ID:
918 s->cursor.id = value;
919 break;
920
921 case SVGA_REG_CURSOR_X:
922 s->cursor.x = value;
923 break;
924
925 case SVGA_REG_CURSOR_Y:
926 s->cursor.y = value;
927 break;
928
929 case SVGA_REG_CURSOR_ON:
930 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
931 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
932 #ifdef HW_MOUSE_ACCEL
933 if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
934 s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
935 #endif
936 break;
937
938 case SVGA_REG_MEM_REGS:
939 case SVGA_REG_NUM_DISPLAYS:
940 case SVGA_REG_PITCHLOCK:
941 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
942 break;
943
944 default:
945 if (s->index >= SVGA_SCRATCH_BASE &&
946 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
947 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
948 break;
949 }
950 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
951 }
952 }
953
954 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
955 {
956 printf("%s: what are we supposed to return?\n", __FUNCTION__);
957 return 0xcafe;
958 }
959
960 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
961 {
962 printf("%s: what are we supposed to do with (%08x)?\n",
963 __FUNCTION__, data);
964 }
965
966 static inline void vmsvga_size(struct vmsvga_state_s *s)
967 {
968 if (s->new_width != s->width || s->new_height != s->height) {
969 s->width = s->new_width;
970 s->height = s->new_height;
971 qemu_console_resize(s->vga.ds, s->width, s->height);
972 s->invalidated = 1;
973 }
974 }
975
976 static void vmsvga_update_display(void *opaque)
977 {
978 struct vmsvga_state_s *s = opaque;
979 if (!s->enable) {
980 s->vga.update(&s->vga);
981 return;
982 }
983
984 vmsvga_size(s);
985
986 vmsvga_fifo_run(s);
987 vmsvga_update_rect_flush(s);
988
989 /*
990 * Is it more efficient to look at vram VGA-dirty bits or wait
991 * for the driver to issue SVGA_CMD_UPDATE?
992 */
993 if (s->invalidated) {
994 s->invalidated = 0;
995 vmsvga_update_screen(s);
996 }
997 }
998
999 static void vmsvga_reset(struct vmsvga_state_s *s)
1000 {
1001 s->index = 0;
1002 s->enable = 0;
1003 s->config = 0;
1004 s->width = -1;
1005 s->height = -1;
1006 s->svgaid = SVGA_ID;
1007 s->depth = ds_get_bits_per_pixel(s->vga.ds);
1008 s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
1009 s->cursor.on = 0;
1010 s->redraw_fifo_first = 0;
1011 s->redraw_fifo_last = 0;
1012 switch (s->depth) {
1013 case 8:
1014 s->wred = 0x00000007;
1015 s->wgreen = 0x00000038;
1016 s->wblue = 0x000000c0;
1017 break;
1018 case 15:
1019 s->wred = 0x0000001f;
1020 s->wgreen = 0x000003e0;
1021 s->wblue = 0x00007c00;
1022 break;
1023 case 16:
1024 s->wred = 0x0000001f;
1025 s->wgreen = 0x000007e0;
1026 s->wblue = 0x0000f800;
1027 break;
1028 case 24:
1029 s->wred = 0x00ff0000;
1030 s->wgreen = 0x0000ff00;
1031 s->wblue = 0x000000ff;
1032 break;
1033 case 32:
1034 s->wred = 0x00ff0000;
1035 s->wgreen = 0x0000ff00;
1036 s->wblue = 0x000000ff;
1037 break;
1038 }
1039 s->syncing = 0;
1040
1041 vga_dirty_log_start(&s->vga);
1042 }
1043
1044 static void vmsvga_invalidate_display(void *opaque)
1045 {
1046 struct vmsvga_state_s *s = opaque;
1047 if (!s->enable) {
1048 s->vga.invalidate(&s->vga);
1049 return;
1050 }
1051
1052 s->invalidated = 1;
1053 }
1054
1055 /* save the vga display in a PPM image even if no display is
1056 available */
1057 static void vmsvga_screen_dump(void *opaque, const char *filename)
1058 {
1059 struct vmsvga_state_s *s = opaque;
1060 if (!s->enable) {
1061 s->vga.screen_dump(&s->vga, filename);
1062 return;
1063 }
1064
1065 if (s->depth == 32) {
1066 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
1067 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
1068 ppm_save(filename, ds);
1069 qemu_free(ds);
1070 }
1071 }
1072
1073 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1074 {
1075 struct vmsvga_state_s *s = opaque;
1076
1077 if (s->vga.text_update)
1078 s->vga.text_update(&s->vga, chardata);
1079 }
1080
1081 #ifdef DIRECT_VRAM
1082 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
1083 {
1084 struct vmsvga_state_s *s = opaque;
1085 if (addr < s->fb_size)
1086 return *(uint8_t *) (ds_get_data(s->ds) + addr);
1087 else
1088 return *(uint8_t *) (s->vram_ptr + addr);
1089 }
1090
1091 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
1092 {
1093 struct vmsvga_state_s *s = opaque;
1094 if (addr < s->fb_size)
1095 return *(uint16_t *) (ds_get_data(s->ds) + addr);
1096 else
1097 return *(uint16_t *) (s->vram_ptr + addr);
1098 }
1099
1100 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1101 {
1102 struct vmsvga_state_s *s = opaque;
1103 if (addr < s->fb_size)
1104 return *(uint32_t *) (ds_get_data(s->ds) + addr);
1105 else
1106 return *(uint32_t *) (s->vram_ptr + addr);
1107 }
1108
1109 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1110 uint32_t value)
1111 {
1112 struct vmsvga_state_s *s = opaque;
1113 if (addr < s->fb_size)
1114 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
1115 else
1116 *(uint8_t *) (s->vram_ptr + addr) = value;
1117 }
1118
1119 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1120 uint32_t value)
1121 {
1122 struct vmsvga_state_s *s = opaque;
1123 if (addr < s->fb_size)
1124 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
1125 else
1126 *(uint16_t *) (s->vram_ptr + addr) = value;
1127 }
1128
1129 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1130 uint32_t value)
1131 {
1132 struct vmsvga_state_s *s = opaque;
1133 if (addr < s->fb_size)
1134 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
1135 else
1136 *(uint32_t *) (s->vram_ptr + addr) = value;
1137 }
1138
1139 static CPUReadMemoryFunc * const vmsvga_vram_read[] = {
1140 vmsvga_vram_readb,
1141 vmsvga_vram_readw,
1142 vmsvga_vram_readl,
1143 };
1144
1145 static CPUWriteMemoryFunc * const vmsvga_vram_write[] = {
1146 vmsvga_vram_writeb,
1147 vmsvga_vram_writew,
1148 vmsvga_vram_writel,
1149 };
1150 #endif
1151
1152 static int vmsvga_post_load(void *opaque, int version_id)
1153 {
1154 struct vmsvga_state_s *s = opaque;
1155
1156 s->invalidated = 1;
1157 if (s->config)
1158 s->fifo = (uint32_t *) s->fifo_ptr;
1159
1160 return 0;
1161 }
1162
1163 static const VMStateDescription vmstate_vmware_vga_internal = {
1164 .name = "vmware_vga_internal",
1165 .version_id = 0,
1166 .minimum_version_id = 0,
1167 .minimum_version_id_old = 0,
1168 .post_load = vmsvga_post_load,
1169 .fields = (VMStateField []) {
1170 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1171 VMSTATE_INT32(enable, struct vmsvga_state_s),
1172 VMSTATE_INT32(config, struct vmsvga_state_s),
1173 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1174 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1175 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1176 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1177 VMSTATE_INT32(index, struct vmsvga_state_s),
1178 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1179 scratch_size, 0, vmstate_info_uint32, uint32_t),
1180 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1181 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1182 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1183 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1184 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1185 VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1186 VMSTATE_END_OF_LIST()
1187 }
1188 };
1189
1190 static const VMStateDescription vmstate_vmware_vga = {
1191 .name = "vmware_vga",
1192 .version_id = 0,
1193 .minimum_version_id = 0,
1194 .minimum_version_id_old = 0,
1195 .fields = (VMStateField []) {
1196 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1197 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1198 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1199 VMSTATE_END_OF_LIST()
1200 }
1201 };
1202
1203 static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
1204 {
1205 s->scratch_size = SVGA_SCRATCH_SIZE;
1206 s->scratch = qemu_malloc(s->scratch_size * 4);
1207
1208 s->vga.ds = graphic_console_init(vmsvga_update_display,
1209 vmsvga_invalidate_display,
1210 vmsvga_screen_dump,
1211 vmsvga_text_update, s);
1212
1213
1214 s->fifo_size = SVGA_FIFO_SIZE;
1215 s->fifo_offset = qemu_ram_alloc(NULL, "vmsvga.fifo", s->fifo_size);
1216 s->fifo_ptr = qemu_get_ram_ptr(s->fifo_offset);
1217
1218 vga_common_init(&s->vga, vga_ram_size);
1219 vga_init(&s->vga);
1220 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1221
1222 vga_init_vbe(&s->vga);
1223
1224 rom_add_vga(VGABIOS_FILENAME);
1225
1226 vmsvga_reset(s);
1227 }
1228
1229 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1230 pcibus_t addr, pcibus_t size, int type)
1231 {
1232 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1233 struct vmsvga_state_s *s = &d->chip;
1234
1235 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1236 1, 4, vmsvga_index_read, s);
1237 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1238 1, 4, vmsvga_index_write, s);
1239 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1240 1, 4, vmsvga_value_read, s);
1241 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1242 1, 4, vmsvga_value_write, s);
1243 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1244 1, 4, vmsvga_bios_read, s);
1245 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1246 1, 4, vmsvga_bios_write, s);
1247 }
1248
1249 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1250 pcibus_t addr, pcibus_t size, int type)
1251 {
1252 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1253 struct vmsvga_state_s *s = &d->chip;
1254 ram_addr_t iomemtype;
1255
1256 s->vram_base = addr;
1257 #ifdef DIRECT_VRAM
1258 iomemtype = cpu_register_io_memory(vmsvga_vram_read,
1259 vmsvga_vram_write, s);
1260 #else
1261 iomemtype = s->vga.vram_offset | IO_MEM_RAM;
1262 #endif
1263 cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
1264 iomemtype);
1265
1266 s->vga.map_addr = addr;
1267 s->vga.map_end = addr + s->vga.vram_size;
1268 vga_dirty_log_restart(&s->vga);
1269 }
1270
1271 static void pci_vmsvga_map_fifo(PCIDevice *pci_dev, int region_num,
1272 pcibus_t addr, pcibus_t size, int type)
1273 {
1274 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1275 struct vmsvga_state_s *s = &d->chip;
1276 ram_addr_t iomemtype;
1277
1278 s->fifo_base = addr;
1279 iomemtype = s->fifo_offset | IO_MEM_RAM;
1280 cpu_register_physical_memory(s->fifo_base, s->fifo_size,
1281 iomemtype);
1282 }
1283
1284 static int pci_vmsvga_initfn(PCIDevice *dev)
1285 {
1286 struct pci_vmsvga_state_s *s =
1287 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1288
1289 pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1290 pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
1291 pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
1292 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
1293 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
1294 s->card.config[PCI_SUBSYSTEM_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
1295 s->card.config[PCI_SUBSYSTEM_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
1296 s->card.config[PCI_SUBSYSTEM_ID] = SVGA_PCI_DEVICE_ID & 0xff;
1297 s->card.config[PCI_SUBSYSTEM_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
1298 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
1299
1300 pci_register_bar(&s->card, 0, 0x10,
1301 PCI_BASE_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1302 pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
1303 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_mem);
1304
1305 pci_register_bar(&s->card, 2, SVGA_FIFO_SIZE,
1306 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_fifo);
1307
1308 vmsvga_init(&s->chip, VGA_RAM_SIZE);
1309
1310 return 0;
1311 }
1312
1313 void pci_vmsvga_init(PCIBus *bus)
1314 {
1315 pci_create_simple(bus, -1, "vmware-svga");
1316 }
1317
1318 static PCIDeviceInfo vmsvga_info = {
1319 .qdev.name = "vmware-svga",
1320 .qdev.size = sizeof(struct pci_vmsvga_state_s),
1321 .qdev.vmsd = &vmstate_vmware_vga,
1322 .init = pci_vmsvga_initfn,
1323 };
1324
1325 static void vmsvga_register(void)
1326 {
1327 pci_qdev_register(&vmsvga_info);
1328 }
1329 device_init(vmsvga_register);
Patch queue for openSUSE QEMU