hw/spapr_pci.c

   1 /*
   2  * QEMU sPAPR PCI host originated from Uninorth PCI host
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
   5  * Copyright (C) 2011 David Gibson, IBM Corporation.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "hw/spapr.h"
  29 #include "hw/spapr_pci.h"
  30 #include "exec-memory.h"
  31 #include <libfdt.h>
  32
  33 #include "hw/pci_internals.h"
  34
  35 static PCIDevice *find_dev(sPAPREnvironment *spapr,
  36                            uint64_t buid, uint32_t config_addr)
  37 {
  38     int devfn = (config_addr >> 8) & 0xFF;
  39     sPAPRPHBState *phb;
  40
  41     QLIST_FOREACH(phb, &spapr->phbs, list) {
  42         BusChild *kid;
  43
  44         if (phb->buid != buid) {
  45             continue;
  46         }
  47
  48         QTAILQ_FOREACH(kid, &phb->host_state.bus->qbus.children, sibling) {
  49             PCIDevice *dev = (PCIDevice *)kid->child;
  50             if (dev->devfn == devfn) {
  51                 return dev;
  52             }
  53         }
  54     }
  55
  56     return NULL;
  57 }
  58
  59 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
  60 {
  61     /* This handles the encoding of extended config space addresses */
  62     return ((arg >> 20) & 0xf00) | (arg & 0xff);
  63 }
  64
  65 static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
  66                                    uint32_t addr, uint32_t size,
  67                                    target_ulong rets)
  68 {
  69     PCIDevice *pci_dev;
  70     uint32_t val;
  71
  72     if ((size != 1) && (size != 2) && (size != 4)) {
  73         /* access must be 1, 2 or 4 bytes */
  74         rtas_st(rets, 0, -1);
  75         return;
  76     }
  77
  78     pci_dev = find_dev(spapr, buid, addr);
  79     addr = rtas_pci_cfgaddr(addr);
  80
  81     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
  82         /* Access must be to a valid device, within bounds and
  83          * naturally aligned */
  84         rtas_st(rets, 0, -1);
  85         return;
  86     }
  87
  88     val = pci_host_config_read_common(pci_dev, addr,
  89                                       pci_config_size(pci_dev), size);
  90
  91     rtas_st(rets, 0, 0);
  92     rtas_st(rets, 1, val);
  93 }
  94
  95 static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
  96                                      uint32_t token, uint32_t nargs,
  97                                      target_ulong args,
  98                                      uint32_t nret, target_ulong rets)
  99 {
 100     uint64_t buid;
 101     uint32_t size, addr;
 102
 103     if ((nargs != 4) || (nret != 2)) {
 104         rtas_st(rets, 0, -1);
 105         return;
 106     }
 107
 108     buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 109     size = rtas_ld(args, 3);
 110     addr = rtas_ld(args, 0);
 111
 112     finish_read_pci_config(spapr, buid, addr, size, rets);
 113 }
 114
 115 static void rtas_read_pci_config(sPAPREnvironment *spapr,
 116                                  uint32_t token, uint32_t nargs,
 117                                  target_ulong args,
 118                                  uint32_t nret, target_ulong rets)
 119 {
 120     uint32_t size, addr;
 121
 122     if ((nargs != 2) || (nret != 2)) {
 123         rtas_st(rets, 0, -1);
 124         return;
 125     }
 126
 127     size = rtas_ld(args, 1);
 128     addr = rtas_ld(args, 0);
 129
 130     finish_read_pci_config(spapr, 0, addr, size, rets);
 131 }
 132
 133 static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
 134                                     uint32_t addr, uint32_t size,
 135                                     uint32_t val, target_ulong rets)
 136 {
 137     PCIDevice *pci_dev;
 138
 139     if ((size != 1) && (size != 2) && (size != 4)) {
 140         /* access must be 1, 2 or 4 bytes */
 141         rtas_st(rets, 0, -1);
 142         return;
 143     }
 144
 145     pci_dev = find_dev(spapr, buid, addr);
 146     addr = rtas_pci_cfgaddr(addr);
 147
 148     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
 149         /* Access must be to a valid device, within bounds and
 150          * naturally aligned */
 151         rtas_st(rets, 0, -1);
 152         return;
 153     }
 154
 155     pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
 156                                  val, size);
 157
 158     rtas_st(rets, 0, 0);
 159 }
 160
 161 static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
 162                                       uint32_t token, uint32_t nargs,
 163                                       target_ulong args,
 164                                       uint32_t nret, target_ulong rets)
 165 {
 166     uint64_t buid;
 167     uint32_t val, size, addr;
 168
 169     if ((nargs != 5) || (nret != 1)) {
 170         rtas_st(rets, 0, -1);
 171         return;
 172     }
 173
 174     buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 175     val = rtas_ld(args, 4);
 176     size = rtas_ld(args, 3);
 177     addr = rtas_ld(args, 0);
 178
 179     finish_write_pci_config(spapr, buid, addr, size, val, rets);
 180 }
 181
 182 static void rtas_write_pci_config(sPAPREnvironment *spapr,
 183                                   uint32_t token, uint32_t nargs,
 184                                   target_ulong args,
 185                                   uint32_t nret, target_ulong rets)
 186 {
 187     uint32_t val, size, addr;
 188
 189     if ((nargs != 3) || (nret != 1)) {
 190         rtas_st(rets, 0, -1);
 191         return;
 192     }
 193
 194
 195     val = rtas_ld(args, 2);
 196     size = rtas_ld(args, 1);
 197     addr = rtas_ld(args, 0);
 198
 199     finish_write_pci_config(spapr, 0, addr, size, val, rets);
 200 }
 201
 202 static int pci_spapr_swizzle(int slot, int pin)
 203 {
 204     return (slot + pin) % PCI_NUM_PINS;
 205 }
 206
 207 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
 208 {
 209     /*
 210      * Here we need to convert pci_dev + irq_num to some unique value
 211      * which is less than number of IRQs on the specific bus (4).  We
 212      * use standard PCI swizzling, that is (slot number + pin number)
 213      * % 4.
 214      */
 215     return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
 216 }
 217
 218 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
 219 {
 220     /*
 221      * Here we use the number returned by pci_spapr_map_irq to find a
 222      * corresponding qemu_irq.
 223      */
 224     sPAPRPHBState *phb = opaque;
 225
 226     qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
 227 }
 228
 229 static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
 230                               unsigned size)
 231 {
 232     switch (size) {
 233     case 1:
 234         return cpu_inb(addr);
 235     case 2:
 236         return cpu_inw(addr);
 237     case 4:
 238         return cpu_inl(addr);
 239     }
 240     assert(0);
 241 }
 242
 243 static void spapr_io_write(void *opaque, target_phys_addr_t addr,
 244                            uint64_t data, unsigned size)
 245 {
 246     switch (size) {
 247     case 1:
 248         cpu_outb(addr, data);
 249         return;
 250     case 2:
 251         cpu_outw(addr, data);
 252         return;
 253     case 4:
 254         cpu_outl(addr, data);
 255         return;
 256     }
 257     assert(0);
 258 }
 259
 260 static const MemoryRegionOps spapr_io_ops = {
 261     .endianness = DEVICE_LITTLE_ENDIAN,
 262     .read = spapr_io_read,
 263     .write = spapr_io_write
 264 };
 265
 266 /*
 267  * PHB PCI device
 268  */
 269 static int spapr_phb_init(SysBusDevice *s)
 270 {
 271     sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
 272     char *namebuf;
 273     int i;
 274     PCIBus *bus;
 275
 276     phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid);
 277     namebuf = alloca(strlen(phb->dtbusname) + 32);
 278
 279     /* Initialize memory regions */
 280     sprintf(namebuf, "%s.mmio", phb->dtbusname);
 281     memory_region_init(&phb->memspace, namebuf, INT64_MAX);
 282
 283     sprintf(namebuf, "%s.mmio-alias", phb->dtbusname);
 284     memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
 285                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size);
 286     memory_region_add_subregion(get_system_memory(), phb->mem_win_addr,
 287                                 &phb->memwindow);
 288
 289     /* On ppc, we only have MMIO no specific IO space from the CPU
 290      * perspective.  In theory we ought to be able to embed the PCI IO
 291      * memory region direction in the system memory space.  However,
 292      * if any of the IO BAR subregions use the old_portio mechanism,
 293      * that won't be processed properly unless accessed from the
 294      * system io address space.  This hack to bounce things via
 295      * system_io works around the problem until all the users of
 296      * old_portion are updated */
 297     sprintf(namebuf, "%s.io", phb->dtbusname);
 298     memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
 299     /* FIXME: fix to support multiple PHBs */
 300     memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
 301
 302     sprintf(namebuf, "%s.io-alias", phb->dtbusname);
 303     memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
 304                           namebuf, SPAPR_PCI_IO_WIN_SIZE);
 305     memory_region_add_subregion(get_system_memory(), phb->io_win_addr,
 306                                 &phb->iowindow);
 307
 308     bus = pci_register_bus(&phb->busdev.qdev,
 309                            phb->busname ? phb->busname : phb->dtbusname,
 310                            pci_spapr_set_irq, pci_spapr_map_irq, phb,
 311                            &phb->memspace, &phb->iospace,
 312                            PCI_DEVFN(0, 0), PCI_NUM_PINS);
 313     phb->host_state.bus = bus;
 314
 315     QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
 316
 317     /* Initialize the LSI table */
 318     for (i = 0; i < PCI_NUM_PINS; i++) {
 319         qemu_irq qirq;
 320         uint32_t num;
 321
 322         qirq = spapr_allocate_lsi(0, &num);
 323         if (!qirq) {
 324             return -1;
 325         }
 326
 327         phb->lsi_table[i].dt_irq = num;
 328         phb->lsi_table[i].qirq = qirq;
 329     }
 330
 331     return 0;
 332 }
 333
 334 static Property spapr_phb_properties[] = {
 335     DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
 336     DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
 337     DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
 338     DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
 339     DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
 340     DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
 341     DEFINE_PROP_END_OF_LIST(),
 342 };
 343
 344 static void spapr_phb_class_init(ObjectClass *klass, void *data)
 345 {
 346     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 347     DeviceClass *dc = DEVICE_CLASS(klass);
 348
 349     sdc->init = spapr_phb_init;
 350     dc->props = spapr_phb_properties;
 351
 352     spapr_rtas_register("read-pci-config", rtas_read_pci_config);
 353     spapr_rtas_register("write-pci-config", rtas_write_pci_config);
 354     spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
 355     spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
 356 }
 357
 358 static TypeInfo spapr_phb_info = {
 359     .name          = "spapr-pci-host-bridge",
 360     .parent        = TYPE_SYS_BUS_DEVICE,
 361     .instance_size = sizeof(sPAPRPHBState),
 362     .class_init    = spapr_phb_class_init,
 363 };
 364
 365 void spapr_create_phb(sPAPREnvironment *spapr,
 366                       const char *busname, uint64_t buid,
 367                       uint64_t mem_win_addr, uint64_t mem_win_size,
 368                       uint64_t io_win_addr)
 369 {
 370     DeviceState *dev;
 371
 372     dev = qdev_create(NULL, spapr_phb_info.name);
 373
 374     if (busname) {
 375         qdev_prop_set_string(dev, "busname", g_strdup(busname));
 376     }
 377     qdev_prop_set_uint64(dev, "buid", buid);
 378     qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
 379     qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
 380     qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);
 381
 382     qdev_init_nofail(dev);
 383 }
 384
 385 /* Macros to operate with address in OF binding to PCI */
 386 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
 387 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
 388 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
 389 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
 390 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
 391 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
 392 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
 393 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
 394 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
 395
 396 int spapr_populate_pci_devices(sPAPRPHBState *phb,
 397                                uint32_t xics_phandle,
 398                                void *fdt)
 399 {
 400     int bus_off, i, j;
 401     char nodename[256];
 402     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
 403     struct {
 404         uint32_t hi;
 405         uint64_t child;
 406         uint64_t parent;
 407         uint64_t size;
 408     } __attribute__((packed)) ranges[] = {
 409         {
 410             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
 411             cpu_to_be64(phb->io_win_addr),
 412             cpu_to_be64(memory_region_size(&phb->iospace)),
 413         },
 414         {
 415             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
 416             cpu_to_be64(phb->mem_win_addr),
 417             cpu_to_be64(memory_region_size(&phb->memwindow)),
 418         },
 419     };
 420     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
 421     uint32_t interrupt_map_mask[] = {
 422         cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
 423     uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
 424
 425     /* Start populating the FDT */
 426     sprintf(nodename, "pci@%" PRIx64, phb->buid);
 427     bus_off = fdt_add_subnode(fdt, 0, nodename);
 428     if (bus_off < 0) {
 429         return bus_off;
 430     }
 431
 432 #define _FDT(exp) \
 433     do { \
 434         int ret = (exp);                                           \
 435         if (ret < 0) {                                             \
 436             return ret;                                            \
 437         }                                                          \
 438     } while (0)
 439
 440     /* Write PHB properties */
 441     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
 442     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
 443     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
 444     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
 445     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
 446     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
 447     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
 448     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
 449     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
 450     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
 451
 452     /* Build the interrupt-map, this must matches what is done
 453      * in pci_spapr_map_irq
 454      */
 455     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
 456                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
 457     for (i = 0; i < PCI_SLOT_MAX; i++) {
 458         for (j = 0; j < PCI_NUM_PINS; j++) {
 459             uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
 460             int lsi_num = pci_spapr_swizzle(i, j);
 461
 462             irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
 463             irqmap[1] = 0;
 464             irqmap[2] = 0;
 465             irqmap[3] = cpu_to_be32(j+1);
 466             irqmap[4] = cpu_to_be32(xics_phandle);
 467             irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].dt_irq);
 468             irqmap[6] = cpu_to_be32(0x8);
 469         }
 470     }
 471     /* Write interrupt map */
 472     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
 473                      sizeof(interrupt_map)));
 474
 475     return 0;
 476 }
 477
 478 static void register_types(void)
 479 {
 480     type_register_static(&spapr_phb_info);
 481 }
 482 type_init(register_types)