hw/usb/hcd-uhci.c

   1 /*
   2  * USB UHCI controller emulation
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Copyright (c) 2008 Max Krasnyansky
   7  *     Magor rewrite of the UHCI data structures parser and frame processor
   8  *     Support for fully async operation and multiple outstanding transactions
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28 #include "hw/hw.h"
  29 #include "hw/usb.h"
  30 #include "hw/pci.h"
  31 #include "qemu-timer.h"
  32 #include "iov.h"
  33 #include "dma.h"
  34 #include "trace.h"
  35
  36 //#define DEBUG
  37 //#define DEBUG_DUMP_DATA
  38
  39 #define UHCI_CMD_FGR      (1 << 4)
  40 #define UHCI_CMD_EGSM     (1 << 3)
  41 #define UHCI_CMD_GRESET   (1 << 2)
  42 #define UHCI_CMD_HCRESET  (1 << 1)
  43 #define UHCI_CMD_RS       (1 << 0)
  44
  45 #define UHCI_STS_HCHALTED (1 << 5)
  46 #define UHCI_STS_HCPERR   (1 << 4)
  47 #define UHCI_STS_HSERR    (1 << 3)
  48 #define UHCI_STS_RD       (1 << 2)
  49 #define UHCI_STS_USBERR   (1 << 1)
  50 #define UHCI_STS_USBINT   (1 << 0)
  51
  52 #define TD_CTRL_SPD     (1 << 29)
  53 #define TD_CTRL_ERROR_SHIFT  27
  54 #define TD_CTRL_IOS     (1 << 25)
  55 #define TD_CTRL_IOC     (1 << 24)
  56 #define TD_CTRL_ACTIVE  (1 << 23)
  57 #define TD_CTRL_STALL   (1 << 22)
  58 #define TD_CTRL_BABBLE  (1 << 20)
  59 #define TD_CTRL_NAK     (1 << 19)
  60 #define TD_CTRL_TIMEOUT (1 << 18)
  61
  62 #define UHCI_PORT_SUSPEND (1 << 12)
  63 #define UHCI_PORT_RESET (1 << 9)
  64 #define UHCI_PORT_LSDA  (1 << 8)
  65 #define UHCI_PORT_RD    (1 << 6)
  66 #define UHCI_PORT_ENC   (1 << 3)
  67 #define UHCI_PORT_EN    (1 << 2)
  68 #define UHCI_PORT_CSC   (1 << 1)
  69 #define UHCI_PORT_CCS   (1 << 0)
  70
  71 #define UHCI_PORT_READ_ONLY    (0x1bb)
  72 #define UHCI_PORT_WRITE_CLEAR  (UHCI_PORT_CSC | UHCI_PORT_ENC)
  73
  74 #define FRAME_TIMER_FREQ 1000
  75
  76 #define FRAME_MAX_LOOPS  256
  77
  78 #define NB_PORTS 2
  79
  80 enum {
  81     TD_RESULT_STOP_FRAME = 10,
  82     TD_RESULT_COMPLETE,
  83     TD_RESULT_NEXT_QH,
  84     TD_RESULT_ASYNC_START,
  85     TD_RESULT_ASYNC_CONT,
  86 };
  87
  88 typedef struct UHCIState UHCIState;
  89 typedef struct UHCIAsync UHCIAsync;
  90 typedef struct UHCIQueue UHCIQueue;
  91
  92 /*
  93  * Pending async transaction.
  94  * 'packet' must be the first field because completion
  95  * handler does "(UHCIAsync *) pkt" cast.
  96  */
  97
  98 struct UHCIAsync {
  99     USBPacket packet;
 100     QEMUSGList sgl;
 101     UHCIQueue *queue;
 102     QTAILQ_ENTRY(UHCIAsync) next;
 103     uint32_t  td;
 104     uint8_t   isoc;
 105     uint8_t   done;
 106 };
 107
 108 struct UHCIQueue {
 109     uint32_t  token;
 110     UHCIState *uhci;
 111     QTAILQ_ENTRY(UHCIQueue) next;
 112     QTAILQ_HEAD(, UHCIAsync) asyncs;
 113     int8_t    valid;
 114 };
 115
 116 typedef struct UHCIPort {
 117     USBPort port;
 118     uint16_t ctrl;
 119 } UHCIPort;
 120
 121 struct UHCIState {
 122     PCIDevice dev;
 123     MemoryRegion io_bar;
 124     USBBus bus; /* Note unused when we're a companion controller */
 125     uint16_t cmd; /* cmd register */
 126     uint16_t status;
 127     uint16_t intr; /* interrupt enable register */
 128     uint16_t frnum; /* frame number */
 129     uint32_t fl_base_addr; /* frame list base address */
 130     uint8_t sof_timing;
 131     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
 132     int64_t expire_time;
 133     QEMUTimer *frame_timer;
 134     QEMUBH *bh;
 135     uint32_t frame_bytes;
 136     uint32_t frame_bandwidth;
 137     UHCIPort ports[NB_PORTS];
 138
 139     /* Interrupts that should be raised at the end of the current frame.  */
 140     uint32_t pending_int_mask;
 141     int irq_pin;
 142
 143     /* Active packets */
 144     QTAILQ_HEAD(, UHCIQueue) queues;
 145     uint8_t num_ports_vmstate;
 146
 147     /* Properties */
 148     char *masterbus;
 149     uint32_t firstport;
 150 };
 151
 152 typedef struct UHCI_TD {
 153     uint32_t link;
 154     uint32_t ctrl; /* see TD_CTRL_xxx */
 155     uint32_t token;
 156     uint32_t buffer;
 157 } UHCI_TD;
 158
 159 typedef struct UHCI_QH {
 160     uint32_t link;
 161     uint32_t el_link;
 162 } UHCI_QH;
 163
 164 static inline int32_t uhci_queue_token(UHCI_TD *td)
 165 {
 166     /* covers ep, dev, pid -> identifies the endpoint */
 167     return td->token & 0x7ffff;
 168 }
 169
 170 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td)
 171 {
 172     uint32_t token = uhci_queue_token(td);
 173     UHCIQueue *queue;
 174
 175     QTAILQ_FOREACH(queue, &s->queues, next) {
 176         if (queue->token == token) {
 177             return queue;
 178         }
 179     }
 180
 181     queue = g_new0(UHCIQueue, 1);
 182     queue->uhci = s;
 183     queue->token = token;
 184     QTAILQ_INIT(&queue->asyncs);
 185     QTAILQ_INSERT_HEAD(&s->queues, queue, next);
 186     trace_usb_uhci_queue_add(queue->token);
 187     return queue;
 188 }
 189
 190 static void uhci_queue_free(UHCIQueue *queue)
 191 {
 192     UHCIState *s = queue->uhci;
 193
 194     trace_usb_uhci_queue_del(queue->token);
 195     QTAILQ_REMOVE(&s->queues, queue, next);
 196     g_free(queue);
 197 }
 198
 199 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr)
 200 {
 201     UHCIAsync *async = g_new0(UHCIAsync, 1);
 202
 203     async->queue = queue;
 204     async->td = addr;
 205     usb_packet_init(&async->packet);
 206     pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
 207     trace_usb_uhci_packet_add(async->queue->token, async->td);
 208
 209     return async;
 210 }
 211
 212 static void uhci_async_free(UHCIAsync *async)
 213 {
 214     trace_usb_uhci_packet_del(async->queue->token, async->td);
 215     usb_packet_cleanup(&async->packet);
 216     qemu_sglist_destroy(&async->sgl);
 217     g_free(async);
 218 }
 219
 220 static void uhci_async_link(UHCIAsync *async)
 221 {
 222     UHCIQueue *queue = async->queue;
 223     QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
 224     trace_usb_uhci_packet_link_async(async->queue->token, async->td);
 225 }
 226
 227 static void uhci_async_unlink(UHCIAsync *async)
 228 {
 229     UHCIQueue *queue = async->queue;
 230     QTAILQ_REMOVE(&queue->asyncs, async, next);
 231     trace_usb_uhci_packet_unlink_async(async->queue->token, async->td);
 232 }
 233
 234 static void uhci_async_cancel(UHCIAsync *async)
 235 {
 236     trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done);
 237     if (!async->done)
 238         usb_cancel_packet(&async->packet);
 239     uhci_async_free(async);
 240 }
 241
 242 /*
 243  * Mark all outstanding async packets as invalid.
 244  * This is used for canceling them when TDs are removed by the HCD.
 245  */
 246 static void uhci_async_validate_begin(UHCIState *s)
 247 {
 248     UHCIQueue *queue;
 249
 250     QTAILQ_FOREACH(queue, &s->queues, next) {
 251         queue->valid--;
 252     }
 253 }
 254
 255 /*
 256  * Cancel async packets that are no longer valid
 257  */
 258 static void uhci_async_validate_end(UHCIState *s)
 259 {
 260     UHCIQueue *queue, *n;
 261     UHCIAsync *async;
 262
 263     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
 264         if (queue->valid > 0) {
 265             continue;
 266         }
 267         while (!QTAILQ_EMPTY(&queue->asyncs)) {
 268             async = QTAILQ_FIRST(&queue->asyncs);
 269             uhci_async_unlink(async);
 270             uhci_async_cancel(async);
 271         }
 272         uhci_queue_free(queue);
 273     }
 274 }
 275
 276 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
 277 {
 278     UHCIQueue *queue;
 279     UHCIAsync *curr, *n;
 280
 281     QTAILQ_FOREACH(queue, &s->queues, next) {
 282         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 283             if (!usb_packet_is_inflight(&curr->packet) ||
 284                 curr->packet.ep->dev != dev) {
 285                 continue;
 286             }
 287             uhci_async_unlink(curr);
 288             uhci_async_cancel(curr);
 289         }
 290     }
 291 }
 292
 293 static void uhci_async_cancel_all(UHCIState *s)
 294 {
 295     UHCIQueue *queue;
 296     UHCIAsync *curr, *n;
 297
 298     QTAILQ_FOREACH(queue, &s->queues, next) {
 299         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 300             uhci_async_unlink(curr);
 301             uhci_async_cancel(curr);
 302         }
 303         uhci_queue_free(queue);
 304     }
 305 }
 306
 307 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td)
 308 {
 309     uint32_t token = uhci_queue_token(td);
 310     UHCIQueue *queue;
 311     UHCIAsync *async;
 312
 313     QTAILQ_FOREACH(queue, &s->queues, next) {
 314         if (queue->token == token) {
 315             break;
 316         }
 317     }
 318     if (queue == NULL) {
 319         return NULL;
 320     }
 321
 322     QTAILQ_FOREACH(async, &queue->asyncs, next) {
 323         if (async->td == addr) {
 324             return async;
 325         }
 326     }
 327
 328     return NULL;
 329 }
 330
 331 static void uhci_update_irq(UHCIState *s)
 332 {
 333     int level;
 334     if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
 335         ((s->status2 & 2) && (s->intr & (1 << 3))) ||
 336         ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
 337         ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
 338         (s->status & UHCI_STS_HSERR) ||
 339         (s->status & UHCI_STS_HCPERR)) {
 340         level = 1;
 341     } else {
 342         level = 0;
 343     }
 344     qemu_set_irq(s->dev.irq[s->irq_pin], level);
 345 }
 346
 347 static void uhci_reset(void *opaque)
 348 {
 349     UHCIState *s = opaque;
 350     uint8_t *pci_conf;
 351     int i;
 352     UHCIPort *port;
 353
 354     trace_usb_uhci_reset();
 355
 356     pci_conf = s->dev.config;
 357
 358     pci_conf[0x6a] = 0x01; /* usb clock */
 359     pci_conf[0x6b] = 0x00;
 360     s->cmd = 0;
 361     s->status = 0;
 362     s->status2 = 0;
 363     s->intr = 0;
 364     s->fl_base_addr = 0;
 365     s->sof_timing = 64;
 366
 367     for(i = 0; i < NB_PORTS; i++) {
 368         port = &s->ports[i];
 369         port->ctrl = 0x0080;
 370         if (port->port.dev && port->port.dev->attached) {
 371             usb_port_reset(&port->port);
 372         }
 373     }
 374
 375     uhci_async_cancel_all(s);
 376     qemu_bh_cancel(s->bh);
 377     uhci_update_irq(s);
 378 }
 379
 380 static const VMStateDescription vmstate_uhci_port = {
 381     .name = "uhci port",
 382     .version_id = 1,
 383     .minimum_version_id = 1,
 384     .minimum_version_id_old = 1,
 385     .fields      = (VMStateField []) {
 386         VMSTATE_UINT16(ctrl, UHCIPort),
 387         VMSTATE_END_OF_LIST()
 388     }
 389 };
 390
 391 static const VMStateDescription vmstate_uhci = {
 392     .name = "uhci",
 393     .version_id = 2,
 394     .minimum_version_id = 1,
 395     .minimum_version_id_old = 1,
 396     .fields      = (VMStateField []) {
 397         VMSTATE_PCI_DEVICE(dev, UHCIState),
 398         VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
 399         VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
 400                              vmstate_uhci_port, UHCIPort),
 401         VMSTATE_UINT16(cmd, UHCIState),
 402         VMSTATE_UINT16(status, UHCIState),
 403         VMSTATE_UINT16(intr, UHCIState),
 404         VMSTATE_UINT16(frnum, UHCIState),
 405         VMSTATE_UINT32(fl_base_addr, UHCIState),
 406         VMSTATE_UINT8(sof_timing, UHCIState),
 407         VMSTATE_UINT8(status2, UHCIState),
 408         VMSTATE_TIMER(frame_timer, UHCIState),
 409         VMSTATE_INT64_V(expire_time, UHCIState, 2),
 410         VMSTATE_END_OF_LIST()
 411     }
 412 };
 413
 414 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 415 {
 416     UHCIState *s = opaque;
 417
 418     addr &= 0x1f;
 419     switch(addr) {
 420     case 0x0c:
 421         s->sof_timing = val;
 422         break;
 423     }
 424 }
 425
 426 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
 427 {
 428     UHCIState *s = opaque;
 429     uint32_t val;
 430
 431     addr &= 0x1f;
 432     switch(addr) {
 433     case 0x0c:
 434         val = s->sof_timing;
 435         break;
 436     default:
 437         val = 0xff;
 438         break;
 439     }
 440     return val;
 441 }
 442
 443 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 444 {
 445     UHCIState *s = opaque;
 446
 447     addr &= 0x1f;
 448     trace_usb_uhci_mmio_writew(addr, val);
 449
 450     switch(addr) {
 451     case 0x00:
 452         if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
 453             /* start frame processing */
 454             trace_usb_uhci_schedule_start();
 455             s->expire_time = qemu_get_clock_ns(vm_clock) +
 456                 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 457             qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
 458             s->status &= ~UHCI_STS_HCHALTED;
 459         } else if (!(val & UHCI_CMD_RS)) {
 460             s->status |= UHCI_STS_HCHALTED;
 461         }
 462         if (val & UHCI_CMD_GRESET) {
 463             UHCIPort *port;
 464             int i;
 465
 466             /* send reset on the USB bus */
 467             for(i = 0; i < NB_PORTS; i++) {
 468                 port = &s->ports[i];
 469                 usb_device_reset(port->port.dev);
 470             }
 471             uhci_reset(s);
 472             return;
 473         }
 474         if (val & UHCI_CMD_HCRESET) {
 475             uhci_reset(s);
 476             return;
 477         }
 478         s->cmd = val;
 479         break;
 480     case 0x02:
 481         s->status &= ~val;
 482         /* XXX: the chip spec is not coherent, so we add a hidden
 483            register to distinguish between IOC and SPD */
 484         if (val & UHCI_STS_USBINT)
 485             s->status2 = 0;
 486         uhci_update_irq(s);
 487         break;
 488     case 0x04:
 489         s->intr = val;
 490         uhci_update_irq(s);
 491         break;
 492     case 0x06:
 493         if (s->status & UHCI_STS_HCHALTED)
 494             s->frnum = val & 0x7ff;
 495         break;
 496     case 0x10 ... 0x1f:
 497         {
 498             UHCIPort *port;
 499             USBDevice *dev;
 500             int n;
 501
 502             n = (addr >> 1) & 7;
 503             if (n >= NB_PORTS)
 504                 return;
 505             port = &s->ports[n];
 506             dev = port->port.dev;
 507             if (dev && dev->attached) {
 508                 /* port reset */
 509                 if ( (val & UHCI_PORT_RESET) &&
 510                      !(port->ctrl & UHCI_PORT_RESET) ) {
 511                     usb_device_reset(dev);
 512                 }
 513             }
 514             port->ctrl &= UHCI_PORT_READ_ONLY;
 515             port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
 516             /* some bits are reset when a '1' is written to them */
 517             port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
 518         }
 519         break;
 520     }
 521 }
 522
 523 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
 524 {
 525     UHCIState *s = opaque;
 526     uint32_t val;
 527
 528     addr &= 0x1f;
 529     switch(addr) {
 530     case 0x00:
 531         val = s->cmd;
 532         break;
 533     case 0x02:
 534         val = s->status;
 535         break;
 536     case 0x04:
 537         val = s->intr;
 538         break;
 539     case 0x06:
 540         val = s->frnum;
 541         break;
 542     case 0x10 ... 0x1f:
 543         {
 544             UHCIPort *port;
 545             int n;
 546             n = (addr >> 1) & 7;
 547             if (n >= NB_PORTS)
 548                 goto read_default;
 549             port = &s->ports[n];
 550             val = port->ctrl;
 551         }
 552         break;
 553     default:
 554     read_default:
 555         val = 0xff7f; /* disabled port */
 556         break;
 557     }
 558
 559     trace_usb_uhci_mmio_readw(addr, val);
 560
 561     return val;
 562 }
 563
 564 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 565 {
 566     UHCIState *s = opaque;
 567
 568     addr &= 0x1f;
 569     trace_usb_uhci_mmio_writel(addr, val);
 570
 571     switch(addr) {
 572     case 0x08:
 573         s->fl_base_addr = val & ~0xfff;
 574         break;
 575     }
 576 }
 577
 578 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
 579 {
 580     UHCIState *s = opaque;
 581     uint32_t val;
 582
 583     addr &= 0x1f;
 584     switch(addr) {
 585     case 0x08:
 586         val = s->fl_base_addr;
 587         break;
 588     default:
 589         val = 0xffffffff;
 590         break;
 591     }
 592     trace_usb_uhci_mmio_readl(addr, val);
 593     return val;
 594 }
 595
 596 /* signal resume if controller suspended */
 597 static void uhci_resume (void *opaque)
 598 {
 599     UHCIState *s = (UHCIState *)opaque;
 600
 601     if (!s)
 602         return;
 603
 604     if (s->cmd & UHCI_CMD_EGSM) {
 605         s->cmd |= UHCI_CMD_FGR;
 606         s->status |= UHCI_STS_RD;
 607         uhci_update_irq(s);
 608     }
 609 }
 610
 611 static void uhci_attach(USBPort *port1)
 612 {
 613     UHCIState *s = port1->opaque;
 614     UHCIPort *port = &s->ports[port1->index];
 615
 616     /* set connect status */
 617     port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
 618
 619     /* update speed */
 620     if (port->port.dev->speed == USB_SPEED_LOW) {
 621         port->ctrl |= UHCI_PORT_LSDA;
 622     } else {
 623         port->ctrl &= ~UHCI_PORT_LSDA;
 624     }
 625
 626     uhci_resume(s);
 627 }
 628
 629 static void uhci_detach(USBPort *port1)
 630 {
 631     UHCIState *s = port1->opaque;
 632     UHCIPort *port = &s->ports[port1->index];
 633
 634     uhci_async_cancel_device(s, port1->dev);
 635
 636     /* set connect status */
 637     if (port->ctrl & UHCI_PORT_CCS) {
 638         port->ctrl &= ~UHCI_PORT_CCS;
 639         port->ctrl |= UHCI_PORT_CSC;
 640     }
 641     /* disable port */
 642     if (port->ctrl & UHCI_PORT_EN) {
 643         port->ctrl &= ~UHCI_PORT_EN;
 644         port->ctrl |= UHCI_PORT_ENC;
 645     }
 646
 647     uhci_resume(s);
 648 }
 649
 650 static void uhci_child_detach(USBPort *port1, USBDevice *child)
 651 {
 652     UHCIState *s = port1->opaque;
 653
 654     uhci_async_cancel_device(s, child);
 655 }
 656
 657 static void uhci_wakeup(USBPort *port1)
 658 {
 659     UHCIState *s = port1->opaque;
 660     UHCIPort *port = &s->ports[port1->index];
 661
 662     if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
 663         port->ctrl |= UHCI_PORT_RD;
 664         uhci_resume(s);
 665     }
 666 }
 667
 668 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
 669 {
 670     USBDevice *dev;
 671     int i;
 672
 673     for (i = 0; i < NB_PORTS; i++) {
 674         UHCIPort *port = &s->ports[i];
 675         if (!(port->ctrl & UHCI_PORT_EN)) {
 676             continue;
 677         }
 678         dev = usb_find_device(&port->port, addr);
 679         if (dev != NULL) {
 680             return dev;
 681         }
 682     }
 683     return NULL;
 684 }
 685
 686 static void uhci_async_complete(USBPort *port, USBPacket *packet);
 687 static void uhci_process_frame(UHCIState *s);
 688
 689 /* return -1 if fatal error (frame must be stopped)
 690           0 if TD successful
 691           1 if TD unsuccessful or inactive
 692 */
 693 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
 694 {
 695     int len = 0, max_len, err, ret;
 696     uint8_t pid;
 697
 698     max_len = ((td->token >> 21) + 1) & 0x7ff;
 699     pid = td->token & 0xff;
 700
 701     ret = async->packet.result;
 702
 703     if (td->ctrl & TD_CTRL_IOS)
 704         td->ctrl &= ~TD_CTRL_ACTIVE;
 705
 706     if (ret < 0)
 707         goto out;
 708
 709     len = async->packet.result;
 710     td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
 711
 712     /* The NAK bit may have been set by a previous frame, so clear it
 713        here.  The docs are somewhat unclear, but win2k relies on this
 714        behavior.  */
 715     td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
 716     if (td->ctrl & TD_CTRL_IOC)
 717         *int_mask |= 0x01;
 718
 719     if (pid == USB_TOKEN_IN) {
 720         if (len > max_len) {
 721             ret = USB_RET_BABBLE;
 722             goto out;
 723         }
 724
 725         if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
 726             *int_mask |= 0x02;
 727             /* short packet: do not update QH */
 728             trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
 729                                                     async->td);
 730             return TD_RESULT_NEXT_QH;
 731         }
 732     }
 733
 734     /* success */
 735     trace_usb_uhci_packet_complete_success(async->queue->token, async->td);
 736     return TD_RESULT_COMPLETE;
 737
 738 out:
 739     switch(ret) {
 740     case USB_RET_STALL:
 741         td->ctrl |= TD_CTRL_STALL;
 742         td->ctrl &= ~TD_CTRL_ACTIVE;
 743         s->status |= UHCI_STS_USBERR;
 744         if (td->ctrl & TD_CTRL_IOC) {
 745             *int_mask |= 0x01;
 746         }
 747         uhci_update_irq(s);
 748         trace_usb_uhci_packet_complete_stall(async->queue->token, async->td);
 749         return TD_RESULT_NEXT_QH;
 750
 751     case USB_RET_BABBLE:
 752         td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
 753         td->ctrl &= ~TD_CTRL_ACTIVE;
 754         s->status |= UHCI_STS_USBERR;
 755         if (td->ctrl & TD_CTRL_IOC) {
 756             *int_mask |= 0x01;
 757         }
 758         uhci_update_irq(s);
 759         /* frame interrupted */
 760         trace_usb_uhci_packet_complete_babble(async->queue->token, async->td);
 761         return TD_RESULT_STOP_FRAME;
 762
 763     case USB_RET_NAK:
 764         td->ctrl |= TD_CTRL_NAK;
 765         if (pid == USB_TOKEN_SETUP)
 766             break;
 767         return TD_RESULT_NEXT_QH;
 768
 769     case USB_RET_IOERROR:
 770     case USB_RET_NODEV:
 771     default:
 772         break;
 773     }
 774
 775     /* Retry the TD if error count is not zero */
 776
 777     td->ctrl |= TD_CTRL_TIMEOUT;
 778     err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
 779     if (err != 0) {
 780         err--;
 781         if (err == 0) {
 782             td->ctrl &= ~TD_CTRL_ACTIVE;
 783             s->status |= UHCI_STS_USBERR;
 784             if (td->ctrl & TD_CTRL_IOC)
 785                 *int_mask |= 0x01;
 786             uhci_update_irq(s);
 787             trace_usb_uhci_packet_complete_error(async->queue->token,
 788                                                  async->td);
 789         }
 790     }
 791     td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
 792         (err << TD_CTRL_ERROR_SHIFT);
 793     return TD_RESULT_NEXT_QH;
 794 }
 795
 796 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td,
 797                           uint32_t *int_mask, bool queuing)
 798 {
 799     UHCIAsync *async;
 800     int len = 0, max_len;
 801     uint8_t pid;
 802     USBDevice *dev;
 803     USBEndpoint *ep;
 804
 805     /* Is active ? */
 806     if (!(td->ctrl & TD_CTRL_ACTIVE))
 807         return TD_RESULT_NEXT_QH;
 808
 809     async = uhci_async_find_td(s, addr, td);
 810     if (async) {
 811         /* Already submitted */
 812         async->queue->valid = 32;
 813
 814         if (!async->done)
 815             return TD_RESULT_ASYNC_CONT;
 816         if (queuing) {
 817             /* we are busy filling the queue, we are not prepared
 818                to consume completed packages then, just leave them
 819                in async state */
 820             return TD_RESULT_ASYNC_CONT;
 821         }
 822
 823         uhci_async_unlink(async);
 824         goto done;
 825     }
 826
 827     /* Allocate new packet */
 828     async = uhci_async_alloc(uhci_queue_get(s, td), addr);
 829
 830     /* valid needs to be large enough to handle 10 frame delay
 831      * for initial isochronous requests
 832      */
 833     async->queue->valid = 32;
 834     async->isoc  = td->ctrl & TD_CTRL_IOS;
 835
 836     max_len = ((td->token >> 21) + 1) & 0x7ff;
 837     pid = td->token & 0xff;
 838
 839     dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
 840     ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
 841     usb_packet_setup(&async->packet, pid, ep);
 842     qemu_sglist_add(&async->sgl, td->buffer, max_len);
 843     usb_packet_map(&async->packet, &async->sgl);
 844
 845     switch(pid) {
 846     case USB_TOKEN_OUT:
 847     case USB_TOKEN_SETUP:
 848         len = usb_handle_packet(dev, &async->packet);
 849         if (len >= 0)
 850             len = max_len;
 851         break;
 852
 853     case USB_TOKEN_IN:
 854         len = usb_handle_packet(dev, &async->packet);
 855         break;
 856
 857     default:
 858         /* invalid pid : frame interrupted */
 859         uhci_async_free(async);
 860         s->status |= UHCI_STS_HCPERR;
 861         uhci_update_irq(s);
 862         return TD_RESULT_STOP_FRAME;
 863     }
 864
 865     if (len == USB_RET_ASYNC) {
 866         uhci_async_link(async);
 867         return TD_RESULT_ASYNC_START;
 868     }
 869
 870     async->packet.result = len;
 871
 872 done:
 873     len = uhci_complete_td(s, td, async, int_mask);
 874     usb_packet_unmap(&async->packet);
 875     uhci_async_free(async);
 876     return len;
 877 }
 878
 879 static void uhci_async_complete(USBPort *port, USBPacket *packet)
 880 {
 881     UHCIAsync *async = container_of(packet, UHCIAsync, packet);
 882     UHCIState *s = async->queue->uhci;
 883
 884     if (async->isoc) {
 885         UHCI_TD td;
 886         uint32_t link = async->td;
 887         uint32_t int_mask = 0, val;
 888
 889         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
 890         le32_to_cpus(&td.link);
 891         le32_to_cpus(&td.ctrl);
 892         le32_to_cpus(&td.token);
 893         le32_to_cpus(&td.buffer);
 894
 895         uhci_async_unlink(async);
 896         uhci_complete_td(s, &td, async, &int_mask);
 897         s->pending_int_mask |= int_mask;
 898
 899         /* update the status bits of the TD */
 900         val = cpu_to_le32(td.ctrl);
 901         pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
 902         uhci_async_free(async);
 903     } else {
 904         async->done = 1;
 905         if (s->frame_bytes < s->frame_bandwidth) {
 906             qemu_bh_schedule(s->bh);
 907         }
 908     }
 909 }
 910
 911 static int is_valid(uint32_t link)
 912 {
 913     return (link & 1) == 0;
 914 }
 915
 916 static int is_qh(uint32_t link)
 917 {
 918     return (link & 2) != 0;
 919 }
 920
 921 static int depth_first(uint32_t link)
 922 {
 923     return (link & 4) != 0;
 924 }
 925
 926 /* QH DB used for detecting QH loops */
 927 #define UHCI_MAX_QUEUES 128
 928 typedef struct {
 929     uint32_t addr[UHCI_MAX_QUEUES];
 930     int      count;
 931 } QhDb;
 932
 933 static void qhdb_reset(QhDb *db)
 934 {
 935     db->count = 0;
 936 }
 937
 938 /* Add QH to DB. Returns 1 if already present or DB is full. */
 939 static int qhdb_insert(QhDb *db, uint32_t addr)
 940 {
 941     int i;
 942     for (i = 0; i < db->count; i++)
 943         if (db->addr[i] == addr)
 944             return 1;
 945
 946     if (db->count >= UHCI_MAX_QUEUES)
 947         return 1;
 948
 949     db->addr[db->count++] = addr;
 950     return 0;
 951 }
 952
 953 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td)
 954 {
 955     uint32_t int_mask = 0;
 956     uint32_t plink = td->link;
 957     uint32_t token = uhci_queue_token(td);
 958     UHCI_TD ptd;
 959     int ret;
 960
 961     while (is_valid(plink)) {
 962         pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd));
 963         le32_to_cpus(&ptd.link);
 964         le32_to_cpus(&ptd.ctrl);
 965         le32_to_cpus(&ptd.token);
 966         le32_to_cpus(&ptd.buffer);
 967         if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
 968             break;
 969         }
 970         if (uhci_queue_token(&ptd) != token) {
 971             break;
 972         }
 973         trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
 974         ret = uhci_handle_td(s, plink, &ptd, &int_mask, true);
 975         if (ret == TD_RESULT_ASYNC_CONT) {
 976             break;
 977         }
 978         assert(ret == TD_RESULT_ASYNC_START);
 979         assert(int_mask == 0);
 980         plink = ptd.link;
 981     }
 982 }
 983
 984 static void uhci_process_frame(UHCIState *s)
 985 {
 986     uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
 987     uint32_t curr_qh, td_count = 0;
 988     int cnt, ret;
 989     UHCI_TD td;
 990     UHCI_QH qh;
 991     QhDb qhdb;
 992
 993     frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
 994
 995     pci_dma_read(&s->dev, frame_addr, &link, 4);
 996     le32_to_cpus(&link);
 997
 998     int_mask = 0;
 999     curr_qh  = 0;
1000
1001     qhdb_reset(&qhdb);
1002
1003     for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1004         if (s->frame_bytes >= s->frame_bandwidth) {
1005             /* We've reached the usb 1.1 bandwidth, which is
1006                1280 bytes/frame, stop processing */
1007             trace_usb_uhci_frame_stop_bandwidth();
1008             break;
1009         }
1010         if (is_qh(link)) {
1011             /* QH */
1012             trace_usb_uhci_qh_load(link & ~0xf);
1013
1014             if (qhdb_insert(&qhdb, link)) {
1015                 /*
1016                  * We're going in circles. Which is not a bug because
1017                  * HCD is allowed to do that as part of the BW management.
1018                  *
1019                  * Stop processing here if no transaction has been done
1020                  * since we've been here last time.
1021                  */
1022                 if (td_count == 0) {
1023                     trace_usb_uhci_frame_loop_stop_idle();
1024                     break;
1025                 } else {
1026                     trace_usb_uhci_frame_loop_continue();
1027                     td_count = 0;
1028                     qhdb_reset(&qhdb);
1029                     qhdb_insert(&qhdb, link);
1030                 }
1031             }
1032
1033             pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1034             le32_to_cpus(&qh.link);
1035             le32_to_cpus(&qh.el_link);
1036
1037             if (!is_valid(qh.el_link)) {
1038                 /* QH w/o elements */
1039                 curr_qh = 0;
1040                 link = qh.link;
1041             } else {
1042                 /* QH with elements */
1043                 curr_qh = link;
1044                 link = qh.el_link;
1045             }
1046             continue;
1047         }
1048
1049         /* TD */
1050         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
1051         le32_to_cpus(&td.link);
1052         le32_to_cpus(&td.ctrl);
1053         le32_to_cpus(&td.token);
1054         le32_to_cpus(&td.buffer);
1055         trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1056
1057         old_td_ctrl = td.ctrl;
1058         ret = uhci_handle_td(s, link, &td, &int_mask, false);
1059         if (old_td_ctrl != td.ctrl) {
1060             /* update the status bits of the TD */
1061             val = cpu_to_le32(td.ctrl);
1062             pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1063         }
1064
1065         switch (ret) {
1066         case TD_RESULT_STOP_FRAME: /* interrupted frame */
1067             goto out;
1068
1069         case TD_RESULT_NEXT_QH:
1070         case TD_RESULT_ASYNC_CONT:
1071             trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1072             link = curr_qh ? qh.link : td.link;
1073             continue;
1074
1075         case TD_RESULT_ASYNC_START:
1076             trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1077             if (is_valid(td.link)) {
1078                 uhci_fill_queue(s, &td);
1079             }
1080             link = curr_qh ? qh.link : td.link;
1081             continue;
1082
1083         case TD_RESULT_COMPLETE:
1084             trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1085             link = td.link;
1086             td_count++;
1087             s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1088
1089             if (curr_qh) {
1090                 /* update QH element link */
1091                 qh.el_link = link;
1092                 val = cpu_to_le32(qh.el_link);
1093                 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1094
1095                 if (!depth_first(link)) {
1096                     /* done with this QH */
1097                     curr_qh = 0;
1098                     link    = qh.link;
1099                 }
1100             }
1101             break;
1102
1103         default:
1104             assert(!"unknown return code");
1105         }
1106
1107         /* go to the next entry */
1108     }
1109
1110 out:
1111     s->pending_int_mask |= int_mask;
1112 }
1113
1114 static void uhci_bh(void *opaque)
1115 {
1116     UHCIState *s = opaque;
1117     uhci_process_frame(s);
1118 }
1119
1120 static void uhci_frame_timer(void *opaque)
1121 {
1122     UHCIState *s = opaque;
1123
1124     /* prepare the timer for the next frame */
1125     s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1126     s->frame_bytes = 0;
1127     qemu_bh_cancel(s->bh);
1128
1129     if (!(s->cmd & UHCI_CMD_RS)) {
1130         /* Full stop */
1131         trace_usb_uhci_schedule_stop();
1132         qemu_del_timer(s->frame_timer);
1133         uhci_async_cancel_all(s);
1134         /* set hchalted bit in status - UHCI11D 2.1.2 */
1135         s->status |= UHCI_STS_HCHALTED;
1136         return;
1137     }
1138
1139     /* Complete the previous frame */
1140     if (s->pending_int_mask) {
1141         s->status2 |= s->pending_int_mask;
1142         s->status  |= UHCI_STS_USBINT;
1143         uhci_update_irq(s);
1144     }
1145     s->pending_int_mask = 0;
1146
1147     /* Start new frame */
1148     s->frnum = (s->frnum + 1) & 0x7ff;
1149
1150     trace_usb_uhci_frame_start(s->frnum);
1151
1152     uhci_async_validate_begin(s);
1153
1154     uhci_process_frame(s);
1155
1156     uhci_async_validate_end(s);
1157
1158     qemu_mod_timer(s->frame_timer, s->expire_time);
1159 }
1160
1161 static const MemoryRegionPortio uhci_portio[] = {
1162     { 0, 32, 2, .write = uhci_ioport_writew, },
1163     { 0, 32, 2, .read = uhci_ioport_readw, },
1164     { 0, 32, 4, .write = uhci_ioport_writel, },
1165     { 0, 32, 4, .read = uhci_ioport_readl, },
1166     { 0, 32, 1, .write = uhci_ioport_writeb, },
1167     { 0, 32, 1, .read = uhci_ioport_readb, },
1168     PORTIO_END_OF_LIST()
1169 };
1170
1171 static const MemoryRegionOps uhci_ioport_ops = {
1172     .old_portio = uhci_portio,
1173 };
1174
1175 static USBPortOps uhci_port_ops = {
1176     .attach = uhci_attach,
1177     .detach = uhci_detach,
1178     .child_detach = uhci_child_detach,
1179     .wakeup = uhci_wakeup,
1180     .complete = uhci_async_complete,
1181 };
1182
1183 static USBBusOps uhci_bus_ops = {
1184 };
1185
1186 static int usb_uhci_common_initfn(PCIDevice *dev)
1187 {
1188     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1189     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1190     uint8_t *pci_conf = s->dev.config;
1191     int i;
1192
1193     pci_conf[PCI_CLASS_PROG] = 0x00;
1194     /* TODO: reset value should be 0. */
1195     pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1196
1197     switch (pc->device_id) {
1198     case PCI_DEVICE_ID_INTEL_82801I_UHCI1:
1199         s->irq_pin = 0;  /* A */
1200         break;
1201     case PCI_DEVICE_ID_INTEL_82801I_UHCI2:
1202         s->irq_pin = 1;  /* B */
1203         break;
1204     case PCI_DEVICE_ID_INTEL_82801I_UHCI3:
1205         s->irq_pin = 2;  /* C */
1206         break;
1207     default:
1208         s->irq_pin = 3;  /* D */
1209         break;
1210     }
1211     pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1);
1212
1213     if (s->masterbus) {
1214         USBPort *ports[NB_PORTS];
1215         for(i = 0; i < NB_PORTS; i++) {
1216             ports[i] = &s->ports[i].port;
1217         }
1218         if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1219                 s->firstport, s, &uhci_port_ops,
1220                 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1221             return -1;
1222         }
1223     } else {
1224         usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1225         for (i = 0; i < NB_PORTS; i++) {
1226             usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1227                               USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1228         }
1229     }
1230     s->bh = qemu_bh_new(uhci_bh, s);
1231     s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1232     s->num_ports_vmstate = NB_PORTS;
1233     QTAILQ_INIT(&s->queues);
1234
1235     qemu_register_reset(uhci_reset, s);
1236
1237     memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1238     /* Use region 4 for consistency with real hardware.  BSD guests seem
1239        to rely on this.  */
1240     pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1241
1242     return 0;
1243 }
1244
1245 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1246 {
1247     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1248     uint8_t *pci_conf = s->dev.config;
1249
1250     /* USB misc control 1/2 */
1251     pci_set_long(pci_conf + 0x40,0x00001000);
1252     /* PM capability */
1253     pci_set_long(pci_conf + 0x80,0x00020001);
1254     /* USB legacy support  */
1255     pci_set_long(pci_conf + 0xc0,0x00002000);
1256
1257     return usb_uhci_common_initfn(dev);
1258 }
1259
1260 static int usb_uhci_exit(PCIDevice *dev)
1261 {
1262     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1263
1264     memory_region_destroy(&s->io_bar);
1265     return 0;
1266 }
1267
1268 static Property uhci_properties[] = {
1269     DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1270     DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1271     DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1272     DEFINE_PROP_END_OF_LIST(),
1273 };
1274
1275 static void piix3_uhci_class_init(ObjectClass *klass, void *data)
1276 {
1277     DeviceClass *dc = DEVICE_CLASS(klass);
1278     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1279
1280     k->init = usb_uhci_common_initfn;
1281     k->exit = usb_uhci_exit;
1282     k->vendor_id = PCI_VENDOR_ID_INTEL;
1283     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
1284     k->revision = 0x01;
1285     k->class_id = PCI_CLASS_SERIAL_USB;
1286     dc->vmsd = &vmstate_uhci;
1287     dc->props = uhci_properties;
1288 }
1289
1290 static TypeInfo piix3_uhci_info = {
1291     .name          = "piix3-usb-uhci",
1292     .parent        = TYPE_PCI_DEVICE,
1293     .instance_size = sizeof(UHCIState),
1294     .class_init    = piix3_uhci_class_init,
1295 };
1296
1297 static void piix4_uhci_class_init(ObjectClass *klass, void *data)
1298 {
1299     DeviceClass *dc = DEVICE_CLASS(klass);
1300     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1301
1302     k->init = usb_uhci_common_initfn;
1303     k->exit = usb_uhci_exit;
1304     k->vendor_id = PCI_VENDOR_ID_INTEL;
1305     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
1306     k->revision = 0x01;
1307     k->class_id = PCI_CLASS_SERIAL_USB;
1308     dc->vmsd = &vmstate_uhci;
1309     dc->props = uhci_properties;
1310 }
1311
1312 static TypeInfo piix4_uhci_info = {
1313     .name          = "piix4-usb-uhci",
1314     .parent        = TYPE_PCI_DEVICE,
1315     .instance_size = sizeof(UHCIState),
1316     .class_init    = piix4_uhci_class_init,
1317 };
1318
1319 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data)
1320 {
1321     DeviceClass *dc = DEVICE_CLASS(klass);
1322     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1323
1324     k->init = usb_uhci_vt82c686b_initfn;
1325     k->exit = usb_uhci_exit;
1326     k->vendor_id = PCI_VENDOR_ID_VIA;
1327     k->device_id = PCI_DEVICE_ID_VIA_UHCI;
1328     k->revision = 0x01;
1329     k->class_id = PCI_CLASS_SERIAL_USB;
1330     dc->vmsd = &vmstate_uhci;
1331     dc->props = uhci_properties;
1332 }
1333
1334 static TypeInfo vt82c686b_uhci_info = {
1335     .name          = "vt82c686b-usb-uhci",
1336     .parent        = TYPE_PCI_DEVICE,
1337     .instance_size = sizeof(UHCIState),
1338     .class_init    = vt82c686b_uhci_class_init,
1339 };
1340
1341 static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
1342 {
1343     DeviceClass *dc = DEVICE_CLASS(klass);
1344     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1345
1346     k->init = usb_uhci_common_initfn;
1347     k->vendor_id = PCI_VENDOR_ID_INTEL;
1348     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
1349     k->revision = 0x03;
1350     k->class_id = PCI_CLASS_SERIAL_USB;
1351     dc->vmsd = &vmstate_uhci;
1352     dc->props = uhci_properties;
1353 }
1354
1355 static TypeInfo ich9_uhci1_info = {
1356     .name          = "ich9-usb-uhci1",
1357     .parent        = TYPE_PCI_DEVICE,
1358     .instance_size = sizeof(UHCIState),
1359     .class_init    = ich9_uhci1_class_init,
1360 };
1361
1362 static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
1363 {
1364     DeviceClass *dc = DEVICE_CLASS(klass);
1365     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1366
1367     k->init = usb_uhci_common_initfn;
1368     k->vendor_id = PCI_VENDOR_ID_INTEL;
1369     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
1370     k->revision = 0x03;
1371     k->class_id = PCI_CLASS_SERIAL_USB;
1372     dc->vmsd = &vmstate_uhci;
1373     dc->props = uhci_properties;
1374 }
1375
1376 static TypeInfo ich9_uhci2_info = {
1377     .name          = "ich9-usb-uhci2",
1378     .parent        = TYPE_PCI_DEVICE,
1379     .instance_size = sizeof(UHCIState),
1380     .class_init    = ich9_uhci2_class_init,
1381 };
1382
1383 static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
1384 {
1385     DeviceClass *dc = DEVICE_CLASS(klass);
1386     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1387
1388     k->init = usb_uhci_common_initfn;
1389     k->vendor_id = PCI_VENDOR_ID_INTEL;
1390     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
1391     k->revision = 0x03;
1392     k->class_id = PCI_CLASS_SERIAL_USB;
1393     dc->vmsd = &vmstate_uhci;
1394     dc->props = uhci_properties;
1395 }
1396
1397 static TypeInfo ich9_uhci3_info = {
1398     .name          = "ich9-usb-uhci3",
1399     .parent        = TYPE_PCI_DEVICE,
1400     .instance_size = sizeof(UHCIState),
1401     .class_init    = ich9_uhci3_class_init,
1402 };
1403
1404 static void uhci_register_types(void)
1405 {
1406     type_register_static(&piix3_uhci_info);
1407     type_register_static(&piix4_uhci_info);
1408     type_register_static(&vt82c686b_uhci_info);
1409     type_register_static(&ich9_uhci1_info);
1410     type_register_static(&ich9_uhci2_info);
1411     type_register_static(&ich9_uhci3_info);
1412 }
1413
1414 type_init(uhci_register_types)