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target-arm/neon_helper: Remove obsolete FIXME comment
[qemu/pbrook.git] / hw / pci.c
blob2ca6ff6fecd43643d56fb1c0c11df469d791a580
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "range.h"
33 #include "qmp-commands.h"
34 #include "msi.h"
35 #include "msix.h"
36
37 //#define DEBUG_PCI
38 #ifdef DEBUG_PCI
39 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
40 #else
41 # define PCI_DPRINTF(format, ...) do { } while (0)
42 #endif
43
44 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
45 static char *pcibus_get_dev_path(DeviceState *dev);
46 static char *pcibus_get_fw_dev_path(DeviceState *dev);
47 static int pcibus_reset(BusState *qbus);
48
49 static Property pci_props[] = {
50 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
51 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
52 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
53 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
54 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
55 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
56 QEMU_PCI_CAP_SERR_BITNR, true),
57 DEFINE_PROP_END_OF_LIST()
58 };
59
60 static void pci_bus_class_init(ObjectClass *klass, void *data)
61 {
62 BusClass *k = BUS_CLASS(klass);
63
64 k->print_dev = pcibus_dev_print;
65 k->get_dev_path = pcibus_get_dev_path;
66 k->get_fw_dev_path = pcibus_get_fw_dev_path;
67 k->reset = pcibus_reset;
68 }
69
70 static const TypeInfo pci_bus_info = {
71 .name = TYPE_PCI_BUS,
72 .parent = TYPE_BUS,
73 .instance_size = sizeof(PCIBus),
74 .class_init = pci_bus_class_init,
75 };
76
77 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
78 static void pci_update_mappings(PCIDevice *d);
79 static void pci_set_irq(void *opaque, int irq_num, int level);
80 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
81 static void pci_del_option_rom(PCIDevice *pdev);
82
83 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
84 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
85
86 struct PCIHostBus {
87 int domain;
88 struct PCIBus *bus;
89 QLIST_ENTRY(PCIHostBus) next;
90 };
91 static QLIST_HEAD(, PCIHostBus) host_buses;
92
93 static const VMStateDescription vmstate_pcibus = {
94 .name = "PCIBUS",
95 .version_id = 1,
96 .minimum_version_id = 1,
97 .minimum_version_id_old = 1,
98 .fields = (VMStateField []) {
99 VMSTATE_INT32_EQUAL(nirq, PCIBus),
100 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
101 VMSTATE_END_OF_LIST()
102 }
103 };
104 static int pci_bar(PCIDevice *d, int reg)
105 {
106 uint8_t type;
107
108 if (reg != PCI_ROM_SLOT)
109 return PCI_BASE_ADDRESS_0 + reg * 4;
110
111 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
112 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
113 }
114
115 static inline int pci_irq_state(PCIDevice *d, int irq_num)
116 {
117 return (d->irq_state >> irq_num) & 0x1;
118 }
119
120 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
121 {
122 d->irq_state &= ~(0x1 << irq_num);
123 d->irq_state |= level << irq_num;
124 }
125
126 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
127 {
128 PCIBus *bus;
129 for (;;) {
130 bus = pci_dev->bus;
131 irq_num = bus->map_irq(pci_dev, irq_num);
132 if (bus->set_irq)
133 break;
134 pci_dev = bus->parent_dev;
135 }
136 bus->irq_count[irq_num] += change;
137 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
138 }
139
140 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
141 {
142 assert(irq_num >= 0);
143 assert(irq_num < bus->nirq);
144 return !!bus->irq_count[irq_num];
145 }
146
147 /* Update interrupt status bit in config space on interrupt
148 * state change. */
149 static void pci_update_irq_status(PCIDevice *dev)
150 {
151 if (dev->irq_state) {
152 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
153 } else {
154 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
155 }
156 }
157
158 void pci_device_deassert_intx(PCIDevice *dev)
159 {
160 int i;
161 for (i = 0; i < PCI_NUM_PINS; ++i) {
162 qemu_set_irq(dev->irq[i], 0);
163 }
164 }
165
166 /*
167 * This function is called on #RST and FLR.
168 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
169 */
170 void pci_device_reset(PCIDevice *dev)
171 {
172 int r;
173
174 qdev_reset_all(&dev->qdev);
175
176 dev->irq_state = 0;
177 pci_update_irq_status(dev);
178 pci_device_deassert_intx(dev);
179 /* Clear all writable bits */
180 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
181 pci_get_word(dev->wmask + PCI_COMMAND) |
182 pci_get_word(dev->w1cmask + PCI_COMMAND));
183 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
184 pci_get_word(dev->wmask + PCI_STATUS) |
185 pci_get_word(dev->w1cmask + PCI_STATUS));
186 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
187 dev->config[PCI_INTERRUPT_LINE] = 0x0;
188 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
189 PCIIORegion *region = &dev->io_regions[r];
190 if (!region->size) {
191 continue;
192 }
193
194 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
195 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
196 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
197 } else {
198 pci_set_long(dev->config + pci_bar(dev, r), region->type);
199 }
200 }
201 pci_update_mappings(dev);
202
203 msi_reset(dev);
204 msix_reset(dev);
205 }
206
207 /*
208 * Trigger pci bus reset under a given bus.
209 * To be called on RST# assert.
210 */
211 void pci_bus_reset(PCIBus *bus)
212 {
213 int i;
214
215 for (i = 0; i < bus->nirq; i++) {
216 bus->irq_count[i] = 0;
217 }
218 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
219 if (bus->devices[i]) {
220 pci_device_reset(bus->devices[i]);
221 }
222 }
223 }
224
225 static int pcibus_reset(BusState *qbus)
226 {
227 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
228
229 /* topology traverse is done by pci_bus_reset().
230 Tell qbus/qdev walker not to traverse the tree */
231 return 1;
232 }
233
234 static void pci_host_bus_register(int domain, PCIBus *bus)
235 {
236 struct PCIHostBus *host;
237 host = g_malloc0(sizeof(*host));
238 host->domain = domain;
239 host->bus = bus;
240 QLIST_INSERT_HEAD(&host_buses, host, next);
241 }
242
243 PCIBus *pci_find_root_bus(int domain)
244 {
245 struct PCIHostBus *host;
246
247 QLIST_FOREACH(host, &host_buses, next) {
248 if (host->domain == domain) {
249 return host->bus;
250 }
251 }
252
253 return NULL;
254 }
255
256 int pci_find_domain(const PCIBus *bus)
257 {
258 PCIDevice *d;
259 struct PCIHostBus *host;
260
261 /* obtain root bus */
262 while ((d = bus->parent_dev) != NULL) {
263 bus = d->bus;
264 }
265
266 QLIST_FOREACH(host, &host_buses, next) {
267 if (host->bus == bus) {
268 return host->domain;
269 }
270 }
271
272 abort(); /* should not be reached */
273 return -1;
274 }
275
276 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
277 const char *name,
278 MemoryRegion *address_space_mem,
279 MemoryRegion *address_space_io,
280 uint8_t devfn_min)
281 {
282 qbus_create_inplace(&bus->qbus, TYPE_PCI_BUS, parent, name);
283 assert(PCI_FUNC(devfn_min) == 0);
284 bus->devfn_min = devfn_min;
285 bus->address_space_mem = address_space_mem;
286 bus->address_space_io = address_space_io;
287
288 /* host bridge */
289 QLIST_INIT(&bus->child);
290 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
291
292 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
293 }
294
295 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
296 MemoryRegion *address_space_mem,
297 MemoryRegion *address_space_io,
298 uint8_t devfn_min)
299 {
300 PCIBus *bus;
301
302 bus = g_malloc0(sizeof(*bus));
303 bus->qbus.glib_allocated = true;
304 pci_bus_new_inplace(bus, parent, name, address_space_mem,
305 address_space_io, devfn_min);
306 return bus;
307 }
308
309 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
310 void *irq_opaque, int nirq)
311 {
312 bus->set_irq = set_irq;
313 bus->map_irq = map_irq;
314 bus->irq_opaque = irq_opaque;
315 bus->nirq = nirq;
316 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
317 }
318
319 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
320 {
321 bus->qbus.allow_hotplug = 1;
322 bus->hotplug = hotplug;
323 bus->hotplug_qdev = qdev;
324 }
325
326 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
327 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
328 void *irq_opaque,
329 MemoryRegion *address_space_mem,
330 MemoryRegion *address_space_io,
331 uint8_t devfn_min, int nirq)
332 {
333 PCIBus *bus;
334
335 bus = pci_bus_new(parent, name, address_space_mem,
336 address_space_io, devfn_min);
337 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
338 return bus;
339 }
340
341 int pci_bus_num(PCIBus *s)
342 {
343 if (!s->parent_dev)
344 return 0; /* pci host bridge */
345 return s->parent_dev->config[PCI_SECONDARY_BUS];
346 }
347
348 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
349 {
350 PCIDevice *s = container_of(pv, PCIDevice, config);
351 uint8_t *config;
352 int i;
353
354 assert(size == pci_config_size(s));
355 config = g_malloc(size);
356
357 qemu_get_buffer(f, config, size);
358 for (i = 0; i < size; ++i) {
359 if ((config[i] ^ s->config[i]) &
360 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
361 g_free(config);
362 return -EINVAL;
363 }
364 }
365 memcpy(s->config, config, size);
366
367 pci_update_mappings(s);
368
369 g_free(config);
370 return 0;
371 }
372
373 /* just put buffer */
374 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
375 {
376 const uint8_t **v = pv;
377 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
378 qemu_put_buffer(f, *v, size);
379 }
380
381 static VMStateInfo vmstate_info_pci_config = {
382 .name = "pci config",
383 .get = get_pci_config_device,
384 .put = put_pci_config_device,
385 };
386
387 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
388 {
389 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
390 uint32_t irq_state[PCI_NUM_PINS];
391 int i;
392 for (i = 0; i < PCI_NUM_PINS; ++i) {
393 irq_state[i] = qemu_get_be32(f);
394 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
395 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
396 irq_state[i]);
397 return -EINVAL;
398 }
399 }
400
401 for (i = 0; i < PCI_NUM_PINS; ++i) {
402 pci_set_irq_state(s, i, irq_state[i]);
403 }
404
405 return 0;
406 }
407
408 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
409 {
410 int i;
411 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
412
413 for (i = 0; i < PCI_NUM_PINS; ++i) {
414 qemu_put_be32(f, pci_irq_state(s, i));
415 }
416 }
417
418 static VMStateInfo vmstate_info_pci_irq_state = {
419 .name = "pci irq state",
420 .get = get_pci_irq_state,
421 .put = put_pci_irq_state,
422 };
423
424 const VMStateDescription vmstate_pci_device = {
425 .name = "PCIDevice",
426 .version_id = 2,
427 .minimum_version_id = 1,
428 .minimum_version_id_old = 1,
429 .fields = (VMStateField []) {
430 VMSTATE_INT32_LE(version_id, PCIDevice),
431 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
432 vmstate_info_pci_config,
433 PCI_CONFIG_SPACE_SIZE),
434 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
435 vmstate_info_pci_irq_state,
436 PCI_NUM_PINS * sizeof(int32_t)),
437 VMSTATE_END_OF_LIST()
438 }
439 };
440
441 const VMStateDescription vmstate_pcie_device = {
442 .name = "PCIEDevice",
443 .version_id = 2,
444 .minimum_version_id = 1,
445 .minimum_version_id_old = 1,
446 .fields = (VMStateField []) {
447 VMSTATE_INT32_LE(version_id, PCIDevice),
448 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
449 vmstate_info_pci_config,
450 PCIE_CONFIG_SPACE_SIZE),
451 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
452 vmstate_info_pci_irq_state,
453 PCI_NUM_PINS * sizeof(int32_t)),
454 VMSTATE_END_OF_LIST()
455 }
456 };
457
458 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
459 {
460 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
461 }
462
463 void pci_device_save(PCIDevice *s, QEMUFile *f)
464 {
465 /* Clear interrupt status bit: it is implicit
466 * in irq_state which we are saving.
467 * This makes us compatible with old devices
468 * which never set or clear this bit. */
469 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
470 vmstate_save_state(f, pci_get_vmstate(s), s);
471 /* Restore the interrupt status bit. */
472 pci_update_irq_status(s);
473 }
474
475 int pci_device_load(PCIDevice *s, QEMUFile *f)
476 {
477 int ret;
478 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
479 /* Restore the interrupt status bit. */
480 pci_update_irq_status(s);
481 return ret;
482 }
483
484 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
485 {
486 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
487 pci_default_sub_vendor_id);
488 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
489 pci_default_sub_device_id);
490 }
491
492 /*
493 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
494 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
495 */
496 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
497 unsigned int *slotp, unsigned int *funcp)
498 {
499 const char *p;
500 char *e;
501 unsigned long val;
502 unsigned long dom = 0, bus = 0;
503 unsigned int slot = 0;
504 unsigned int func = 0;
505
506 p = addr;
507 val = strtoul(p, &e, 16);
508 if (e == p)
509 return -1;
510 if (*e == ':') {
511 bus = val;
512 p = e + 1;
513 val = strtoul(p, &e, 16);
514 if (e == p)
515 return -1;
516 if (*e == ':') {
517 dom = bus;
518 bus = val;
519 p = e + 1;
520 val = strtoul(p, &e, 16);
521 if (e == p)
522 return -1;
523 }
524 }
525
526 slot = val;
527
528 if (funcp != NULL) {
529 if (*e != '.')
530 return -1;
531
532 p = e + 1;
533 val = strtoul(p, &e, 16);
534 if (e == p)
535 return -1;
536
537 func = val;
538 }
539
540 /* if funcp == NULL func is 0 */
541 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
542 return -1;
543
544 if (*e)
545 return -1;
546
547 *domp = dom;
548 *busp = bus;
549 *slotp = slot;
550 if (funcp != NULL)
551 *funcp = func;
552 return 0;
553 }
554
555 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
556 unsigned *slotp)
557 {
558 /* strip legacy tag */
559 if (!strncmp(addr, "pci_addr=", 9)) {
560 addr += 9;
561 }
562 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
563 monitor_printf(mon, "Invalid pci address\n");
564 return -1;
565 }
566 return 0;
567 }
568
569 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
570 {
571 int dom, bus;
572 unsigned slot;
573
574 if (!devaddr) {
575 *devfnp = -1;
576 return pci_find_bus_nr(pci_find_root_bus(0), 0);
577 }
578
579 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
580 return NULL;
581 }
582
583 *devfnp = PCI_DEVFN(slot, 0);
584 return pci_find_bus_nr(pci_find_root_bus(dom), bus);
585 }
586
587 static void pci_init_cmask(PCIDevice *dev)
588 {
589 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
590 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
591 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
592 dev->cmask[PCI_REVISION_ID] = 0xff;
593 dev->cmask[PCI_CLASS_PROG] = 0xff;
594 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
595 dev->cmask[PCI_HEADER_TYPE] = 0xff;
596 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
597 }
598
599 static void pci_init_wmask(PCIDevice *dev)
600 {
601 int config_size = pci_config_size(dev);
602
603 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
604 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
605 pci_set_word(dev->wmask + PCI_COMMAND,
606 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
607 PCI_COMMAND_INTX_DISABLE);
608 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
609 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
610 }
611
612 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
613 config_size - PCI_CONFIG_HEADER_SIZE);
614 }
615
616 static void pci_init_w1cmask(PCIDevice *dev)
617 {
618 /*
619 * Note: It's okay to set w1cmask even for readonly bits as
620 * long as their value is hardwired to 0.
621 */
622 pci_set_word(dev->w1cmask + PCI_STATUS,
623 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
624 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
625 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
626 }
627
628 static void pci_init_mask_bridge(PCIDevice *d)
629 {
630 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
631 PCI_SEC_LETENCY_TIMER */
632 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
633
634 /* base and limit */
635 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
636 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
637 pci_set_word(d->wmask + PCI_MEMORY_BASE,
638 PCI_MEMORY_RANGE_MASK & 0xffff);
639 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
640 PCI_MEMORY_RANGE_MASK & 0xffff);
641 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
642 PCI_PREF_RANGE_MASK & 0xffff);
643 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
644 PCI_PREF_RANGE_MASK & 0xffff);
645
646 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
647 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
648
649 /* Supported memory and i/o types */
650 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
651 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
652 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
653 PCI_PREF_RANGE_TYPE_64);
654 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
655 PCI_PREF_RANGE_TYPE_64);
656
657 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
658 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
659 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
660 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
661 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
662 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
663 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
664 PCI_BRIDGE_CTL_PARITY |
665 PCI_BRIDGE_CTL_SERR |
666 PCI_BRIDGE_CTL_ISA |
667 PCI_BRIDGE_CTL_VGA |
668 PCI_BRIDGE_CTL_VGA_16BIT |
669 PCI_BRIDGE_CTL_MASTER_ABORT |
670 PCI_BRIDGE_CTL_BUS_RESET |
671 PCI_BRIDGE_CTL_FAST_BACK |
672 PCI_BRIDGE_CTL_DISCARD |
673 PCI_BRIDGE_CTL_SEC_DISCARD |
674 PCI_BRIDGE_CTL_DISCARD_SERR);
675 /* Below does not do anything as we never set this bit, put here for
676 * completeness. */
677 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
678 PCI_BRIDGE_CTL_DISCARD_STATUS);
679 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
680 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
681 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
682 PCI_PREF_RANGE_TYPE_MASK);
683 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
684 PCI_PREF_RANGE_TYPE_MASK);
685 }
686
687 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
688 {
689 uint8_t slot = PCI_SLOT(dev->devfn);
690 uint8_t func;
691
692 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
693 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
694 }
695
696 /*
697 * multifunction bit is interpreted in two ways as follows.
698 * - all functions must set the bit to 1.
699 * Example: Intel X53
700 * - function 0 must set the bit, but the rest function (> 0)
701 * is allowed to leave the bit to 0.
702 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
703 *
704 * So OS (at least Linux) checks the bit of only function 0,
705 * and doesn't see the bit of function > 0.
706 *
707 * The below check allows both interpretation.
708 */
709 if (PCI_FUNC(dev->devfn)) {
710 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
711 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
712 /* function 0 should set multifunction bit */
713 error_report("PCI: single function device can't be populated "
714 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
715 return -1;
716 }
717 return 0;
718 }
719
720 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
721 return 0;
722 }
723 /* function 0 indicates single function, so function > 0 must be NULL */
724 for (func = 1; func < PCI_FUNC_MAX; ++func) {
725 if (bus->devices[PCI_DEVFN(slot, func)]) {
726 error_report("PCI: %x.0 indicates single function, "
727 "but %x.%x is already populated.",
728 slot, slot, func);
729 return -1;
730 }
731 }
732 return 0;
733 }
734
735 static void pci_config_alloc(PCIDevice *pci_dev)
736 {
737 int config_size = pci_config_size(pci_dev);
738
739 pci_dev->config = g_malloc0(config_size);
740 pci_dev->cmask = g_malloc0(config_size);
741 pci_dev->wmask = g_malloc0(config_size);
742 pci_dev->w1cmask = g_malloc0(config_size);
743 pci_dev->used = g_malloc0(config_size);
744 }
745
746 static void pci_config_free(PCIDevice *pci_dev)
747 {
748 g_free(pci_dev->config);
749 g_free(pci_dev->cmask);
750 g_free(pci_dev->wmask);
751 g_free(pci_dev->w1cmask);
752 g_free(pci_dev->used);
753 }
754
755 /* -1 for devfn means auto assign */
756 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
757 const char *name, int devfn)
758 {
759 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
760 PCIConfigReadFunc *config_read = pc->config_read;
761 PCIConfigWriteFunc *config_write = pc->config_write;
762
763 if (devfn < 0) {
764 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
765 devfn += PCI_FUNC_MAX) {
766 if (!bus->devices[devfn])
767 goto found;
768 }
769 error_report("PCI: no slot/function available for %s, all in use", name);
770 return NULL;
771 found: ;
772 } else if (bus->devices[devfn]) {
773 error_report("PCI: slot %d function %d not available for %s, in use by %s",
774 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
775 return NULL;
776 }
777 pci_dev->bus = bus;
778 if (bus->dma_context_fn) {
779 pci_dev->dma = bus->dma_context_fn(bus, bus->dma_context_opaque, devfn);
780 }
781 pci_dev->devfn = devfn;
782 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
783 pci_dev->irq_state = 0;
784 pci_config_alloc(pci_dev);
785
786 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
787 pci_config_set_device_id(pci_dev->config, pc->device_id);
788 pci_config_set_revision(pci_dev->config, pc->revision);
789 pci_config_set_class(pci_dev->config, pc->class_id);
790
791 if (!pc->is_bridge) {
792 if (pc->subsystem_vendor_id || pc->subsystem_id) {
793 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
794 pc->subsystem_vendor_id);
795 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
796 pc->subsystem_id);
797 } else {
798 pci_set_default_subsystem_id(pci_dev);
799 }
800 } else {
801 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
802 assert(!pc->subsystem_vendor_id);
803 assert(!pc->subsystem_id);
804 }
805 pci_init_cmask(pci_dev);
806 pci_init_wmask(pci_dev);
807 pci_init_w1cmask(pci_dev);
808 if (pc->is_bridge) {
809 pci_init_mask_bridge(pci_dev);
810 }
811 if (pci_init_multifunction(bus, pci_dev)) {
812 pci_config_free(pci_dev);
813 return NULL;
814 }
815
816 if (!config_read)
817 config_read = pci_default_read_config;
818 if (!config_write)
819 config_write = pci_default_write_config;
820 pci_dev->config_read = config_read;
821 pci_dev->config_write = config_write;
822 bus->devices[devfn] = pci_dev;
823 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
824 pci_dev->version_id = 2; /* Current pci device vmstate version */
825 return pci_dev;
826 }
827
828 static void do_pci_unregister_device(PCIDevice *pci_dev)
829 {
830 qemu_free_irqs(pci_dev->irq);
831 pci_dev->bus->devices[pci_dev->devfn] = NULL;
832 pci_config_free(pci_dev);
833 }
834
835 static void pci_unregister_io_regions(PCIDevice *pci_dev)
836 {
837 PCIIORegion *r;
838 int i;
839
840 for(i = 0; i < PCI_NUM_REGIONS; i++) {
841 r = &pci_dev->io_regions[i];
842 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
843 continue;
844 memory_region_del_subregion(r->address_space, r->memory);
845 }
846 }
847
848 static int pci_unregister_device(DeviceState *dev)
849 {
850 PCIDevice *pci_dev = PCI_DEVICE(dev);
851 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
852
853 pci_unregister_io_regions(pci_dev);
854 pci_del_option_rom(pci_dev);
855
856 if (pc->exit) {
857 pc->exit(pci_dev);
858 }
859
860 do_pci_unregister_device(pci_dev);
861 return 0;
862 }
863
864 void pci_register_bar(PCIDevice *pci_dev, int region_num,
865 uint8_t type, MemoryRegion *memory)
866 {
867 PCIIORegion *r;
868 uint32_t addr;
869 uint64_t wmask;
870 pcibus_t size = memory_region_size(memory);
871
872 assert(region_num >= 0);
873 assert(region_num < PCI_NUM_REGIONS);
874 if (size & (size-1)) {
875 fprintf(stderr, "ERROR: PCI region size must be pow2 "
876 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
877 exit(1);
878 }
879
880 r = &pci_dev->io_regions[region_num];
881 r->addr = PCI_BAR_UNMAPPED;
882 r->size = size;
883 r->type = type;
884 r->memory = NULL;
885
886 wmask = ~(size - 1);
887 addr = pci_bar(pci_dev, region_num);
888 if (region_num == PCI_ROM_SLOT) {
889 /* ROM enable bit is writable */
890 wmask |= PCI_ROM_ADDRESS_ENABLE;
891 }
892 pci_set_long(pci_dev->config + addr, type);
893 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
894 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
895 pci_set_quad(pci_dev->wmask + addr, wmask);
896 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
897 } else {
898 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
899 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
900 }
901 pci_dev->io_regions[region_num].memory = memory;
902 pci_dev->io_regions[region_num].address_space
903 = type & PCI_BASE_ADDRESS_SPACE_IO
904 ? pci_dev->bus->address_space_io
905 : pci_dev->bus->address_space_mem;
906 }
907
908 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
909 {
910 return pci_dev->io_regions[region_num].addr;
911 }
912
913 static pcibus_t pci_bar_address(PCIDevice *d,
914 int reg, uint8_t type, pcibus_t size)
915 {
916 pcibus_t new_addr, last_addr;
917 int bar = pci_bar(d, reg);
918 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
919
920 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
921 if (!(cmd & PCI_COMMAND_IO)) {
922 return PCI_BAR_UNMAPPED;
923 }
924 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
925 last_addr = new_addr + size - 1;
926 /* NOTE: we have only 64K ioports on PC */
927 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
928 return PCI_BAR_UNMAPPED;
929 }
930 return new_addr;
931 }
932
933 if (!(cmd & PCI_COMMAND_MEMORY)) {
934 return PCI_BAR_UNMAPPED;
935 }
936 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
937 new_addr = pci_get_quad(d->config + bar);
938 } else {
939 new_addr = pci_get_long(d->config + bar);
940 }
941 /* the ROM slot has a specific enable bit */
942 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
943 return PCI_BAR_UNMAPPED;
944 }
945 new_addr &= ~(size - 1);
946 last_addr = new_addr + size - 1;
947 /* NOTE: we do not support wrapping */
948 /* XXX: as we cannot support really dynamic
949 mappings, we handle specific values as invalid
950 mappings. */
951 if (last_addr <= new_addr || new_addr == 0 ||
952 last_addr == PCI_BAR_UNMAPPED) {
953 return PCI_BAR_UNMAPPED;
954 }
955
956 /* Now pcibus_t is 64bit.
957 * Check if 32 bit BAR wraps around explicitly.
958 * Without this, PC ide doesn't work well.
959 * TODO: remove this work around.
960 */
961 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
962 return PCI_BAR_UNMAPPED;
963 }
964
965 /*
966 * OS is allowed to set BAR beyond its addressable
967 * bits. For example, 32 bit OS can set 64bit bar
968 * to >4G. Check it. TODO: we might need to support
969 * it in the future for e.g. PAE.
970 */
971 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
972 return PCI_BAR_UNMAPPED;
973 }
974
975 return new_addr;
976 }
977
978 static void pci_update_mappings(PCIDevice *d)
979 {
980 PCIIORegion *r;
981 int i;
982 pcibus_t new_addr;
983
984 for(i = 0; i < PCI_NUM_REGIONS; i++) {
985 r = &d->io_regions[i];
986
987 /* this region isn't registered */
988 if (!r->size)
989 continue;
990
991 new_addr = pci_bar_address(d, i, r->type, r->size);
992
993 /* This bar isn't changed */
994 if (new_addr == r->addr)
995 continue;
996
997 /* now do the real mapping */
998 if (r->addr != PCI_BAR_UNMAPPED) {
999 memory_region_del_subregion(r->address_space, r->memory);
1000 }
1001 r->addr = new_addr;
1002 if (r->addr != PCI_BAR_UNMAPPED) {
1003 memory_region_add_subregion_overlap(r->address_space,
1004 r->addr, r->memory, 1);
1005 }
1006 }
1007 }
1008
1009 static inline int pci_irq_disabled(PCIDevice *d)
1010 {
1011 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1012 }
1013
1014 /* Called after interrupt disabled field update in config space,
1015 * assert/deassert interrupts if necessary.
1016 * Gets original interrupt disable bit value (before update). */
1017 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1018 {
1019 int i, disabled = pci_irq_disabled(d);
1020 if (disabled == was_irq_disabled)
1021 return;
1022 for (i = 0; i < PCI_NUM_PINS; ++i) {
1023 int state = pci_irq_state(d, i);
1024 pci_change_irq_level(d, i, disabled ? -state : state);
1025 }
1026 }
1027
1028 uint32_t pci_default_read_config(PCIDevice *d,
1029 uint32_t address, int len)
1030 {
1031 uint32_t val = 0;
1032
1033 memcpy(&val, d->config + address, len);
1034 return le32_to_cpu(val);
1035 }
1036
1037 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1038 {
1039 int i, was_irq_disabled = pci_irq_disabled(d);
1040
1041 for (i = 0; i < l; val >>= 8, ++i) {
1042 uint8_t wmask = d->wmask[addr + i];
1043 uint8_t w1cmask = d->w1cmask[addr + i];
1044 assert(!(wmask & w1cmask));
1045 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1046 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1047 }
1048 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1049 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1050 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1051 range_covers_byte(addr, l, PCI_COMMAND))
1052 pci_update_mappings(d);
1053
1054 if (range_covers_byte(addr, l, PCI_COMMAND))
1055 pci_update_irq_disabled(d, was_irq_disabled);
1056
1057 msi_write_config(d, addr, val, l);
1058 msix_write_config(d, addr, val, l);
1059 }
1060
1061 /***********************************************************/
1062 /* generic PCI irq support */
1063
1064 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1065 static void pci_set_irq(void *opaque, int irq_num, int level)
1066 {
1067 PCIDevice *pci_dev = opaque;
1068 int change;
1069
1070 change = level - pci_irq_state(pci_dev, irq_num);
1071 if (!change)
1072 return;
1073
1074 pci_set_irq_state(pci_dev, irq_num, level);
1075 pci_update_irq_status(pci_dev);
1076 if (pci_irq_disabled(pci_dev))
1077 return;
1078 pci_change_irq_level(pci_dev, irq_num, change);
1079 }
1080
1081 /* Special hooks used by device assignment */
1082 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1083 {
1084 assert(!bus->parent_dev);
1085 bus->route_intx_to_irq = route_intx_to_irq;
1086 }
1087
1088 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1089 {
1090 PCIBus *bus;
1091
1092 do {
1093 bus = dev->bus;
1094 pin = bus->map_irq(dev, pin);
1095 dev = bus->parent_dev;
1096 } while (dev);
1097 assert(bus->route_intx_to_irq);
1098 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1099 }
1100
1101 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1102 {
1103 PCIDevice *dev;
1104 PCIBus *sec;
1105 int i;
1106
1107 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1108 dev = bus->devices[i];
1109 if (dev && dev->intx_routing_notifier) {
1110 dev->intx_routing_notifier(dev);
1111 }
1112 QLIST_FOREACH(sec, &bus->child, sibling) {
1113 pci_bus_fire_intx_routing_notifier(sec);
1114 }
1115 }
1116 }
1117
1118 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1119 PCIINTxRoutingNotifier notifier)
1120 {
1121 dev->intx_routing_notifier = notifier;
1122 }
1123
1124 /***********************************************************/
1125 /* monitor info on PCI */
1126
1127 typedef struct {
1128 uint16_t class;
1129 const char *desc;
1130 const char *fw_name;
1131 uint16_t fw_ign_bits;
1132 } pci_class_desc;
1133
1134 static const pci_class_desc pci_class_descriptions[] =
1135 {
1136 { 0x0001, "VGA controller", "display"},
1137 { 0x0100, "SCSI controller", "scsi"},
1138 { 0x0101, "IDE controller", "ide"},
1139 { 0x0102, "Floppy controller", "fdc"},
1140 { 0x0103, "IPI controller", "ipi"},
1141 { 0x0104, "RAID controller", "raid"},
1142 { 0x0106, "SATA controller"},
1143 { 0x0107, "SAS controller"},
1144 { 0x0180, "Storage controller"},
1145 { 0x0200, "Ethernet controller", "ethernet"},
1146 { 0x0201, "Token Ring controller", "token-ring"},
1147 { 0x0202, "FDDI controller", "fddi"},
1148 { 0x0203, "ATM controller", "atm"},
1149 { 0x0280, "Network controller"},
1150 { 0x0300, "VGA controller", "display", 0x00ff},
1151 { 0x0301, "XGA controller"},
1152 { 0x0302, "3D controller"},
1153 { 0x0380, "Display controller"},
1154 { 0x0400, "Video controller", "video"},
1155 { 0x0401, "Audio controller", "sound"},
1156 { 0x0402, "Phone"},
1157 { 0x0403, "Audio controller", "sound"},
1158 { 0x0480, "Multimedia controller"},
1159 { 0x0500, "RAM controller", "memory"},
1160 { 0x0501, "Flash controller", "flash"},
1161 { 0x0580, "Memory controller"},
1162 { 0x0600, "Host bridge", "host"},
1163 { 0x0601, "ISA bridge", "isa"},
1164 { 0x0602, "EISA bridge", "eisa"},
1165 { 0x0603, "MC bridge", "mca"},
1166 { 0x0604, "PCI bridge", "pci"},
1167 { 0x0605, "PCMCIA bridge", "pcmcia"},
1168 { 0x0606, "NUBUS bridge", "nubus"},
1169 { 0x0607, "CARDBUS bridge", "cardbus"},
1170 { 0x0608, "RACEWAY bridge"},
1171 { 0x0680, "Bridge"},
1172 { 0x0700, "Serial port", "serial"},
1173 { 0x0701, "Parallel port", "parallel"},
1174 { 0x0800, "Interrupt controller", "interrupt-controller"},
1175 { 0x0801, "DMA controller", "dma-controller"},
1176 { 0x0802, "Timer", "timer"},
1177 { 0x0803, "RTC", "rtc"},
1178 { 0x0900, "Keyboard", "keyboard"},
1179 { 0x0901, "Pen", "pen"},
1180 { 0x0902, "Mouse", "mouse"},
1181 { 0x0A00, "Dock station", "dock", 0x00ff},
1182 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1183 { 0x0c00, "Fireware contorller", "fireware"},
1184 { 0x0c01, "Access bus controller", "access-bus"},
1185 { 0x0c02, "SSA controller", "ssa"},
1186 { 0x0c03, "USB controller", "usb"},
1187 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1188 { 0, NULL}
1189 };
1190
1191 static void pci_for_each_device_under_bus(PCIBus *bus,
1192 void (*fn)(PCIBus *b, PCIDevice *d,
1193 void *opaque),
1194 void *opaque)
1195 {
1196 PCIDevice *d;
1197 int devfn;
1198
1199 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1200 d = bus->devices[devfn];
1201 if (d) {
1202 fn(bus, d, opaque);
1203 }
1204 }
1205 }
1206
1207 void pci_for_each_device(PCIBus *bus, int bus_num,
1208 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1209 void *opaque)
1210 {
1211 bus = pci_find_bus_nr(bus, bus_num);
1212
1213 if (bus) {
1214 pci_for_each_device_under_bus(bus, fn, opaque);
1215 }
1216 }
1217
1218 static const pci_class_desc *get_class_desc(int class)
1219 {
1220 const pci_class_desc *desc;
1221
1222 desc = pci_class_descriptions;
1223 while (desc->desc && class != desc->class) {
1224 desc++;
1225 }
1226
1227 return desc;
1228 }
1229
1230 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1231
1232 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1233 {
1234 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1235 int i;
1236
1237 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1238 const PCIIORegion *r = &dev->io_regions[i];
1239 PciMemoryRegionList *region;
1240
1241 if (!r->size) {
1242 continue;
1243 }
1244
1245 region = g_malloc0(sizeof(*region));
1246 region->value = g_malloc0(sizeof(*region->value));
1247
1248 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1249 region->value->type = g_strdup("io");
1250 } else {
1251 region->value->type = g_strdup("memory");
1252 region->value->has_prefetch = true;
1253 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1254 region->value->has_mem_type_64 = true;
1255 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1256 }
1257
1258 region->value->bar = i;
1259 region->value->address = r->addr;
1260 region->value->size = r->size;
1261
1262 /* XXX: waiting for the qapi to support GSList */
1263 if (!cur_item) {
1264 head = cur_item = region;
1265 } else {
1266 cur_item->next = region;
1267 cur_item = region;
1268 }
1269 }
1270
1271 return head;
1272 }
1273
1274 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1275 int bus_num)
1276 {
1277 PciBridgeInfo *info;
1278
1279 info = g_malloc0(sizeof(*info));
1280
1281 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1282 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1283 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1284
1285 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1286 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1287 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1288
1289 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1290 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1291 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1292
1293 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1294 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1295 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1296
1297 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1298 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1299 if (child_bus) {
1300 info->has_devices = true;
1301 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1302 }
1303 }
1304
1305 return info;
1306 }
1307
1308 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1309 int bus_num)
1310 {
1311 const pci_class_desc *desc;
1312 PciDeviceInfo *info;
1313 uint8_t type;
1314 int class;
1315
1316 info = g_malloc0(sizeof(*info));
1317 info->bus = bus_num;
1318 info->slot = PCI_SLOT(dev->devfn);
1319 info->function = PCI_FUNC(dev->devfn);
1320
1321 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1322 info->class_info.class = class;
1323 desc = get_class_desc(class);
1324 if (desc->desc) {
1325 info->class_info.has_desc = true;
1326 info->class_info.desc = g_strdup(desc->desc);
1327 }
1328
1329 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1330 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1331 info->regions = qmp_query_pci_regions(dev);
1332 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1333
1334 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1335 info->has_irq = true;
1336 info->irq = dev->config[PCI_INTERRUPT_LINE];
1337 }
1338
1339 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1340 if (type == PCI_HEADER_TYPE_BRIDGE) {
1341 info->has_pci_bridge = true;
1342 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1343 }
1344
1345 return info;
1346 }
1347
1348 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1349 {
1350 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1351 PCIDevice *dev;
1352 int devfn;
1353
1354 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1355 dev = bus->devices[devfn];
1356 if (dev) {
1357 info = g_malloc0(sizeof(*info));
1358 info->value = qmp_query_pci_device(dev, bus, bus_num);
1359
1360 /* XXX: waiting for the qapi to support GSList */
1361 if (!cur_item) {
1362 head = cur_item = info;
1363 } else {
1364 cur_item->next = info;
1365 cur_item = info;
1366 }
1367 }
1368 }
1369
1370 return head;
1371 }
1372
1373 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1374 {
1375 PciInfo *info = NULL;
1376
1377 bus = pci_find_bus_nr(bus, bus_num);
1378 if (bus) {
1379 info = g_malloc0(sizeof(*info));
1380 info->bus = bus_num;
1381 info->devices = qmp_query_pci_devices(bus, bus_num);
1382 }
1383
1384 return info;
1385 }
1386
1387 PciInfoList *qmp_query_pci(Error **errp)
1388 {
1389 PciInfoList *info, *head = NULL, *cur_item = NULL;
1390 struct PCIHostBus *host;
1391
1392 QLIST_FOREACH(host, &host_buses, next) {
1393 info = g_malloc0(sizeof(*info));
1394 info->value = qmp_query_pci_bus(host->bus, 0);
1395
1396 /* XXX: waiting for the qapi to support GSList */
1397 if (!cur_item) {
1398 head = cur_item = info;
1399 } else {
1400 cur_item->next = info;
1401 cur_item = info;
1402 }
1403 }
1404
1405 return head;
1406 }
1407
1408 static const char * const pci_nic_models[] = {
1409 "ne2k_pci",
1410 "i82551",
1411 "i82557b",
1412 "i82559er",
1413 "rtl8139",
1414 "e1000",
1415 "pcnet",
1416 "virtio",
1417 NULL
1418 };
1419
1420 static const char * const pci_nic_names[] = {
1421 "ne2k_pci",
1422 "i82551",
1423 "i82557b",
1424 "i82559er",
1425 "rtl8139",
1426 "e1000",
1427 "pcnet",
1428 "virtio-net-pci",
1429 NULL
1430 };
1431
1432 /* Initialize a PCI NIC. */
1433 /* FIXME callers should check for failure, but don't */
1434 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1435 const char *default_devaddr)
1436 {
1437 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1438 PCIBus *bus;
1439 int devfn;
1440 PCIDevice *pci_dev;
1441 DeviceState *dev;
1442 int i;
1443
1444 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1445 if (i < 0)
1446 return NULL;
1447
1448 bus = pci_get_bus_devfn(&devfn, devaddr);
1449 if (!bus) {
1450 error_report("Invalid PCI device address %s for device %s",
1451 devaddr, pci_nic_names[i]);
1452 return NULL;
1453 }
1454
1455 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1456 dev = &pci_dev->qdev;
1457 qdev_set_nic_properties(dev, nd);
1458 if (qdev_init(dev) < 0)
1459 return NULL;
1460 return pci_dev;
1461 }
1462
1463 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1464 const char *default_devaddr)
1465 {
1466 PCIDevice *res;
1467
1468 if (qemu_show_nic_models(nd->model, pci_nic_models))
1469 exit(0);
1470
1471 res = pci_nic_init(nd, default_model, default_devaddr);
1472 if (!res)
1473 exit(1);
1474 return res;
1475 }
1476
1477 PCIDevice *pci_vga_init(PCIBus *bus)
1478 {
1479 switch (vga_interface_type) {
1480 case VGA_CIRRUS:
1481 return pci_create_simple(bus, -1, "cirrus-vga");
1482 case VGA_QXL:
1483 return pci_create_simple(bus, -1, "qxl-vga");
1484 case VGA_STD:
1485 return pci_create_simple(bus, -1, "VGA");
1486 case VGA_VMWARE:
1487 return pci_create_simple(bus, -1, "vmware-svga");
1488 case VGA_NONE:
1489 default: /* Other non-PCI types. Checking for unsupported types is already
1490 done in vl.c. */
1491 return NULL;
1492 }
1493 }
1494
1495 /* Whether a given bus number is in range of the secondary
1496 * bus of the given bridge device. */
1497 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1498 {
1499 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1500 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1501 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1502 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1503 }
1504
1505 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1506 {
1507 PCIBus *sec;
1508
1509 if (!bus) {
1510 return NULL;
1511 }
1512
1513 if (pci_bus_num(bus) == bus_num) {
1514 return bus;
1515 }
1516
1517 /* Consider all bus numbers in range for the host pci bridge. */
1518 if (bus->parent_dev &&
1519 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1520 return NULL;
1521 }
1522
1523 /* try child bus */
1524 for (; bus; bus = sec) {
1525 QLIST_FOREACH(sec, &bus->child, sibling) {
1526 assert(sec->parent_dev);
1527 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1528 return sec;
1529 }
1530 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1531 break;
1532 }
1533 }
1534 }
1535
1536 return NULL;
1537 }
1538
1539 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1540 {
1541 bus = pci_find_bus_nr(bus, bus_num);
1542
1543 if (!bus)
1544 return NULL;
1545
1546 return bus->devices[devfn];
1547 }
1548
1549 static int pci_qdev_init(DeviceState *qdev)
1550 {
1551 PCIDevice *pci_dev = (PCIDevice *)qdev;
1552 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1553 PCIBus *bus;
1554 int rc;
1555 bool is_default_rom;
1556
1557 /* initialize cap_present for pci_is_express() and pci_config_size() */
1558 if (pc->is_express) {
1559 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1560 }
1561
1562 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1563 pci_dev = do_pci_register_device(pci_dev, bus,
1564 object_get_typename(OBJECT(qdev)),
1565 pci_dev->devfn);
1566 if (pci_dev == NULL)
1567 return -1;
1568 if (qdev->hotplugged && pc->no_hotplug) {
1569 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev)));
1570 do_pci_unregister_device(pci_dev);
1571 return -1;
1572 }
1573 if (pc->init) {
1574 rc = pc->init(pci_dev);
1575 if (rc != 0) {
1576 do_pci_unregister_device(pci_dev);
1577 return rc;
1578 }
1579 }
1580
1581 /* rom loading */
1582 is_default_rom = false;
1583 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1584 pci_dev->romfile = g_strdup(pc->romfile);
1585 is_default_rom = true;
1586 }
1587 pci_add_option_rom(pci_dev, is_default_rom);
1588
1589 if (bus->hotplug) {
1590 /* Let buses differentiate between hotplug and when device is
1591 * enabled during qemu machine creation. */
1592 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1593 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1594 PCI_COLDPLUG_ENABLED);
1595 if (rc != 0) {
1596 int r = pci_unregister_device(&pci_dev->qdev);
1597 assert(!r);
1598 return rc;
1599 }
1600 }
1601 return 0;
1602 }
1603
1604 static int pci_unplug_device(DeviceState *qdev)
1605 {
1606 PCIDevice *dev = PCI_DEVICE(qdev);
1607 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1608
1609 if (pc->no_hotplug) {
1610 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev)));
1611 return -1;
1612 }
1613 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1614 PCI_HOTPLUG_DISABLED);
1615 }
1616
1617 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1618 const char *name)
1619 {
1620 DeviceState *dev;
1621
1622 dev = qdev_create(&bus->qbus, name);
1623 qdev_prop_set_int32(dev, "addr", devfn);
1624 qdev_prop_set_bit(dev, "multifunction", multifunction);
1625 return PCI_DEVICE(dev);
1626 }
1627
1628 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1629 bool multifunction,
1630 const char *name)
1631 {
1632 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1633 qdev_init_nofail(&dev->qdev);
1634 return dev;
1635 }
1636
1637 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1638 {
1639 return pci_create_multifunction(bus, devfn, false, name);
1640 }
1641
1642 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1643 {
1644 return pci_create_simple_multifunction(bus, devfn, false, name);
1645 }
1646
1647 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1648 {
1649 int config_size = pci_config_size(pdev);
1650 int offset = PCI_CONFIG_HEADER_SIZE;
1651 int i;
1652 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1653 if (pdev->used[i])
1654 offset = i + 1;
1655 else if (i - offset + 1 == size)
1656 return offset;
1657 return 0;
1658 }
1659
1660 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1661 uint8_t *prev_p)
1662 {
1663 uint8_t next, prev;
1664
1665 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1666 return 0;
1667
1668 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1669 prev = next + PCI_CAP_LIST_NEXT)
1670 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1671 break;
1672
1673 if (prev_p)
1674 *prev_p = prev;
1675 return next;
1676 }
1677
1678 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1679 {
1680 uint8_t next, prev, found = 0;
1681
1682 if (!(pdev->used[offset])) {
1683 return 0;
1684 }
1685
1686 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1687
1688 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1689 prev = next + PCI_CAP_LIST_NEXT) {
1690 if (next <= offset && next > found) {
1691 found = next;
1692 }
1693 }
1694 return found;
1695 }
1696
1697 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1698 This is needed for an option rom which is used for more than one device. */
1699 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1700 {
1701 uint16_t vendor_id;
1702 uint16_t device_id;
1703 uint16_t rom_vendor_id;
1704 uint16_t rom_device_id;
1705 uint16_t rom_magic;
1706 uint16_t pcir_offset;
1707 uint8_t checksum;
1708
1709 /* Words in rom data are little endian (like in PCI configuration),
1710 so they can be read / written with pci_get_word / pci_set_word. */
1711
1712 /* Only a valid rom will be patched. */
1713 rom_magic = pci_get_word(ptr);
1714 if (rom_magic != 0xaa55) {
1715 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1716 return;
1717 }
1718 pcir_offset = pci_get_word(ptr + 0x18);
1719 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1720 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1721 return;
1722 }
1723
1724 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1725 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1726 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1727 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1728
1729 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1730 vendor_id, device_id, rom_vendor_id, rom_device_id);
1731
1732 checksum = ptr[6];
1733
1734 if (vendor_id != rom_vendor_id) {
1735 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1736 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1737 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1738 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1739 ptr[6] = checksum;
1740 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1741 }
1742
1743 if (device_id != rom_device_id) {
1744 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1745 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1746 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1747 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1748 ptr[6] = checksum;
1749 pci_set_word(ptr + pcir_offset + 6, device_id);
1750 }
1751 }
1752
1753 /* Add an option rom for the device */
1754 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1755 {
1756 int size;
1757 char *path;
1758 void *ptr;
1759 char name[32];
1760 const VMStateDescription *vmsd;
1761
1762 if (!pdev->romfile)
1763 return 0;
1764 if (strlen(pdev->romfile) == 0)
1765 return 0;
1766
1767 if (!pdev->rom_bar) {
1768 /*
1769 * Load rom via fw_cfg instead of creating a rom bar,
1770 * for 0.11 compatibility.
1771 */
1772 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1773 if (class == 0x0300) {
1774 rom_add_vga(pdev->romfile);
1775 } else {
1776 rom_add_option(pdev->romfile, -1);
1777 }
1778 return 0;
1779 }
1780
1781 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1782 if (path == NULL) {
1783 path = g_strdup(pdev->romfile);
1784 }
1785
1786 size = get_image_size(path);
1787 if (size < 0) {
1788 error_report("%s: failed to find romfile \"%s\"",
1789 __FUNCTION__, pdev->romfile);
1790 g_free(path);
1791 return -1;
1792 }
1793 if (size & (size - 1)) {
1794 size = 1 << qemu_fls(size);
1795 }
1796
1797 vmsd = qdev_get_vmsd(DEVICE(pdev));
1798
1799 if (vmsd) {
1800 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1801 } else {
1802 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
1803 }
1804 pdev->has_rom = true;
1805 memory_region_init_ram(&pdev->rom, name, size);
1806 vmstate_register_ram(&pdev->rom, &pdev->qdev);
1807 ptr = memory_region_get_ram_ptr(&pdev->rom);
1808 load_image(path, ptr);
1809 g_free(path);
1810
1811 if (is_default_rom) {
1812 /* Only the default rom images will be patched (if needed). */
1813 pci_patch_ids(pdev, ptr, size);
1814 }
1815
1816 qemu_put_ram_ptr(ptr);
1817
1818 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1819
1820 return 0;
1821 }
1822
1823 static void pci_del_option_rom(PCIDevice *pdev)
1824 {
1825 if (!pdev->has_rom)
1826 return;
1827
1828 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1829 memory_region_destroy(&pdev->rom);
1830 pdev->has_rom = false;
1831 }
1832
1833 /*
1834 * if !offset
1835 * Reserve space and add capability to the linked list in pci config space
1836 *
1837 * if offset = 0,
1838 * Find and reserve space and add capability to the linked list
1839 * in pci config space */
1840 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1841 uint8_t offset, uint8_t size)
1842 {
1843 uint8_t *config;
1844 int i, overlapping_cap;
1845
1846 if (!offset) {
1847 offset = pci_find_space(pdev, size);
1848 if (!offset) {
1849 return -ENOSPC;
1850 }
1851 } else {
1852 /* Verify that capabilities don't overlap. Note: device assignment
1853 * depends on this check to verify that the device is not broken.
1854 * Should never trigger for emulated devices, but it's helpful
1855 * for debugging these. */
1856 for (i = offset; i < offset + size; i++) {
1857 overlapping_cap = pci_find_capability_at_offset(pdev, i);
1858 if (overlapping_cap) {
1859 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
1860 "Attempt to add PCI capability %x at offset "
1861 "%x overlaps existing capability %x at offset %x\n",
1862 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
1863 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1864 cap_id, offset, overlapping_cap, i);
1865 return -EINVAL;
1866 }
1867 }
1868 }
1869
1870 config = pdev->config + offset;
1871 config[PCI_CAP_LIST_ID] = cap_id;
1872 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1873 pdev->config[PCI_CAPABILITY_LIST] = offset;
1874 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1875 memset(pdev->used + offset, 0xFF, size);
1876 /* Make capability read-only by default */
1877 memset(pdev->wmask + offset, 0, size);
1878 /* Check capability by default */
1879 memset(pdev->cmask + offset, 0xFF, size);
1880 return offset;
1881 }
1882
1883 /* Unlink capability from the pci config space. */
1884 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1885 {
1886 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1887 if (!offset)
1888 return;
1889 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1890 /* Make capability writable again */
1891 memset(pdev->wmask + offset, 0xff, size);
1892 memset(pdev->w1cmask + offset, 0, size);
1893 /* Clear cmask as device-specific registers can't be checked */
1894 memset(pdev->cmask + offset, 0, size);
1895 memset(pdev->used + offset, 0, size);
1896
1897 if (!pdev->config[PCI_CAPABILITY_LIST])
1898 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1899 }
1900
1901 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1902 {
1903 return pci_find_capability_list(pdev, cap_id, NULL);
1904 }
1905
1906 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1907 {
1908 PCIDevice *d = (PCIDevice *)dev;
1909 const pci_class_desc *desc;
1910 char ctxt[64];
1911 PCIIORegion *r;
1912 int i, class;
1913
1914 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1915 desc = pci_class_descriptions;
1916 while (desc->desc && class != desc->class)
1917 desc++;
1918 if (desc->desc) {
1919 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1920 } else {
1921 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1922 }
1923
1924 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1925 "pci id %04x:%04x (sub %04x:%04x)\n",
1926 indent, "", ctxt, pci_bus_num(d->bus),
1927 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1928 pci_get_word(d->config + PCI_VENDOR_ID),
1929 pci_get_word(d->config + PCI_DEVICE_ID),
1930 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1931 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1932 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1933 r = &d->io_regions[i];
1934 if (!r->size)
1935 continue;
1936 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1937 " [0x%"FMT_PCIBUS"]\n",
1938 indent, "",
1939 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1940 r->addr, r->addr + r->size - 1);
1941 }
1942 }
1943
1944 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1945 {
1946 PCIDevice *d = (PCIDevice *)dev;
1947 const char *name = NULL;
1948 const pci_class_desc *desc = pci_class_descriptions;
1949 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1950
1951 while (desc->desc &&
1952 (class & ~desc->fw_ign_bits) !=
1953 (desc->class & ~desc->fw_ign_bits)) {
1954 desc++;
1955 }
1956
1957 if (desc->desc) {
1958 name = desc->fw_name;
1959 }
1960
1961 if (name) {
1962 pstrcpy(buf, len, name);
1963 } else {
1964 snprintf(buf, len, "pci%04x,%04x",
1965 pci_get_word(d->config + PCI_VENDOR_ID),
1966 pci_get_word(d->config + PCI_DEVICE_ID));
1967 }
1968
1969 return buf;
1970 }
1971
1972 static char *pcibus_get_fw_dev_path(DeviceState *dev)
1973 {
1974 PCIDevice *d = (PCIDevice *)dev;
1975 char path[50], name[33];
1976 int off;
1977
1978 off = snprintf(path, sizeof(path), "%s@%x",
1979 pci_dev_fw_name(dev, name, sizeof name),
1980 PCI_SLOT(d->devfn));
1981 if (PCI_FUNC(d->devfn))
1982 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
1983 return g_strdup(path);
1984 }
1985
1986 static char *pcibus_get_dev_path(DeviceState *dev)
1987 {
1988 PCIDevice *d = container_of(dev, PCIDevice, qdev);
1989 PCIDevice *t;
1990 int slot_depth;
1991 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1992 * 00 is added here to make this format compatible with
1993 * domain:Bus:Slot.Func for systems without nested PCI bridges.
1994 * Slot.Function list specifies the slot and function numbers for all
1995 * devices on the path from root to the specific device. */
1996 char domain[] = "DDDD:00";
1997 char slot[] = ":SS.F";
1998 int domain_len = sizeof domain - 1 /* For '\0' */;
1999 int slot_len = sizeof slot - 1 /* For '\0' */;
2000 int path_len;
2001 char *path, *p;
2002 int s;
2003
2004 /* Calculate # of slots on path between device and root. */;
2005 slot_depth = 0;
2006 for (t = d; t; t = t->bus->parent_dev) {
2007 ++slot_depth;
2008 }
2009
2010 path_len = domain_len + slot_len * slot_depth;
2011
2012 /* Allocate memory, fill in the terminating null byte. */
2013 path = g_malloc(path_len + 1 /* For '\0' */);
2014 path[path_len] = '\0';
2015
2016 /* First field is the domain. */
2017 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2018 assert(s == domain_len);
2019 memcpy(path, domain, domain_len);
2020
2021 /* Fill in slot numbers. We walk up from device to root, so need to print
2022 * them in the reverse order, last to first. */
2023 p = path + path_len;
2024 for (t = d; t; t = t->bus->parent_dev) {
2025 p -= slot_len;
2026 s = snprintf(slot, sizeof slot, ":%02x.%x",
2027 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2028 assert(s == slot_len);
2029 memcpy(p, slot, slot_len);
2030 }
2031
2032 return path;
2033 }
2034
2035 static int pci_qdev_find_recursive(PCIBus *bus,
2036 const char *id, PCIDevice **pdev)
2037 {
2038 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2039 if (!qdev) {
2040 return -ENODEV;
2041 }
2042
2043 /* roughly check if given qdev is pci device */
2044 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2045 *pdev = PCI_DEVICE(qdev);
2046 return 0;
2047 }
2048 return -EINVAL;
2049 }
2050
2051 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2052 {
2053 struct PCIHostBus *host;
2054 int rc = -ENODEV;
2055
2056 QLIST_FOREACH(host, &host_buses, next) {
2057 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2058 if (!tmp) {
2059 rc = 0;
2060 break;
2061 }
2062 if (tmp != -ENODEV) {
2063 rc = tmp;
2064 }
2065 }
2066
2067 return rc;
2068 }
2069
2070 MemoryRegion *pci_address_space(PCIDevice *dev)
2071 {
2072 return dev->bus->address_space_mem;
2073 }
2074
2075 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2076 {
2077 return dev->bus->address_space_io;
2078 }
2079
2080 static void pci_device_class_init(ObjectClass *klass, void *data)
2081 {
2082 DeviceClass *k = DEVICE_CLASS(klass);
2083 k->init = pci_qdev_init;
2084 k->unplug = pci_unplug_device;
2085 k->exit = pci_unregister_device;
2086 k->bus_type = TYPE_PCI_BUS;
2087 k->props = pci_props;
2088 }
2089
2090 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque)
2091 {
2092 bus->dma_context_fn = fn;
2093 bus->dma_context_opaque = opaque;
2094 }
2095
2096 static TypeInfo pci_device_type_info = {
2097 .name = TYPE_PCI_DEVICE,
2098 .parent = TYPE_DEVICE,
2099 .instance_size = sizeof(PCIDevice),
2100 .abstract = true,
2101 .class_size = sizeof(PCIDeviceClass),
2102 .class_init = pci_device_class_init,
2103 };
2104
2105 static void pci_register_types(void)
2106 {
2107 type_register_static(&pci_bus_info);
2108 type_register_static(&pci_device_type_info);
2109 }
2110
2111 type_init(pci_register_types)
Various patches