hw/ppce500_pci.c

   1 /*
   2  * QEMU PowerPC E500 embedded processors pci controller emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc4xx_pci.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "pci.h"
  19 #include "pci_host.h"
  20 #include "bswap.h"
  21
  22 #ifdef DEBUG_PCI
  23 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
  24 #else
  25 #define pci_debug(fmt, ...)
  26 #endif
  27
  28 #define PCIE500_CFGADDR       0x0
  29 #define PCIE500_CFGDATA       0x4
  30 #define PCIE500_REG_BASE      0xC00
  31 #define PCIE500_ALL_SIZE      0x1000
  32 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
  33
  34 #define PPCE500_PCI_CONFIG_ADDR         0x0
  35 #define PPCE500_PCI_CONFIG_DATA         0x4
  36 #define PPCE500_PCI_INTACK              0x8
  37
  38 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
  39 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
  40 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
  41 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
  42 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
  43 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
  44 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
  45
  46 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
  47
  48 #define PCI_POTAR               0x0
  49 #define PCI_POTEAR              0x4
  50 #define PCI_POWBAR              0x8
  51 #define PCI_POWAR               0x10
  52
  53 #define PCI_PITAR               0x0
  54 #define PCI_PIWBAR              0x8
  55 #define PCI_PIWBEAR             0xC
  56 #define PCI_PIWAR               0x10
  57
  58 #define PPCE500_PCI_NR_POBS     5
  59 #define PPCE500_PCI_NR_PIBS     3
  60
  61 struct  pci_outbound {
  62     uint32_t potar;
  63     uint32_t potear;
  64     uint32_t powbar;
  65     uint32_t powar;
  66 };
  67
  68 struct pci_inbound {
  69     uint32_t pitar;
  70     uint32_t piwbar;
  71     uint32_t piwbear;
  72     uint32_t piwar;
  73 };
  74
  75 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
  76
  77 #define PPC_E500_PCI_HOST_BRIDGE(obj) \
  78     OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
  79
  80 struct PPCE500PCIState {
  81     PCIHostState parent_obj;
  82
  83     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
  84     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
  85     uint32_t gasket_time;
  86     qemu_irq irq[4];
  87     /* mmio maps */
  88     MemoryRegion container;
  89     MemoryRegion iomem;
  90 };
  91
  92 typedef struct PPCE500PCIState PPCE500PCIState;
  93
  94 static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
  95                               unsigned size)
  96 {
  97     PPCE500PCIState *pci = opaque;
  98     unsigned long win;
  99     uint32_t value = 0;
 100     int idx;
 101
 102     win = addr & 0xfe0;
 103
 104     switch (win) {
 105     case PPCE500_PCI_OW1:
 106     case PPCE500_PCI_OW2:
 107     case PPCE500_PCI_OW3:
 108     case PPCE500_PCI_OW4:
 109         idx = (addr >> 5) & 0x7;
 110         switch (addr & 0xC) {
 111         case PCI_POTAR:
 112             value = pci->pob[idx].potar;
 113             break;
 114         case PCI_POTEAR:
 115             value = pci->pob[idx].potear;
 116             break;
 117         case PCI_POWBAR:
 118             value = pci->pob[idx].powbar;
 119             break;
 120         case PCI_POWAR:
 121             value = pci->pob[idx].powar;
 122             break;
 123         default:
 124             break;
 125         }
 126         break;
 127
 128     case PPCE500_PCI_IW3:
 129     case PPCE500_PCI_IW2:
 130     case PPCE500_PCI_IW1:
 131         idx = ((addr >> 5) & 0x3) - 1;
 132         switch (addr & 0xC) {
 133         case PCI_PITAR:
 134             value = pci->pib[idx].pitar;
 135             break;
 136         case PCI_PIWBAR:
 137             value = pci->pib[idx].piwbar;
 138             break;
 139         case PCI_PIWBEAR:
 140             value = pci->pib[idx].piwbear;
 141             break;
 142         case PCI_PIWAR:
 143             value = pci->pib[idx].piwar;
 144             break;
 145         default:
 146             break;
 147         };
 148         break;
 149
 150     case PPCE500_PCI_GASKET_TIMR:
 151         value = pci->gasket_time;
 152         break;
 153
 154     default:
 155         break;
 156     }
 157
 158     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
 159               win, addr, value);
 160     return value;
 161 }
 162
 163 static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
 164                            uint64_t value, unsigned size)
 165 {
 166     PPCE500PCIState *pci = opaque;
 167     unsigned long win;
 168     int idx;
 169
 170     win = addr & 0xfe0;
 171
 172     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
 173               __func__, (unsigned)value, win, addr);
 174
 175     switch (win) {
 176     case PPCE500_PCI_OW1:
 177     case PPCE500_PCI_OW2:
 178     case PPCE500_PCI_OW3:
 179     case PPCE500_PCI_OW4:
 180         idx = (addr >> 5) & 0x7;
 181         switch (addr & 0xC) {
 182         case PCI_POTAR:
 183             pci->pob[idx].potar = value;
 184             break;
 185         case PCI_POTEAR:
 186             pci->pob[idx].potear = value;
 187             break;
 188         case PCI_POWBAR:
 189             pci->pob[idx].powbar = value;
 190             break;
 191         case PCI_POWAR:
 192             pci->pob[idx].powar = value;
 193             break;
 194         default:
 195             break;
 196         };
 197         break;
 198
 199     case PPCE500_PCI_IW3:
 200     case PPCE500_PCI_IW2:
 201     case PPCE500_PCI_IW1:
 202         idx = ((addr >> 5) & 0x3) - 1;
 203         switch (addr & 0xC) {
 204         case PCI_PITAR:
 205             pci->pib[idx].pitar = value;
 206             break;
 207         case PCI_PIWBAR:
 208             pci->pib[idx].piwbar = value;
 209             break;
 210         case PCI_PIWBEAR:
 211             pci->pib[idx].piwbear = value;
 212             break;
 213         case PCI_PIWAR:
 214             pci->pib[idx].piwar = value;
 215             break;
 216         default:
 217             break;
 218         };
 219         break;
 220
 221     case PPCE500_PCI_GASKET_TIMR:
 222         pci->gasket_time = value;
 223         break;
 224
 225     default:
 226         break;
 227     };
 228 }
 229
 230 static const MemoryRegionOps e500_pci_reg_ops = {
 231     .read = pci_reg_read4,
 232     .write = pci_reg_write4,
 233     .endianness = DEVICE_BIG_ENDIAN,
 234 };
 235
 236 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 237 {
 238     int devno = pci_dev->devfn >> 3, ret = 0;
 239
 240     switch (devno) {
 241         /* Two PCI slot */
 242         case 0x11:
 243         case 0x12:
 244             ret = (irq_num + devno - 0x10) % 4;
 245             break;
 246         default:
 247             printf("Error:%s:unknown dev number\n", __func__);
 248     }
 249
 250     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
 251            pci_dev->devfn, irq_num, ret, devno);
 252
 253     return ret;
 254 }
 255
 256 static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
 257 {
 258     qemu_irq *pic = opaque;
 259
 260     pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
 261
 262     qemu_set_irq(pic[irq_num], level);
 263 }
 264
 265 static const VMStateDescription vmstate_pci_outbound = {
 266     .name = "pci_outbound",
 267     .version_id = 0,
 268     .minimum_version_id = 0,
 269     .minimum_version_id_old = 0,
 270     .fields      = (VMStateField[]) {
 271         VMSTATE_UINT32(potar, struct pci_outbound),
 272         VMSTATE_UINT32(potear, struct pci_outbound),
 273         VMSTATE_UINT32(powbar, struct pci_outbound),
 274         VMSTATE_UINT32(powar, struct pci_outbound),
 275         VMSTATE_END_OF_LIST()
 276     }
 277 };
 278
 279 static const VMStateDescription vmstate_pci_inbound = {
 280     .name = "pci_inbound",
 281     .version_id = 0,
 282     .minimum_version_id = 0,
 283     .minimum_version_id_old = 0,
 284     .fields      = (VMStateField[]) {
 285         VMSTATE_UINT32(pitar, struct pci_inbound),
 286         VMSTATE_UINT32(piwbar, struct pci_inbound),
 287         VMSTATE_UINT32(piwbear, struct pci_inbound),
 288         VMSTATE_UINT32(piwar, struct pci_inbound),
 289         VMSTATE_END_OF_LIST()
 290     }
 291 };
 292
 293 static const VMStateDescription vmstate_ppce500_pci = {
 294     .name = "ppce500_pci",
 295     .version_id = 1,
 296     .minimum_version_id = 1,
 297     .minimum_version_id_old = 1,
 298     .fields      = (VMStateField[]) {
 299         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
 300                              vmstate_pci_outbound, struct pci_outbound),
 301         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
 302                              vmstate_pci_outbound, struct pci_inbound),
 303         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 #include "exec-memory.h"
 309
 310 static int e500_pcihost_initfn(SysBusDevice *dev)
 311 {
 312     PCIHostState *h;
 313     PPCE500PCIState *s;
 314     PCIBus *b;
 315     int i;
 316     MemoryRegion *address_space_mem = get_system_memory();
 317     MemoryRegion *address_space_io = get_system_io();
 318
 319     h = PCI_HOST_BRIDGE(dev);
 320     s = PPC_E500_PCI_HOST_BRIDGE(dev);
 321
 322     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 323         sysbus_init_irq(dev, &s->irq[i]);
 324     }
 325
 326     b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
 327                          mpc85xx_pci_map_irq, s->irq, address_space_mem,
 328                          address_space_io, PCI_DEVFN(0x11, 0), 4);
 329     h->bus = b;
 330
 331     pci_create_simple(b, 0, "e500-host-bridge");
 332
 333     memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
 334     memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
 335                           "pci-conf-idx", 4);
 336     memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
 337                           "pci-conf-data", 4);
 338     memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
 339                           "pci.reg", PCIE500_REG_SIZE);
 340     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
 341     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
 342     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
 343     sysbus_init_mmio(dev, &s->container);
 344
 345     return 0;
 346 }
 347
 348 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
 349 {
 350     DeviceClass *dc = DEVICE_CLASS(klass);
 351     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 352
 353     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
 354     k->device_id = PCI_DEVICE_ID_MPC8533E;
 355     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
 356     dc->desc = "Host bridge";
 357 }
 358
 359 static const TypeInfo e500_host_bridge_info = {
 360     .name          = "e500-host-bridge",
 361     .parent        = TYPE_PCI_DEVICE,
 362     .instance_size = sizeof(PCIDevice),
 363     .class_init    = e500_host_bridge_class_init,
 364 };
 365
 366 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
 367 {
 368     DeviceClass *dc = DEVICE_CLASS(klass);
 369     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 370
 371     k->init = e500_pcihost_initfn;
 372     dc->vmsd = &vmstate_ppce500_pci;
 373 }
 374
 375 static const TypeInfo e500_pcihost_info = {
 376     .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
 377     .parent        = TYPE_PCI_HOST_BRIDGE,
 378     .instance_size = sizeof(PPCE500PCIState),
 379     .class_init    = e500_pcihost_class_init,
 380 };
 381
 382 static void e500_pci_register_types(void)
 383 {
 384     type_register_static(&e500_pcihost_info);
 385     type_register_static(&e500_host_bridge_info);
 386 }
 387
 388 type_init(e500_pci_register_types)