hw/ppc/e500.c

   1 /*
   2  * QEMU PowerPC e500-based platforms
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "e500.h"
  20 #include "e500-ccsr.h"
  21 #include "net/net.h"
  22 #include "qemu/config-file.h"
  23 #include "hw/hw.h"
  24 #include "hw/serial.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/kvm.h"
  29 #include "kvm_ppc.h"
  30 #include "sysemu/device_tree.h"
  31 #include "hw/openpic.h"
  32 #include "hw/ppc.h"
  33 #include "hw/loader.h"
  34 #include "elf.h"
  35 #include "hw/sysbus.h"
  36 #include "exec/address-spaces.h"
  37 #include "qemu/host-utils.h"
  38 #include "hw/ppce500_pci.h"
  39
  40 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  41 #define UIMAGE_LOAD_BASE           0
  42 #define DTC_LOAD_PAD               0x1800000
  43 #define DTC_PAD_MASK               0xFFFFF
  44 #define DTB_MAX_SIZE               (8 * 1024 * 1024)
  45 #define INITRD_LOAD_PAD            0x2000000
  46 #define INITRD_PAD_MASK            0xFFFFFF
  47
  48 #define RAM_SIZES_ALIGN            (64UL << 20)
  49
  50 /* TODO: parameterize */
  51 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  52 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  53 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
  54 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
  55 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
  56 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
  57 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
  58 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \
  59                                     MPC8544_PCI_REGS_OFFSET)
  60 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  61 #define MPC8544_PCI_IO             0xE1000000ULL
  62 #define MPC8544_UTIL_OFFSET        0xe0000ULL
  63 #define MPC8544_SPIN_BASE          0xEF000000ULL
  64
  65 struct boot_info
  66 {
  67     uint32_t dt_base;
  68     uint32_t dt_size;
  69     uint32_t entry;
  70 };
  71
  72 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
  73                                 int nr_slots, int *len)
  74 {
  75     int i = 0;
  76     int slot;
  77     int pci_irq;
  78     int host_irq;
  79     int last_slot = first_slot + nr_slots;
  80     uint32_t *pci_map;
  81
  82     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
  83     pci_map = g_malloc(*len);
  84
  85     for (slot = first_slot; slot < last_slot; slot++) {
  86         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
  87             pci_map[i++] = cpu_to_be32(slot << 11);
  88             pci_map[i++] = cpu_to_be32(0x0);
  89             pci_map[i++] = cpu_to_be32(0x0);
  90             pci_map[i++] = cpu_to_be32(pci_irq + 1);
  91             pci_map[i++] = cpu_to_be32(mpic);
  92             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
  93             pci_map[i++] = cpu_to_be32(host_irq + 1);
  94             pci_map[i++] = cpu_to_be32(0x1);
  95         }
  96     }
  97
  98     assert((i * sizeof(uint32_t)) == *len);
  99
 100     return pci_map;
 101 }
 102
 103 static void dt_serial_create(void *fdt, unsigned long long offset,
 104                              const char *soc, const char *mpic,
 105                              const char *alias, int idx, bool defcon)
 106 {
 107     char ser[128];
 108
 109     snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
 110     qemu_devtree_add_subnode(fdt, ser);
 111     qemu_devtree_setprop_string(fdt, ser, "device_type", "serial");
 112     qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550");
 113     qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100);
 114     qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
 115     qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0);
 116     qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2);
 117     qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
 118     qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
 119
 120     if (defcon) {
 121         qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
 122     }
 123 }
 124
 125 static int ppce500_load_device_tree(CPUPPCState *env,
 126                                     PPCE500Params *params,
 127                                     hwaddr addr,
 128                                     hwaddr initrd_base,
 129                                     hwaddr initrd_size)
 130 {
 131     int ret = -1;
 132     uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
 133     int fdt_size;
 134     void *fdt;
 135     uint8_t hypercall[16];
 136     uint32_t clock_freq = 400000000;
 137     uint32_t tb_freq = 400000000;
 138     int i;
 139     const char *toplevel_compat = NULL; /* user override */
 140     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 141     char soc[128];
 142     char mpic[128];
 143     uint32_t mpic_ph;
 144     uint32_t msi_ph;
 145     char gutil[128];
 146     char pci[128];
 147     char msi[128];
 148     uint32_t *pci_map = NULL;
 149     int len;
 150     uint32_t pci_ranges[14] =
 151         {
 152             0x2000000, 0x0, 0xc0000000,
 153             0x0, 0xc0000000,
 154             0x0, 0x20000000,
 155
 156             0x1000000, 0x0, 0x0,
 157             0x0, 0xe1000000,
 158             0x0, 0x10000,
 159         };
 160     QemuOpts *machine_opts;
 161     const char *dtb_file = NULL;
 162
 163     machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
 164     if (machine_opts) {
 165         dtb_file = qemu_opt_get(machine_opts, "dtb");
 166         toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
 167     }
 168
 169     if (dtb_file) {
 170         char *filename;
 171         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 172         if (!filename) {
 173             goto out;
 174         }
 175
 176         fdt = load_device_tree(filename, &fdt_size);
 177         if (!fdt) {
 178             goto out;
 179         }
 180         goto done;
 181     }
 182
 183     fdt = create_device_tree(&fdt_size);
 184     if (fdt == NULL) {
 185         goto out;
 186     }
 187
 188     /* Manipulate device tree in memory. */
 189     qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
 190     qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
 191
 192     qemu_devtree_add_subnode(fdt, "/memory");
 193     qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
 194     qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
 195                          sizeof(mem_reg_property));
 196
 197     qemu_devtree_add_subnode(fdt, "/chosen");
 198     if (initrd_size) {
 199         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 200                                         initrd_base);
 201         if (ret < 0) {
 202             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 203         }
 204
 205         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 206                                         (initrd_base + initrd_size));
 207         if (ret < 0) {
 208             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 209         }
 210     }
 211
 212     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 213                                       params->kernel_cmdline);
 214     if (ret < 0)
 215         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 216
 217     if (kvm_enabled()) {
 218         /* Read out host's frequencies */
 219         clock_freq = kvmppc_get_clockfreq();
 220         tb_freq = kvmppc_get_tbfreq();
 221
 222         /* indicate KVM hypercall interface */
 223         qemu_devtree_add_subnode(fdt, "/hypervisor");
 224         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 225                                     "linux,kvm");
 226         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 227         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 228                              hypercall, sizeof(hypercall));
 229         /* if KVM supports the idle hcall, set property indicating this */
 230         if (kvmppc_get_hasidle(env)) {
 231             qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
 232         }
 233     }
 234
 235     /* Create CPU nodes */
 236     qemu_devtree_add_subnode(fdt, "/cpus");
 237     qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 238     qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 239
 240     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 241        the first node as boot node and be happy */
 242     for (i = smp_cpus - 1; i >= 0; i--) {
 243         CPUState *cpu = NULL;
 244         char cpu_name[128];
 245         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 246
 247         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 248             cpu = ENV_GET_CPU(env);
 249             if (cpu->cpu_index == i) {
 250                 break;
 251             }
 252         }
 253
 254         if (cpu == NULL) {
 255             continue;
 256         }
 257
 258         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
 259                  cpu->cpu_index);
 260         qemu_devtree_add_subnode(fdt, cpu_name);
 261         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 262         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 263         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 264         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index);
 265         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 266                                   env->dcache_line_size);
 267         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 268                                   env->icache_line_size);
 269         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 270         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 271         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 272         if (cpu->cpu_index) {
 273             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 274             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 275             qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 276                                      cpu_release_addr);
 277         } else {
 278             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 279         }
 280     }
 281
 282     qemu_devtree_add_subnode(fdt, "/aliases");
 283     /* XXX These should go into their respective devices' code */
 284     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 285     qemu_devtree_add_subnode(fdt, soc);
 286     qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
 287     qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
 288                          sizeof(compatible_sb));
 289     qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
 290     qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
 291     qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
 292                                MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 293                                MPC8544_CCSRBAR_SIZE);
 294     /* XXX should contain a reasonable value */
 295     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 296
 297     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
 298     qemu_devtree_add_subnode(fdt, mpic);
 299     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
 300     qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
 301     qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
 302                                0x40000);
 303     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
 304     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
 305     mpic_ph = qemu_devtree_alloc_phandle(fdt);
 306     qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 307     qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 308     qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 309
 310     /*
 311      * We have to generate ser1 first, because Linux takes the first
 312      * device it finds in the dt as serial output device. And we generate
 313      * devices in reverse order to the dt.
 314      */
 315     dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
 316                      soc, mpic, "serial1", 1, false);
 317     dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
 318                      soc, mpic, "serial0", 0, true);
 319
 320     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 321              MPC8544_UTIL_OFFSET);
 322     qemu_devtree_add_subnode(fdt, gutil);
 323     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 324     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
 325     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 326
 327     snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
 328     qemu_devtree_add_subnode(fdt, msi);
 329     qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
 330     qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
 331     msi_ph = qemu_devtree_alloc_phandle(fdt);
 332     qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
 333     qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
 334     qemu_devtree_setprop_cells(fdt, msi, "interrupts",
 335         0xe0, 0x0,
 336         0xe1, 0x0,
 337         0xe2, 0x0,
 338         0xe3, 0x0,
 339         0xe4, 0x0,
 340         0xe5, 0x0,
 341         0xe6, 0x0,
 342         0xe7, 0x0);
 343     qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
 344     qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
 345
 346     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 347     qemu_devtree_add_subnode(fdt, pci);
 348     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
 349     qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 350     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
 351     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 352                                0x0, 0x7);
 353     pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
 354                              params->pci_first_slot, params->pci_nr_slots,
 355                              &len);
 356     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
 357     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 358     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
 359     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
 360     for (i = 0; i < 14; i++) {
 361         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 362     }
 363     qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
 364     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 365     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 366                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
 367     qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 368     qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 369     qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
 370     qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
 371     qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
 372
 373     params->fixup_devtree(params, fdt);
 374
 375     if (toplevel_compat) {
 376         qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat,
 377                              strlen(toplevel_compat) + 1);
 378     }
 379
 380 done:
 381     qemu_devtree_dumpdtb(fdt, fdt_size);
 382     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 383     if (ret < 0) {
 384         goto out;
 385     }
 386     g_free(fdt);
 387     ret = fdt_size;
 388
 389 out:
 390     g_free(pci_map);
 391
 392     return ret;
 393 }
 394
 395 /* Create -kernel TLB entries for BookE.  */
 396 static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
 397 {
 398     return 63 - clz64(size >> 10);
 399 }
 400
 401 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 402 {
 403     struct boot_info *bi = env->load_info;
 404     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 405     hwaddr size, dt_end;
 406     int ps;
 407
 408     /* Our initial TLB entry needs to cover everything from 0 to
 409        the device tree top */
 410     dt_end = bi->dt_base + bi->dt_size;
 411     ps = booke206_page_size_to_tlb(dt_end) + 1;
 412     if (ps & 1) {
 413         /* e500v2 can only do even TLB size bits */
 414         ps++;
 415     }
 416     size = (ps << MAS1_TSIZE_SHIFT);
 417     tlb->mas1 = MAS1_VALID | size;
 418     tlb->mas2 = 0;
 419     tlb->mas7_3 = 0;
 420     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 421
 422     env->tlb_dirty = true;
 423 }
 424
 425 static void ppce500_cpu_reset_sec(void *opaque)
 426 {
 427     PowerPCCPU *cpu = opaque;
 428     CPUPPCState *env = &cpu->env;
 429
 430     cpu_reset(CPU(cpu));
 431
 432     /* Secondary CPU starts in halted state for now. Needs to change when
 433        implementing non-kernel boot. */
 434     env->halted = 1;
 435     env->exception_index = EXCP_HLT;
 436 }
 437
 438 static void ppce500_cpu_reset(void *opaque)
 439 {
 440     PowerPCCPU *cpu = opaque;
 441     CPUPPCState *env = &cpu->env;
 442     struct boot_info *bi = env->load_info;
 443
 444     cpu_reset(CPU(cpu));
 445
 446     /* Set initial guest state. */
 447     env->halted = 0;
 448     env->gpr[1] = (16<<20) - 8;
 449     env->gpr[3] = bi->dt_base;
 450     env->nip = bi->entry;
 451     mmubooke_create_initial_mapping(env);
 452 }
 453
 454 void ppce500_init(PPCE500Params *params)
 455 {
 456     MemoryRegion *address_space_mem = get_system_memory();
 457     MemoryRegion *ram = g_new(MemoryRegion, 1);
 458     PCIBus *pci_bus;
 459     CPUPPCState *env = NULL;
 460     uint64_t elf_entry;
 461     uint64_t elf_lowaddr;
 462     hwaddr entry=0;
 463     hwaddr loadaddr=UIMAGE_LOAD_BASE;
 464     target_long kernel_size=0;
 465     target_ulong dt_base = 0;
 466     target_ulong initrd_base = 0;
 467     target_long initrd_size = 0;
 468     target_ulong cur_base = 0;
 469     int i = 0, j, k;
 470     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 471     qemu_irq **irqs, *mpic;
 472     DeviceState *dev;
 473     CPUPPCState *firstenv = NULL;
 474     MemoryRegion *ccsr_addr_space;
 475     SysBusDevice *s;
 476     PPCE500CCSRState *ccsr;
 477
 478     /* Setup CPUs */
 479     if (params->cpu_model == NULL) {
 480         params->cpu_model = "e500v2_v30";
 481     }
 482
 483     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 484     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 485     for (i = 0; i < smp_cpus; i++) {
 486         PowerPCCPU *cpu;
 487         CPUState *cs;
 488         qemu_irq *input;
 489
 490         cpu = cpu_ppc_init(params->cpu_model);
 491         if (cpu == NULL) {
 492             fprintf(stderr, "Unable to initialize CPU!\n");
 493             exit(1);
 494         }
 495         env = &cpu->env;
 496         cs = CPU(cpu);
 497
 498         if (!firstenv) {
 499             firstenv = env;
 500         }
 501
 502         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 503         input = (qemu_irq *)env->irq_inputs;
 504         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 505         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 506         env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i;
 507         env->mpic_iack = MPC8544_CCSRBAR_BASE +
 508                          MPC8544_MPIC_REGS_OFFSET + 0x200A0;
 509
 510         ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
 511
 512         /* Register reset handler */
 513         if (!i) {
 514             /* Primary CPU */
 515             struct boot_info *boot_info;
 516             boot_info = g_malloc0(sizeof(struct boot_info));
 517             qemu_register_reset(ppce500_cpu_reset, cpu);
 518             env->load_info = boot_info;
 519         } else {
 520             /* Secondary CPUs */
 521             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
 522         }
 523     }
 524
 525     env = firstenv;
 526
 527     /* Fixup Memory size on a alignment boundary */
 528     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 529
 530     /* Register Memory */
 531     memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
 532     vmstate_register_ram_global(ram);
 533     memory_region_add_subregion(address_space_mem, 0, ram);
 534
 535     dev = qdev_create(NULL, "e500-ccsr");
 536     object_property_add_child(qdev_get_machine(), "e500-ccsr",
 537                               OBJECT(dev), NULL);
 538     qdev_init_nofail(dev);
 539     ccsr = CCSR(dev);
 540     ccsr_addr_space = &ccsr->ccsr_space;
 541     memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
 542                                 ccsr_addr_space);
 543
 544     /* MPIC */
 545     mpic = g_new(qemu_irq, 256);
 546     dev = qdev_create(NULL, "openpic");
 547     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
 548     qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20);
 549     qdev_init_nofail(dev);
 550     s = SYS_BUS_DEVICE(dev);
 551
 552     k = 0;
 553     for (i = 0; i < smp_cpus; i++) {
 554         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
 555             sysbus_connect_irq(s, k++, irqs[i][j]);
 556         }
 557     }
 558
 559     for (i = 0; i < 256; i++) {
 560         mpic[i] = qdev_get_gpio_in(dev, i);
 561     }
 562
 563     memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
 564                                 s->mmio[0].memory);
 565
 566     /* Serial */
 567     if (serial_hds[0]) {
 568         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
 569                        0, mpic[42], 399193,
 570                        serial_hds[0], DEVICE_BIG_ENDIAN);
 571     }
 572
 573     if (serial_hds[1]) {
 574         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
 575                        0, mpic[42], 399193,
 576                        serial_hds[1], DEVICE_BIG_ENDIAN);
 577     }
 578
 579     /* General Utility device */
 580     dev = qdev_create(NULL, "mpc8544-guts");
 581     qdev_init_nofail(dev);
 582     s = SYS_BUS_DEVICE(dev);
 583     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
 584                                 sysbus_mmio_get_region(s, 0));
 585
 586     /* PCI */
 587     dev = qdev_create(NULL, "e500-pcihost");
 588     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
 589     qdev_init_nofail(dev);
 590     s = SYS_BUS_DEVICE(dev);
 591     sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
 592     sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
 593     sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
 594     sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
 595     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
 596                                 sysbus_mmio_get_region(s, 0));
 597
 598     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 599     if (!pci_bus)
 600         printf("couldn't create PCI controller!\n");
 601
 602     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
 603
 604     if (pci_bus) {
 605         /* Register network interfaces. */
 606         for (i = 0; i < nb_nics; i++) {
 607             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 608         }
 609     }
 610
 611     /* Register spinning region */
 612     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 613
 614     /* Load kernel. */
 615     if (params->kernel_filename) {
 616         kernel_size = load_uimage(params->kernel_filename, &entry,
 617                                   &loadaddr, NULL);
 618         if (kernel_size < 0) {
 619             kernel_size = load_elf(params->kernel_filename, NULL, NULL,
 620                                    &elf_entry, &elf_lowaddr, NULL, 1,
 621                                    ELF_MACHINE, 0);
 622             entry = elf_entry;
 623             loadaddr = elf_lowaddr;
 624         }
 625         /* XXX try again as binary */
 626         if (kernel_size < 0) {
 627             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 628                     params->kernel_filename);
 629             exit(1);
 630         }
 631
 632         cur_base = loadaddr + kernel_size;
 633
 634         /* Reserve space for dtb */
 635         dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 636         cur_base += DTB_MAX_SIZE;
 637     }
 638
 639     /* Load initrd. */
 640     if (params->initrd_filename) {
 641         initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 642         initrd_size = load_image_targphys(params->initrd_filename, initrd_base,
 643                                           ram_size - initrd_base);
 644
 645         if (initrd_size < 0) {
 646             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 647                     params->initrd_filename);
 648             exit(1);
 649         }
 650
 651         cur_base = initrd_base + initrd_size;
 652     }
 653
 654     /* If we're loading a kernel directly, we must load the device tree too. */
 655     if (params->kernel_filename) {
 656         struct boot_info *boot_info;
 657         int dt_size;
 658
 659         dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base,
 660                                            initrd_size);
 661         if (dt_size < 0) {
 662             fprintf(stderr, "couldn't load device tree\n");
 663             exit(1);
 664         }
 665         assert(dt_size < DTB_MAX_SIZE);
 666
 667         boot_info = env->load_info;
 668         boot_info->entry = entry;
 669         boot_info->dt_base = dt_base;
 670         boot_info->dt_size = dt_size;
 671     }
 672
 673     if (kvm_enabled()) {
 674         kvmppc_init();
 675     }
 676 }
 677
 678 static int e500_ccsr_initfn(SysBusDevice *dev)
 679 {
 680     PPCE500CCSRState *ccsr;
 681
 682     ccsr = CCSR(dev);
 683     memory_region_init(&ccsr->ccsr_space, "e500-ccsr",
 684                        MPC8544_CCSRBAR_SIZE);
 685     return 0;
 686 }
 687
 688 static void e500_ccsr_class_init(ObjectClass *klass, void *data)
 689 {
 690     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 691     k->init = e500_ccsr_initfn;
 692 }
 693
 694 static const TypeInfo e500_ccsr_info = {
 695     .name          = TYPE_CCSR,
 696     .parent        = TYPE_SYS_BUS_DEVICE,
 697     .instance_size = sizeof(PPCE500CCSRState),
 698     .class_init    = e500_ccsr_class_init,
 699 };
 700
 701 static void e500_register_types(void)
 702 {
 703     type_register_static(&e500_ccsr_info);
 704 }
 705
 706 type_init(e500_register_types)