target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_I386_H
  20 #define CPU_I386_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #define CPUArchState struct CPUX86State
  46
  47 #include "exec/cpu-defs.h"
  48
  49 #include "fpu/softfloat.h"
  50
  51 #define R_EAX 0
  52 #define R_ECX 1
  53 #define R_EDX 2
  54 #define R_EBX 3
  55 #define R_ESP 4
  56 #define R_EBP 5
  57 #define R_ESI 6
  58 #define R_EDI 7
  59
  60 #define R_AL 0
  61 #define R_CL 1
  62 #define R_DL 2
  63 #define R_BL 3
  64 #define R_AH 4
  65 #define R_CH 5
  66 #define R_DH 6
  67 #define R_BH 7
  68
  69 #define R_ES 0
  70 #define R_CS 1
  71 #define R_SS 2
  72 #define R_DS 3
  73 #define R_FS 4
  74 #define R_GS 5
  75
  76 /* segment descriptor fields */
  77 #define DESC_G_MASK     (1 << 23)
  78 #define DESC_B_SHIFT    22
  79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  82 #define DESC_AVL_MASK   (1 << 20)
  83 #define DESC_P_MASK     (1 << 15)
  84 #define DESC_DPL_SHIFT  13
  85 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
  86 #define DESC_S_MASK     (1 << 12)
  87 #define DESC_TYPE_SHIFT 8
  88 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
  89 #define DESC_A_MASK     (1 << 8)
  90
  91 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  92 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  93 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  94
  95 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  96 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  97
  98 #define DESC_TSS_BUSY_MASK (1 << 9)
  99
 100 /* eflags masks */
 101 #define CC_C    0x0001
 102 #define CC_P    0x0004
 103 #define CC_A    0x0010
 104 #define CC_Z    0x0040
 105 #define CC_S    0x0080
 106 #define CC_O    0x0800
 107
 108 #define TF_SHIFT   8
 109 #define IOPL_SHIFT 12
 110 #define VM_SHIFT   17
 111
 112 #define TF_MASK                 0x00000100
 113 #define IF_MASK                 0x00000200
 114 #define DF_MASK                 0x00000400
 115 #define IOPL_MASK               0x00003000
 116 #define NT_MASK                 0x00004000
 117 #define RF_MASK                 0x00010000
 118 #define VM_MASK                 0x00020000
 119 #define AC_MASK                 0x00040000
 120 #define VIF_MASK                0x00080000
 121 #define VIP_MASK                0x00100000
 122 #define ID_MASK                 0x00200000
 123
 124 /* hidden flags - used internally by qemu to represent additional cpu
 125    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 126    redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK
 127    bit positions to ease oring with eflags. */
 128 /* current cpl */
 129 #define HF_CPL_SHIFT         0
 130 /* true if soft mmu is being used */
 131 #define HF_SOFTMMU_SHIFT     2
 132 /* true if hardware interrupts must be disabled for next instruction */
 133 #define HF_INHIBIT_IRQ_SHIFT 3
 134 /* 16 or 32 segments */
 135 #define HF_CS32_SHIFT        4
 136 #define HF_SS32_SHIFT        5
 137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 138 #define HF_ADDSEG_SHIFT      6
 139 /* copy of CR0.PE (protected mode) */
 140 #define HF_PE_SHIFT          7
 141 #define HF_TF_SHIFT          8 /* must be same as eflags */
 142 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 143 #define HF_EM_SHIFT         10
 144 #define HF_TS_SHIFT         11
 145 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 146 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 147 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 148 #define HF_RF_SHIFT         16 /* must be same as eflags */
 149 #define HF_VM_SHIFT         17 /* must be same as eflags */
 150 #define HF_AC_SHIFT         18 /* must be same as eflags */
 151 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 152 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 153 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 154 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 155 #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
 156
 157 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 158 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 159 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 160 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 161 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 162 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 163 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 164 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 165 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 166 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 167 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 168 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 169 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 170 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 171 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
 172 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 173 #define HF_AC_MASK           (1 << HF_AC_SHIFT)
 174 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 175 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 176 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 177 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 178 #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
 179
 180 /* hflags2 */
 181
 182 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 183 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 184 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 185 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 186
 187 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 188 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 189 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 190 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 191
 192 #define CR0_PE_SHIFT 0
 193 #define CR0_MP_SHIFT 1
 194
 195 #define CR0_PE_MASK  (1 << 0)
 196 #define CR0_MP_MASK  (1 << 1)
 197 #define CR0_EM_MASK  (1 << 2)
 198 #define CR0_TS_MASK  (1 << 3)
 199 #define CR0_ET_MASK  (1 << 4)
 200 #define CR0_NE_MASK  (1 << 5)
 201 #define CR0_WP_MASK  (1 << 16)
 202 #define CR0_AM_MASK  (1 << 18)
 203 #define CR0_PG_MASK  (1 << 31)
 204
 205 #define CR4_VME_MASK  (1 << 0)
 206 #define CR4_PVI_MASK  (1 << 1)
 207 #define CR4_TSD_MASK  (1 << 2)
 208 #define CR4_DE_MASK   (1 << 3)
 209 #define CR4_PSE_MASK  (1 << 4)
 210 #define CR4_PAE_MASK  (1 << 5)
 211 #define CR4_MCE_MASK  (1 << 6)
 212 #define CR4_PGE_MASK  (1 << 7)
 213 #define CR4_PCE_MASK  (1 << 8)
 214 #define CR4_OSFXSR_SHIFT 9
 215 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 216 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 217 #define CR4_VMXE_MASK   (1 << 13)
 218 #define CR4_SMXE_MASK   (1 << 14)
 219 #define CR4_FSGSBASE_MASK (1 << 16)
 220 #define CR4_PCIDE_MASK  (1 << 17)
 221 #define CR4_OSXSAVE_MASK (1 << 18)
 222 #define CR4_SMEP_MASK   (1 << 20)
 223 #define CR4_SMAP_MASK   (1 << 21)
 224
 225 #define DR6_BD          (1 << 13)
 226 #define DR6_BS          (1 << 14)
 227 #define DR6_BT          (1 << 15)
 228 #define DR6_FIXED_1     0xffff0ff0
 229
 230 #define DR7_GD          (1 << 13)
 231 #define DR7_TYPE_SHIFT  16
 232 #define DR7_LEN_SHIFT   18
 233 #define DR7_FIXED_1     0x00000400
 234 #define DR7_LOCAL_BP_MASK    0x55
 235 #define DR7_MAX_BP           4
 236 #define DR7_TYPE_BP_INST     0x0
 237 #define DR7_TYPE_DATA_WR     0x1
 238 #define DR7_TYPE_IO_RW       0x2
 239 #define DR7_TYPE_DATA_RW     0x3
 240
 241 #define PG_PRESENT_BIT  0
 242 #define PG_RW_BIT       1
 243 #define PG_USER_BIT     2
 244 #define PG_PWT_BIT      3
 245 #define PG_PCD_BIT      4
 246 #define PG_ACCESSED_BIT 5
 247 #define PG_DIRTY_BIT    6
 248 #define PG_PSE_BIT      7
 249 #define PG_GLOBAL_BIT   8
 250 #define PG_NX_BIT       63
 251
 252 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 253 #define PG_RW_MASK       (1 << PG_RW_BIT)
 254 #define PG_USER_MASK     (1 << PG_USER_BIT)
 255 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 256 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 257 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 258 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 259 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 260 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 261 #define PG_HI_USER_MASK  0x7ff0000000000000LL
 262 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 263
 264 #define PG_ERROR_W_BIT     1
 265
 266 #define PG_ERROR_P_MASK    0x01
 267 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 268 #define PG_ERROR_U_MASK    0x04
 269 #define PG_ERROR_RSVD_MASK 0x08
 270 #define PG_ERROR_I_D_MASK  0x10
 271
 272 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
 273 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
 274
 275 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
 276 #define MCE_BANKS_DEF   10
 277
 278 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
 279 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
 280 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
 281
 282 #define MCI_STATUS_VAL  (1ULL<<63)  /* valid error */
 283 #define MCI_STATUS_OVER (1ULL<<62)  /* previous errors lost */
 284 #define MCI_STATUS_UC   (1ULL<<61)  /* uncorrected error */
 285 #define MCI_STATUS_EN   (1ULL<<60)  /* error enabled */
 286 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
 287 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
 288 #define MCI_STATUS_PCC  (1ULL<<57)  /* processor context corrupt */
 289 #define MCI_STATUS_S    (1ULL<<56)  /* Signaled machine check */
 290 #define MCI_STATUS_AR   (1ULL<<55)  /* Action required */
 291
 292 /* MISC register defines */
 293 #define MCM_ADDR_SEGOFF 0       /* segment offset */
 294 #define MCM_ADDR_LINEAR 1       /* linear address */
 295 #define MCM_ADDR_PHYS   2       /* physical address */
 296 #define MCM_ADDR_MEM    3       /* memory address */
 297 #define MCM_ADDR_GENERIC 7      /* generic */
 298
 299 #define MSR_IA32_TSC                    0x10
 300 #define MSR_IA32_APICBASE               0x1b
 301 #define MSR_IA32_APICBASE_BSP           (1<<8)
 302 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 303 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 304 #define MSR_TSC_ADJUST                  0x0000003b
 305 #define MSR_IA32_TSCDEADLINE            0x6e0
 306
 307 #define MSR_MTRRcap                     0xfe
 308 #define MSR_MTRRcap_VCNT                8
 309 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 310 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 311
 312 #define MSR_IA32_SYSENTER_CS            0x174
 313 #define MSR_IA32_SYSENTER_ESP           0x175
 314 #define MSR_IA32_SYSENTER_EIP           0x176
 315
 316 #define MSR_MCG_CAP                     0x179
 317 #define MSR_MCG_STATUS                  0x17a
 318 #define MSR_MCG_CTL                     0x17b
 319
 320 #define MSR_IA32_PERF_STATUS            0x198
 321
 322 #define MSR_IA32_MISC_ENABLE            0x1a0
 323 /* Indicates good rep/movs microcode on some processors: */
 324 #define MSR_IA32_MISC_ENABLE_DEFAULT    1
 325
 326 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 327 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 328
 329 #define MSR_MTRRfix64K_00000            0x250
 330 #define MSR_MTRRfix16K_80000            0x258
 331 #define MSR_MTRRfix16K_A0000            0x259
 332 #define MSR_MTRRfix4K_C0000             0x268
 333 #define MSR_MTRRfix4K_C8000             0x269
 334 #define MSR_MTRRfix4K_D0000             0x26a
 335 #define MSR_MTRRfix4K_D8000             0x26b
 336 #define MSR_MTRRfix4K_E0000             0x26c
 337 #define MSR_MTRRfix4K_E8000             0x26d
 338 #define MSR_MTRRfix4K_F0000             0x26e
 339 #define MSR_MTRRfix4K_F8000             0x26f
 340
 341 #define MSR_PAT                         0x277
 342
 343 #define MSR_MTRRdefType                 0x2ff
 344
 345 #define MSR_MC0_CTL                     0x400
 346 #define MSR_MC0_STATUS                  0x401
 347 #define MSR_MC0_ADDR                    0x402
 348 #define MSR_MC0_MISC                    0x403
 349
 350 #define MSR_EFER                        0xc0000080
 351
 352 #define MSR_EFER_SCE   (1 << 0)
 353 #define MSR_EFER_LME   (1 << 8)
 354 #define MSR_EFER_LMA   (1 << 10)
 355 #define MSR_EFER_NXE   (1 << 11)
 356 #define MSR_EFER_SVME  (1 << 12)
 357 #define MSR_EFER_FFXSR (1 << 14)
 358
 359 #define MSR_STAR                        0xc0000081
 360 #define MSR_LSTAR                       0xc0000082
 361 #define MSR_CSTAR                       0xc0000083
 362 #define MSR_FMASK                       0xc0000084
 363 #define MSR_FSBASE                      0xc0000100
 364 #define MSR_GSBASE                      0xc0000101
 365 #define MSR_KERNELGSBASE                0xc0000102
 366 #define MSR_TSC_AUX                     0xc0000103
 367
 368 #define MSR_VM_HSAVE_PA                 0xc0010117
 369
 370 /* CPUID feature words */
 371 typedef enum FeatureWord {
 372     FEAT_1_EDX,         /* CPUID[1].EDX */
 373     FEAT_1_ECX,         /* CPUID[1].ECX */
 374     FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
 375     FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
 376     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
 377     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
 378     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
 379     FEAT_SVM,           /* CPUID[8000_000A].EDX */
 380     FEATURE_WORDS,
 381 } FeatureWord;
 382
 383 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 384
 385 /* cpuid_features bits */
 386 #define CPUID_FP87 (1 << 0)
 387 #define CPUID_VME  (1 << 1)
 388 #define CPUID_DE   (1 << 2)
 389 #define CPUID_PSE  (1 << 3)
 390 #define CPUID_TSC  (1 << 4)
 391 #define CPUID_MSR  (1 << 5)
 392 #define CPUID_PAE  (1 << 6)
 393 #define CPUID_MCE  (1 << 7)
 394 #define CPUID_CX8  (1 << 8)
 395 #define CPUID_APIC (1 << 9)
 396 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 397 #define CPUID_MTRR (1 << 12)
 398 #define CPUID_PGE  (1 << 13)
 399 #define CPUID_MCA  (1 << 14)
 400 #define CPUID_CMOV (1 << 15)
 401 #define CPUID_PAT  (1 << 16)
 402 #define CPUID_PSE36   (1 << 17)
 403 #define CPUID_PN   (1 << 18)
 404 #define CPUID_CLFLUSH (1 << 19)
 405 #define CPUID_DTS (1 << 21)
 406 #define CPUID_ACPI (1 << 22)
 407 #define CPUID_MMX  (1 << 23)
 408 #define CPUID_FXSR (1 << 24)
 409 #define CPUID_SSE  (1 << 25)
 410 #define CPUID_SSE2 (1 << 26)
 411 #define CPUID_SS (1 << 27)
 412 #define CPUID_HT (1 << 28)
 413 #define CPUID_TM (1 << 29)
 414 #define CPUID_IA64 (1 << 30)
 415 #define CPUID_PBE (1 << 31)
 416
 417 #define CPUID_EXT_SSE3     (1 << 0)
 418 #define CPUID_EXT_PCLMULQDQ (1 << 1)
 419 #define CPUID_EXT_DTES64   (1 << 2)
 420 #define CPUID_EXT_MONITOR  (1 << 3)
 421 #define CPUID_EXT_DSCPL    (1 << 4)
 422 #define CPUID_EXT_VMX      (1 << 5)
 423 #define CPUID_EXT_SMX      (1 << 6)
 424 #define CPUID_EXT_EST      (1 << 7)
 425 #define CPUID_EXT_TM2      (1 << 8)
 426 #define CPUID_EXT_SSSE3    (1 << 9)
 427 #define CPUID_EXT_CID      (1 << 10)
 428 #define CPUID_EXT_FMA      (1 << 12)
 429 #define CPUID_EXT_CX16     (1 << 13)
 430 #define CPUID_EXT_XTPR     (1 << 14)
 431 #define CPUID_EXT_PDCM     (1 << 15)
 432 #define CPUID_EXT_PCID     (1 << 17)
 433 #define CPUID_EXT_DCA      (1 << 18)
 434 #define CPUID_EXT_SSE41    (1 << 19)
 435 #define CPUID_EXT_SSE42    (1 << 20)
 436 #define CPUID_EXT_X2APIC   (1 << 21)
 437 #define CPUID_EXT_MOVBE    (1 << 22)
 438 #define CPUID_EXT_POPCNT   (1 << 23)
 439 #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
 440 #define CPUID_EXT_AES      (1 << 25)
 441 #define CPUID_EXT_XSAVE    (1 << 26)
 442 #define CPUID_EXT_OSXSAVE  (1 << 27)
 443 #define CPUID_EXT_AVX      (1 << 28)
 444 #define CPUID_EXT_F16C     (1 << 29)
 445 #define CPUID_EXT_RDRAND   (1 << 30)
 446 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 447
 448 #define CPUID_EXT2_FPU     (1 << 0)
 449 #define CPUID_EXT2_VME     (1 << 1)
 450 #define CPUID_EXT2_DE      (1 << 2)
 451 #define CPUID_EXT2_PSE     (1 << 3)
 452 #define CPUID_EXT2_TSC     (1 << 4)
 453 #define CPUID_EXT2_MSR     (1 << 5)
 454 #define CPUID_EXT2_PAE     (1 << 6)
 455 #define CPUID_EXT2_MCE     (1 << 7)
 456 #define CPUID_EXT2_CX8     (1 << 8)
 457 #define CPUID_EXT2_APIC    (1 << 9)
 458 #define CPUID_EXT2_SYSCALL (1 << 11)
 459 #define CPUID_EXT2_MTRR    (1 << 12)
 460 #define CPUID_EXT2_PGE     (1 << 13)
 461 #define CPUID_EXT2_MCA     (1 << 14)
 462 #define CPUID_EXT2_CMOV    (1 << 15)
 463 #define CPUID_EXT2_PAT     (1 << 16)
 464 #define CPUID_EXT2_PSE36   (1 << 17)
 465 #define CPUID_EXT2_MP      (1 << 19)
 466 #define CPUID_EXT2_NX      (1 << 20)
 467 #define CPUID_EXT2_MMXEXT  (1 << 22)
 468 #define CPUID_EXT2_MMX     (1 << 23)
 469 #define CPUID_EXT2_FXSR    (1 << 24)
 470 #define CPUID_EXT2_FFXSR   (1 << 25)
 471 #define CPUID_EXT2_PDPE1GB (1 << 26)
 472 #define CPUID_EXT2_RDTSCP  (1 << 27)
 473 #define CPUID_EXT2_LM      (1 << 29)
 474 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 475 #define CPUID_EXT2_3DNOW   (1 << 31)
 476
 477 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
 478 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
 479                                 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
 480                                 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
 481                                 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
 482                                 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
 483                                 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
 484                                 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
 485                                 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
 486                                 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
 487
 488 #define CPUID_EXT3_LAHF_LM (1 << 0)
 489 #define CPUID_EXT3_CMP_LEG (1 << 1)
 490 #define CPUID_EXT3_SVM     (1 << 2)
 491 #define CPUID_EXT3_EXTAPIC (1 << 3)
 492 #define CPUID_EXT3_CR8LEG  (1 << 4)
 493 #define CPUID_EXT3_ABM     (1 << 5)
 494 #define CPUID_EXT3_SSE4A   (1 << 6)
 495 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 496 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 497 #define CPUID_EXT3_OSVW    (1 << 9)
 498 #define CPUID_EXT3_IBS     (1 << 10)
 499 #define CPUID_EXT3_XOP     (1 << 11)
 500 #define CPUID_EXT3_SKINIT  (1 << 12)
 501 #define CPUID_EXT3_WDT     (1 << 13)
 502 #define CPUID_EXT3_LWP     (1 << 15)
 503 #define CPUID_EXT3_FMA4    (1 << 16)
 504 #define CPUID_EXT3_TCE     (1 << 17)
 505 #define CPUID_EXT3_NODEID  (1 << 19)
 506 #define CPUID_EXT3_TBM     (1 << 21)
 507 #define CPUID_EXT3_TOPOEXT (1 << 22)
 508 #define CPUID_EXT3_PERFCORE (1 << 23)
 509 #define CPUID_EXT3_PERFNB  (1 << 24)
 510
 511 #define CPUID_SVM_NPT          (1 << 0)
 512 #define CPUID_SVM_LBRV         (1 << 1)
 513 #define CPUID_SVM_SVMLOCK      (1 << 2)
 514 #define CPUID_SVM_NRIPSAVE     (1 << 3)
 515 #define CPUID_SVM_TSCSCALE     (1 << 4)
 516 #define CPUID_SVM_VMCBCLEAN    (1 << 5)
 517 #define CPUID_SVM_FLUSHASID    (1 << 6)
 518 #define CPUID_SVM_DECODEASSIST (1 << 7)
 519 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 520 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 521
 522 #define CPUID_7_0_EBX_FSGSBASE (1 << 0)
 523 #define CPUID_7_0_EBX_BMI1     (1 << 3)
 524 #define CPUID_7_0_EBX_HLE      (1 << 4)
 525 #define CPUID_7_0_EBX_AVX2     (1 << 5)
 526 #define CPUID_7_0_EBX_SMEP     (1 << 7)
 527 #define CPUID_7_0_EBX_BMI2     (1 << 8)
 528 #define CPUID_7_0_EBX_ERMS     (1 << 9)
 529 #define CPUID_7_0_EBX_INVPCID  (1 << 10)
 530 #define CPUID_7_0_EBX_RTM      (1 << 11)
 531 #define CPUID_7_0_EBX_RDSEED   (1 << 18)
 532 #define CPUID_7_0_EBX_ADX      (1 << 19)
 533 #define CPUID_7_0_EBX_SMAP     (1 << 20)
 534
 535 #define CPUID_VENDOR_SZ      12
 536
 537 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 538 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 539 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 540 #define CPUID_VENDOR_INTEL "GenuineIntel"
 541
 542 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 543 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 544 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 545 #define CPUID_VENDOR_AMD   "AuthenticAMD"
 546
 547 #define CPUID_VENDOR_VIA   "CentaurHauls"
 548
 549 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 550 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 551
 552 #define EXCP00_DIVZ     0
 553 #define EXCP01_DB       1
 554 #define EXCP02_NMI      2
 555 #define EXCP03_INT3     3
 556 #define EXCP04_INTO     4
 557 #define EXCP05_BOUND    5
 558 #define EXCP06_ILLOP    6
 559 #define EXCP07_PREX     7
 560 #define EXCP08_DBLE     8
 561 #define EXCP09_XERR     9
 562 #define EXCP0A_TSS      10
 563 #define EXCP0B_NOSEG    11
 564 #define EXCP0C_STACK    12
 565 #define EXCP0D_GPF      13
 566 #define EXCP0E_PAGE     14
 567 #define EXCP10_COPR     16
 568 #define EXCP11_ALGN     17
 569 #define EXCP12_MCHK     18
 570
 571 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 572                                  for syscall instruction */
 573
 574 /* i386-specific interrupt pending bits.  */
 575 #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
 576 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
 577 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 578 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
 579 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
 580 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1
 581 #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_2
 582 #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_3
 583
 584
 585 enum {
 586     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 587     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 588
 589     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 590     CC_OP_MULW,
 591     CC_OP_MULL,
 592     CC_OP_MULQ,
 593
 594     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 595     CC_OP_ADDW,
 596     CC_OP_ADDL,
 597     CC_OP_ADDQ,
 598
 599     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 600     CC_OP_ADCW,
 601     CC_OP_ADCL,
 602     CC_OP_ADCQ,
 603
 604     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 605     CC_OP_SUBW,
 606     CC_OP_SUBL,
 607     CC_OP_SUBQ,
 608
 609     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 610     CC_OP_SBBW,
 611     CC_OP_SBBL,
 612     CC_OP_SBBQ,
 613
 614     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 615     CC_OP_LOGICW,
 616     CC_OP_LOGICL,
 617     CC_OP_LOGICQ,
 618
 619     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 620     CC_OP_INCW,
 621     CC_OP_INCL,
 622     CC_OP_INCQ,
 623
 624     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 625     CC_OP_DECW,
 626     CC_OP_DECL,
 627     CC_OP_DECQ,
 628
 629     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 630     CC_OP_SHLW,
 631     CC_OP_SHLL,
 632     CC_OP_SHLQ,
 633
 634     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 635     CC_OP_SARW,
 636     CC_OP_SARL,
 637     CC_OP_SARQ,
 638
 639     CC_OP_NB,
 640 };
 641
 642 typedef struct SegmentCache {
 643     uint32_t selector;
 644     target_ulong base;
 645     uint32_t limit;
 646     uint32_t flags;
 647 } SegmentCache;
 648
 649 typedef union {
 650     uint8_t _b[16];
 651     uint16_t _w[8];
 652     uint32_t _l[4];
 653     uint64_t _q[2];
 654     float32 _s[4];
 655     float64 _d[2];
 656 } XMMReg;
 657
 658 typedef union {
 659     uint8_t _b[8];
 660     uint16_t _w[4];
 661     uint32_t _l[2];
 662     float32 _s[2];
 663     uint64_t q;
 664 } MMXReg;
 665
 666 #ifdef HOST_WORDS_BIGENDIAN
 667 #define XMM_B(n) _b[15 - (n)]
 668 #define XMM_W(n) _w[7 - (n)]
 669 #define XMM_L(n) _l[3 - (n)]
 670 #define XMM_S(n) _s[3 - (n)]
 671 #define XMM_Q(n) _q[1 - (n)]
 672 #define XMM_D(n) _d[1 - (n)]
 673
 674 #define MMX_B(n) _b[7 - (n)]
 675 #define MMX_W(n) _w[3 - (n)]
 676 #define MMX_L(n) _l[1 - (n)]
 677 #define MMX_S(n) _s[1 - (n)]
 678 #else
 679 #define XMM_B(n) _b[n]
 680 #define XMM_W(n) _w[n]
 681 #define XMM_L(n) _l[n]
 682 #define XMM_S(n) _s[n]
 683 #define XMM_Q(n) _q[n]
 684 #define XMM_D(n) _d[n]
 685
 686 #define MMX_B(n) _b[n]
 687 #define MMX_W(n) _w[n]
 688 #define MMX_L(n) _l[n]
 689 #define MMX_S(n) _s[n]
 690 #endif
 691 #define MMX_Q(n) q
 692
 693 typedef union {
 694     floatx80 d __attribute__((aligned(16)));
 695     MMXReg mmx;
 696 } FPReg;
 697
 698 typedef struct {
 699     uint64_t base;
 700     uint64_t mask;
 701 } MTRRVar;
 702
 703 #define CPU_NB_REGS64 16
 704 #define CPU_NB_REGS32 8
 705
 706 #ifdef TARGET_X86_64
 707 #define CPU_NB_REGS CPU_NB_REGS64
 708 #else
 709 #define CPU_NB_REGS CPU_NB_REGS32
 710 #endif
 711
 712 #define NB_MMU_MODES 3
 713
 714 typedef enum TPRAccess {
 715     TPR_ACCESS_READ,
 716     TPR_ACCESS_WRITE,
 717 } TPRAccess;
 718
 719 typedef struct CPUX86State {
 720     /* standard registers */
 721     target_ulong regs[CPU_NB_REGS];
 722     target_ulong eip;
 723     target_ulong eflags; /* eflags register. During CPU emulation, CC
 724                         flags and DF are set to zero because they are
 725                         stored elsewhere */
 726
 727     /* emulator internal eflags handling */
 728     target_ulong cc_src;
 729     target_ulong cc_dst;
 730     uint32_t cc_op;
 731     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 732     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 733                         are known at translation time. */
 734     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 735
 736     /* segments */
 737     SegmentCache segs[6]; /* selector values */
 738     SegmentCache ldt;
 739     SegmentCache tr;
 740     SegmentCache gdt; /* only base and limit are used */
 741     SegmentCache idt; /* only base and limit are used */
 742
 743     target_ulong cr[5]; /* NOTE: cr1 is unused */
 744     int32_t a20_mask;
 745
 746     /* FPU state */
 747     unsigned int fpstt; /* top of stack index */
 748     uint16_t fpus;
 749     uint16_t fpuc;
 750     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 751     FPReg fpregs[8];
 752     /* KVM-only so far */
 753     uint16_t fpop;
 754     uint64_t fpip;
 755     uint64_t fpdp;
 756
 757     /* emulator internal variables */
 758     float_status fp_status;
 759     floatx80 ft0;
 760
 761     float_status mmx_status; /* for 3DNow! float ops */
 762     float_status sse_status;
 763     uint32_t mxcsr;
 764     XMMReg xmm_regs[CPU_NB_REGS];
 765     XMMReg xmm_t0;
 766     MMXReg mmx_t0;
 767     target_ulong cc_tmp; /* temporary for rcr/rcl */
 768
 769     /* sysenter registers */
 770     uint32_t sysenter_cs;
 771     target_ulong sysenter_esp;
 772     target_ulong sysenter_eip;
 773     uint64_t efer;
 774     uint64_t star;
 775
 776     uint64_t vm_hsave;
 777     uint64_t vm_vmcb;
 778     uint64_t tsc_offset;
 779     uint64_t intercept;
 780     uint16_t intercept_cr_read;
 781     uint16_t intercept_cr_write;
 782     uint16_t intercept_dr_read;
 783     uint16_t intercept_dr_write;
 784     uint32_t intercept_exceptions;
 785     uint8_t v_tpr;
 786
 787 #ifdef TARGET_X86_64
 788     target_ulong lstar;
 789     target_ulong cstar;
 790     target_ulong fmask;
 791     target_ulong kernelgsbase;
 792 #endif
 793     uint64_t system_time_msr;
 794     uint64_t wall_clock_msr;
 795     uint64_t async_pf_en_msr;
 796     uint64_t pv_eoi_en_msr;
 797
 798     uint64_t tsc;
 799     uint64_t tsc_adjust;
 800     uint64_t tsc_deadline;
 801
 802     uint64_t mcg_status;
 803     uint64_t msr_ia32_misc_enable;
 804
 805     /* exception/interrupt handling */
 806     int error_code;
 807     int exception_is_int;
 808     target_ulong exception_next_eip;
 809     target_ulong dr[8]; /* debug registers */
 810     union {
 811         CPUBreakpoint *cpu_breakpoint[4];
 812         CPUWatchpoint *cpu_watchpoint[4];
 813     }; /* break/watchpoints for dr[0..3] */
 814     uint32_t smbase;
 815     int old_exception;  /* exception in flight */
 816
 817     /* KVM states, automatically cleared on reset */
 818     uint8_t nmi_injected;
 819     uint8_t nmi_pending;
 820
 821     CPU_COMMON
 822
 823     uint64_t pat;
 824
 825     /* processor features (e.g. for CPUID insn) */
 826     uint32_t cpuid_level;
 827     uint32_t cpuid_vendor1;
 828     uint32_t cpuid_vendor2;
 829     uint32_t cpuid_vendor3;
 830     uint32_t cpuid_version;
 831     uint32_t cpuid_features;
 832     uint32_t cpuid_ext_features;
 833     uint32_t cpuid_xlevel;
 834     uint32_t cpuid_model[12];
 835     uint32_t cpuid_ext2_features;
 836     uint32_t cpuid_ext3_features;
 837     uint32_t cpuid_apic_id;
 838     /* Store the results of Centaur's CPUID instructions */
 839     uint32_t cpuid_xlevel2;
 840     uint32_t cpuid_ext4_features;
 841     /* Flags from CPUID[EAX=7,ECX=0].EBX */
 842     uint32_t cpuid_7_0_ebx_features;
 843
 844     /* MTRRs */
 845     uint64_t mtrr_fixed[11];
 846     uint64_t mtrr_deftype;
 847     MTRRVar mtrr_var[8];
 848
 849     /* For KVM */
 850     uint32_t mp_state;
 851     int32_t exception_injected;
 852     int32_t interrupt_injected;
 853     uint8_t soft_interrupt;
 854     uint8_t has_error_code;
 855     uint32_t sipi_vector;
 856     uint32_t cpuid_kvm_features;
 857     uint32_t cpuid_svm_features;
 858     bool tsc_valid;
 859     int tsc_khz;
 860     void *kvm_xsave_buf;
 861
 862     /* in order to simplify APIC support, we leave this pointer to the
 863        user */
 864     struct DeviceState *apic_state;
 865
 866     uint64_t mcg_cap;
 867     uint64_t mcg_ctl;
 868     uint64_t mce_banks[MCE_BANKS_DEF*4];
 869
 870     uint64_t tsc_aux;
 871
 872     /* vmstate */
 873     uint16_t fpus_vmstate;
 874     uint16_t fptag_vmstate;
 875     uint16_t fpregs_format_vmstate;
 876
 877     uint64_t xstate_bv;
 878     XMMReg ymmh_regs[CPU_NB_REGS];
 879
 880     uint64_t xcr0;
 881
 882     TPRAccess tpr_access_type;
 883 } CPUX86State;
 884
 885 #include "cpu-qom.h"
 886
 887 X86CPU *cpu_x86_init(const char *cpu_model);
 888 int cpu_x86_exec(CPUX86State *s);
 889 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 890 void x86_cpudef_setup(void);
 891 int cpu_x86_support_mca_broadcast(CPUX86State *env);
 892
 893 int cpu_get_pic_interrupt(CPUX86State *s);
 894 /* MSDOS compatibility mode FPU exception support */
 895 void cpu_set_ferr(CPUX86State *s);
 896
 897 /* this function must always be used to load data in the segment
 898    cache: it synchronizes the hflags with the segment cache values */
 899 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 900                                           int seg_reg, unsigned int selector,
 901                                           target_ulong base,
 902                                           unsigned int limit,
 903                                           unsigned int flags)
 904 {
 905     SegmentCache *sc;
 906     unsigned int new_hflags;
 907
 908     sc = &env->segs[seg_reg];
 909     sc->selector = selector;
 910     sc->base = base;
 911     sc->limit = limit;
 912     sc->flags = flags;
 913
 914     /* update the hidden flags */
 915     {
 916         if (seg_reg == R_CS) {
 917 #ifdef TARGET_X86_64
 918             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 919                 /* long mode */
 920                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 921                 env->hflags &= ~(HF_ADDSEG_MASK);
 922             } else
 923 #endif
 924             {
 925                 /* legacy / compatibility case */
 926                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 927                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 928                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 929                     new_hflags;
 930             }
 931         }
 932         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 933             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 934         if (env->hflags & HF_CS64_MASK) {
 935             /* zero base assumed for DS, ES and SS in long mode */
 936         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 937                    (env->eflags & VM_MASK) ||
 938                    !(env->hflags & HF_CS32_MASK)) {
 939             /* XXX: try to avoid this test. The problem comes from the
 940                fact that is real mode or vm86 mode we only modify the
 941                'base' and 'selector' fields of the segment cache to go
 942                faster. A solution may be to force addseg to one in
 943                translate-i386.c. */
 944             new_hflags |= HF_ADDSEG_MASK;
 945         } else {
 946             new_hflags |= ((env->segs[R_DS].base |
 947                             env->segs[R_ES].base |
 948                             env->segs[R_SS].base) != 0) <<
 949                 HF_ADDSEG_SHIFT;
 950         }
 951         env->hflags = (env->hflags &
 952                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 953     }
 954 }
 955
 956 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
 957                                                int sipi_vector)
 958 {
 959     CPUX86State *env = &cpu->env;
 960
 961     env->eip = 0;
 962     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
 963                            sipi_vector << 12,
 964                            env->segs[R_CS].limit,
 965                            env->segs[R_CS].flags);
 966     env->halted = 0;
 967 }
 968
 969 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
 970                             target_ulong *base, unsigned int *limit,
 971                             unsigned int *flags);
 972
 973 /* wrapper, just in case memory mappings must be changed */
 974 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 975 {
 976 #if HF_CPL_MASK == 3
 977     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 978 #else
 979 #error HF_CPL_MASK is hardcoded
 980 #endif
 981 }
 982
 983 /* op_helper.c */
 984 /* used for debug or cpu save/restore */
 985 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
 986 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
 987
 988 /* cpu-exec.c */
 989 /* the following helpers are only usable in user mode simulation as
 990    they can trigger unexpected exceptions */
 991 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 992 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 993 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 994
 995 /* you can call this signal handler from your SIGBUS and SIGSEGV
 996    signal handlers to inform the virtual CPU of exceptions. non zero
 997    is returned if the signal was handled by the virtual CPU.  */
 998 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 999                            void *puc);
1000
1001 /* cpuid.c */
1002 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1003                    uint32_t *eax, uint32_t *ebx,
1004                    uint32_t *ecx, uint32_t *edx);
1005 int cpu_x86_register(X86CPU *cpu, const char *cpu_model);
1006 void cpu_clear_apic_feature(CPUX86State *env);
1007 void host_cpuid(uint32_t function, uint32_t count,
1008                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1009
1010 /* helper.c */
1011 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
1012                              int is_write, int mmu_idx);
1013 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
1014 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1015
1016 static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
1017 {
1018     return (dr7 >> (index * 2)) & 1;
1019 }
1020
1021 static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
1022 {
1023     return (dr7 >> (index * 2)) & 2;
1024
1025 }
1026 static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
1027 {
1028     return hw_global_breakpoint_enabled(dr7, index) ||
1029            hw_local_breakpoint_enabled(dr7, index);
1030 }
1031
1032 static inline int hw_breakpoint_type(unsigned long dr7, int index)
1033 {
1034     return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
1035 }
1036
1037 static inline int hw_breakpoint_len(unsigned long dr7, int index)
1038 {
1039     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
1040     return (len == 2) ? 8 : len + 1;
1041 }
1042
1043 void hw_breakpoint_insert(CPUX86State *env, int index);
1044 void hw_breakpoint_remove(CPUX86State *env, int index);
1045 bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
1046 void breakpoint_handler(CPUX86State *env);
1047
1048 /* will be suppressed */
1049 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1050 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1051 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1052
1053 /* hw/pc.c */
1054 void cpu_smm_update(CPUX86State *env);
1055 uint64_t cpu_get_tsc(CPUX86State *env);
1056
1057 #define TARGET_PAGE_BITS 12
1058
1059 #ifdef TARGET_X86_64
1060 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1061 /* ??? This is really 48 bits, sign-extended, but the only thing
1062    accessible to userland with bit 48 set is the VSYSCALL, and that
1063    is handled via other mechanisms.  */
1064 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1065 #else
1066 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1067 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1068 #endif
1069
1070 static inline CPUX86State *cpu_init(const char *cpu_model)
1071 {
1072     X86CPU *cpu = cpu_x86_init(cpu_model);
1073     if (cpu == NULL) {
1074         return NULL;
1075     }
1076     return &cpu->env;
1077 }
1078
1079 #define cpu_exec cpu_x86_exec
1080 #define cpu_gen_code cpu_x86_gen_code
1081 #define cpu_signal_handler cpu_x86_signal_handler
1082 #define cpu_list x86_cpu_list
1083 #define cpudef_setup    x86_cpudef_setup
1084
1085 #define CPU_SAVE_VERSION 12
1086
1087 /* MMU modes definitions */
1088 #define MMU_MODE0_SUFFIX _kernel
1089 #define MMU_MODE1_SUFFIX _user
1090 #define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */
1091 #define MMU_KERNEL_IDX  0
1092 #define MMU_USER_IDX    1
1093 #define MMU_KSMAP_IDX   2
1094 static inline int cpu_mmu_index (CPUX86State *env)
1095 {
1096     return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1097         ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
1098         ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
1099 }
1100
1101 #undef EAX
1102 #define EAX (env->regs[R_EAX])
1103 #undef ECX
1104 #define ECX (env->regs[R_ECX])
1105 #undef EDX
1106 #define EDX (env->regs[R_EDX])
1107 #undef EBX
1108 #define EBX (env->regs[R_EBX])
1109 #undef ESP
1110 #define ESP (env->regs[R_ESP])
1111 #undef EBP
1112 #define EBP (env->regs[R_EBP])
1113 #undef ESI
1114 #define ESI (env->regs[R_ESI])
1115 #undef EDI
1116 #define EDI (env->regs[R_EDI])
1117 #undef EIP
1118 #define EIP (env->eip)
1119 #define DF  (env->df)
1120
1121 #define CC_SRC (env->cc_src)
1122 #define CC_DST (env->cc_dst)
1123 #define CC_OP  (env->cc_op)
1124
1125 /* n must be a constant to be efficient */
1126 static inline target_long lshift(target_long x, int n)
1127 {
1128     if (n >= 0) {
1129         return x << n;
1130     } else {
1131         return x >> (-n);
1132     }
1133 }
1134
1135 /* float macros */
1136 #define FT0    (env->ft0)
1137 #define ST0    (env->fpregs[env->fpstt].d)
1138 #define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
1139 #define ST1    ST(1)
1140
1141 /* translate.c */
1142 void optimize_flags_init(void);
1143
1144 #if defined(CONFIG_USER_ONLY)
1145 static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp)
1146 {
1147     if (newsp)
1148         env->regs[R_ESP] = newsp;
1149     env->regs[R_EAX] = 0;
1150 }
1151 #endif
1152
1153 #include "exec/cpu-all.h"
1154 #include "svm.h"
1155
1156 #if !defined(CONFIG_USER_ONLY)
1157 #include "hw/apic.h"
1158 #endif
1159
1160 static inline bool cpu_has_work(CPUState *cpu)
1161 {
1162     CPUX86State *env = &X86_CPU(cpu)->env;
1163
1164     return ((env->interrupt_request & (CPU_INTERRUPT_HARD |
1165                                        CPU_INTERRUPT_POLL)) &&
1166             (env->eflags & IF_MASK)) ||
1167            (env->interrupt_request & (CPU_INTERRUPT_NMI |
1168                                       CPU_INTERRUPT_INIT |
1169                                       CPU_INTERRUPT_SIPI |
1170                                       CPU_INTERRUPT_MCE));
1171 }
1172
1173 #include "exec/exec-all.h"
1174
1175 static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb)
1176 {
1177     env->eip = tb->pc - tb->cs_base;
1178 }
1179
1180 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1181                                         target_ulong *cs_base, int *flags)
1182 {
1183     *cs_base = env->segs[R_CS].base;
1184     *pc = *cs_base + env->eip;
1185     *flags = env->hflags |
1186         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1187 }
1188
1189 void do_cpu_init(X86CPU *cpu);
1190 void do_cpu_sipi(X86CPU *cpu);
1191
1192 #define MCE_INJECT_BROADCAST    1
1193 #define MCE_INJECT_UNCOND_AO    2
1194
1195 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1196                         uint64_t status, uint64_t mcg_status, uint64_t addr,
1197                         uint64_t misc, int flags);
1198
1199 /* excp_helper.c */
1200 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1201 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1202                                        int error_code);
1203 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1204                                    int error_code, int next_eip_addend);
1205
1206 /* cc_helper.c */
1207 extern const uint8_t parity_table[256];
1208 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1209
1210 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1211 {
1212     return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK);
1213 }
1214
1215 /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
1216 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1217                                    int update_mask)
1218 {
1219     CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1220     DF = 1 - (2 * ((eflags >> 10) & 1));
1221     env->eflags = (env->eflags & ~update_mask) |
1222         (eflags & update_mask) | 0x2;
1223 }
1224
1225 /* load efer and update the corresponding hflags. XXX: do consistency
1226    checks with cpuid bits? */
1227 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1228 {
1229     env->efer = val;
1230     env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1231     if (env->efer & MSR_EFER_LMA) {
1232         env->hflags |= HF_LMA_MASK;
1233     }
1234     if (env->efer & MSR_EFER_SVME) {
1235         env->hflags |= HF_SVME_MASK;
1236     }
1237 }
1238
1239 /* svm_helper.c */
1240 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1241                                    uint64_t param);
1242 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1243
1244 /* op_helper.c */
1245 void do_interrupt(CPUX86State *env);
1246 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1247
1248 void do_smm_enter(CPUX86State *env1);
1249
1250 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1251
1252 void disable_kvm_pv_eoi(void);
1253
1254 /* Return name of 32-bit register, from a R_* constant */
1255 const char *get_register_name_32(unsigned int reg);
1256
1257 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index);
1258 void enable_compat_apic_id_mode(void);
1259
1260 #endif /* CPU_I386_H */