hw/i8254.c

   1 /*
   2  * QEMU 8253/8254 interval timer emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "qemu-timer.h"
  28 #include "i8254.h"
  29 #include "i8254_internal.h"
  30
  31 //#define DEBUG_PIT
  32
  33 #define RW_STATE_LSB 1
  34 #define RW_STATE_MSB 2
  35 #define RW_STATE_WORD0 3
  36 #define RW_STATE_WORD1 4
  37
  38 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
  39
  40 static int pit_get_count(PITChannelState *s)
  41 {
  42     uint64_t d;
  43     int counter;
  44
  45     d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
  46                  get_ticks_per_sec());
  47     switch(s->mode) {
  48     case 0:
  49     case 1:
  50     case 4:
  51     case 5:
  52         counter = (s->count - d) & 0xffff;
  53         break;
  54     case 3:
  55         /* XXX: may be incorrect for odd counts */
  56         counter = s->count - ((2 * d) % s->count);
  57         break;
  58     default:
  59         counter = s->count - (d % s->count);
  60         break;
  61     }
  62     return counter;
  63 }
  64
  65 /* val must be 0 or 1 */
  66 static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
  67                                  int val)
  68 {
  69     switch (sc->mode) {
  70     default:
  71     case 0:
  72     case 4:
  73         /* XXX: just disable/enable counting */
  74         break;
  75     case 1:
  76     case 5:
  77         if (sc->gate < val) {
  78             /* restart counting on rising edge */
  79             sc->count_load_time = qemu_get_clock_ns(vm_clock);
  80             pit_irq_timer_update(sc, sc->count_load_time);
  81         }
  82         break;
  83     case 2:
  84     case 3:
  85         if (sc->gate < val) {
  86             /* restart counting on rising edge */
  87             sc->count_load_time = qemu_get_clock_ns(vm_clock);
  88             pit_irq_timer_update(sc, sc->count_load_time);
  89         }
  90         /* XXX: disable/enable counting */
  91         break;
  92     }
  93     sc->gate = val;
  94 }
  95
  96 static inline void pit_load_count(PITChannelState *s, int val)
  97 {
  98     if (val == 0)
  99         val = 0x10000;
 100     s->count_load_time = qemu_get_clock_ns(vm_clock);
 101     s->count = val;
 102     pit_irq_timer_update(s, s->count_load_time);
 103 }
 104
 105 /* if already latched, do not latch again */
 106 static void pit_latch_count(PITChannelState *s)
 107 {
 108     if (!s->count_latched) {
 109         s->latched_count = pit_get_count(s);
 110         s->count_latched = s->rw_mode;
 111     }
 112 }
 113
 114 static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 115 {
 116     PITCommonState *pit = opaque;
 117     int channel, access;
 118     PITChannelState *s;
 119
 120     addr &= 3;
 121     if (addr == 3) {
 122         channel = val >> 6;
 123         if (channel == 3) {
 124             /* read back command */
 125             for(channel = 0; channel < 3; channel++) {
 126                 s = &pit->channels[channel];
 127                 if (val & (2 << channel)) {
 128                     if (!(val & 0x20)) {
 129                         pit_latch_count(s);
 130                     }
 131                     if (!(val & 0x10) && !s->status_latched) {
 132                         /* status latch */
 133                         /* XXX: add BCD and null count */
 134                         s->status =
 135                             (pit_get_out(s,
 136                                          qemu_get_clock_ns(vm_clock)) << 7) |
 137                             (s->rw_mode << 4) |
 138                             (s->mode << 1) |
 139                             s->bcd;
 140                         s->status_latched = 1;
 141                     }
 142                 }
 143             }
 144         } else {
 145             s = &pit->channels[channel];
 146             access = (val >> 4) & 3;
 147             if (access == 0) {
 148                 pit_latch_count(s);
 149             } else {
 150                 s->rw_mode = access;
 151                 s->read_state = access;
 152                 s->write_state = access;
 153
 154                 s->mode = (val >> 1) & 7;
 155                 s->bcd = val & 1;
 156                 /* XXX: update irq timer ? */
 157             }
 158         }
 159     } else {
 160         s = &pit->channels[addr];
 161         switch(s->write_state) {
 162         default:
 163         case RW_STATE_LSB:
 164             pit_load_count(s, val);
 165             break;
 166         case RW_STATE_MSB:
 167             pit_load_count(s, val << 8);
 168             break;
 169         case RW_STATE_WORD0:
 170             s->write_latch = val;
 171             s->write_state = RW_STATE_WORD1;
 172             break;
 173         case RW_STATE_WORD1:
 174             pit_load_count(s, s->write_latch | (val << 8));
 175             s->write_state = RW_STATE_WORD0;
 176             break;
 177         }
 178     }
 179 }
 180
 181 static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
 182 {
 183     PITCommonState *pit = opaque;
 184     int ret, count;
 185     PITChannelState *s;
 186
 187     addr &= 3;
 188     s = &pit->channels[addr];
 189     if (s->status_latched) {
 190         s->status_latched = 0;
 191         ret = s->status;
 192     } else if (s->count_latched) {
 193         switch(s->count_latched) {
 194         default:
 195         case RW_STATE_LSB:
 196             ret = s->latched_count & 0xff;
 197             s->count_latched = 0;
 198             break;
 199         case RW_STATE_MSB:
 200             ret = s->latched_count >> 8;
 201             s->count_latched = 0;
 202             break;
 203         case RW_STATE_WORD0:
 204             ret = s->latched_count & 0xff;
 205             s->count_latched = RW_STATE_MSB;
 206             break;
 207         }
 208     } else {
 209         switch(s->read_state) {
 210         default:
 211         case RW_STATE_LSB:
 212             count = pit_get_count(s);
 213             ret = count & 0xff;
 214             break;
 215         case RW_STATE_MSB:
 216             count = pit_get_count(s);
 217             ret = (count >> 8) & 0xff;
 218             break;
 219         case RW_STATE_WORD0:
 220             count = pit_get_count(s);
 221             ret = count & 0xff;
 222             s->read_state = RW_STATE_WORD1;
 223             break;
 224         case RW_STATE_WORD1:
 225             count = pit_get_count(s);
 226             ret = (count >> 8) & 0xff;
 227             s->read_state = RW_STATE_WORD0;
 228             break;
 229         }
 230     }
 231     return ret;
 232 }
 233
 234 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
 235 {
 236     int64_t expire_time;
 237     int irq_level;
 238
 239     if (!s->irq_timer || s->irq_disabled) {
 240         return;
 241     }
 242     expire_time = pit_get_next_transition_time(s, current_time);
 243     irq_level = pit_get_out(s, current_time);
 244     qemu_set_irq(s->irq, irq_level);
 245 #ifdef DEBUG_PIT
 246     printf("irq_level=%d next_delay=%f\n",
 247            irq_level,
 248            (double)(expire_time - current_time) / get_ticks_per_sec());
 249 #endif
 250     s->next_transition_time = expire_time;
 251     if (expire_time != -1)
 252         qemu_mod_timer(s->irq_timer, expire_time);
 253     else
 254         qemu_del_timer(s->irq_timer);
 255 }
 256
 257 static void pit_irq_timer(void *opaque)
 258 {
 259     PITChannelState *s = opaque;
 260
 261     pit_irq_timer_update(s, s->next_transition_time);
 262 }
 263
 264 static void pit_reset(DeviceState *dev)
 265 {
 266     PITCommonState *pit = DO_UPCAST(PITCommonState, dev.qdev, dev);
 267     PITChannelState *s;
 268
 269     pit_reset_common(pit);
 270
 271     s = &pit->channels[0];
 272     if (!s->irq_disabled) {
 273         qemu_mod_timer(s->irq_timer, s->next_transition_time);
 274     }
 275 }
 276
 277 /* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
 278  * reenable it when legacy mode is left again. */
 279 static void pit_irq_control(void *opaque, int n, int enable)
 280 {
 281     PITCommonState *pit = opaque;
 282     PITChannelState *s = &pit->channels[0];
 283
 284     if (enable) {
 285         s->irq_disabled = 0;
 286         pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock));
 287     } else {
 288         s->irq_disabled = 1;
 289         qemu_del_timer(s->irq_timer);
 290     }
 291 }
 292
 293 static const MemoryRegionPortio pit_portio[] = {
 294     { 0, 4, 1, .write = pit_ioport_write },
 295     { 0, 3, 1, .read = pit_ioport_read },
 296     PORTIO_END_OF_LIST()
 297 };
 298
 299 static const MemoryRegionOps pit_ioport_ops = {
 300     .old_portio = pit_portio
 301 };
 302
 303 static void pit_post_load(PITCommonState *s)
 304 {
 305     PITChannelState *sc = &s->channels[0];
 306
 307     if (sc->next_transition_time != -1) {
 308         qemu_mod_timer(sc->irq_timer, sc->next_transition_time);
 309     } else {
 310         qemu_del_timer(sc->irq_timer);
 311     }
 312 }
 313
 314 static int pit_initfn(PITCommonState *pit)
 315 {
 316     PITChannelState *s;
 317
 318     s = &pit->channels[0];
 319     /* the timer 0 is connected to an IRQ */
 320     s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
 321     qdev_init_gpio_out(&pit->dev.qdev, &s->irq, 1);
 322
 323     memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4);
 324
 325     qdev_init_gpio_in(&pit->dev.qdev, pit_irq_control, 1);
 326
 327     return 0;
 328 }
 329
 330 static Property pit_properties[] = {
 331     DEFINE_PROP_HEX32("iobase", PITCommonState, iobase,  -1),
 332     DEFINE_PROP_END_OF_LIST(),
 333 };
 334
 335 static void pit_class_initfn(ObjectClass *klass, void *data)
 336 {
 337     PITCommonClass *k = PIT_COMMON_CLASS(klass);
 338     DeviceClass *dc = DEVICE_CLASS(klass);
 339
 340     k->init = pit_initfn;
 341     k->set_channel_gate = pit_set_channel_gate;
 342     k->get_channel_info = pit_get_channel_info_common;
 343     k->post_load = pit_post_load;
 344     dc->reset = pit_reset;
 345     dc->props = pit_properties;
 346 }
 347
 348 static TypeInfo pit_info = {
 349     .name          = "isa-pit",
 350     .parent        = TYPE_PIT_COMMON,
 351     .instance_size = sizeof(PITCommonState),
 352     .class_init    = pit_class_initfn,
 353 };
 354
 355 static void pit_register_types(void)
 356 {
 357     type_register_static(&pit_info);
 358 }
 359
 360 type_init(pit_register_types)