hw/spapr_pci.c

   1 /*
   2  * QEMU sPAPR PCI host originated from Uninorth PCI host
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
   5  * Copyright (C) 2011 David Gibson, IBM Corporation.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "msi.h"
  28 #include "msix.h"
  29 #include "pci_host.h"
  30 #include "hw/spapr.h"
  31 #include "hw/spapr_pci.h"
  32 #include "exec-memory.h"
  33 #include <libfdt.h>
  34 #include "trace.h"
  35
  36 #include "hw/pci_internals.h"
  37
  38 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
  39 #define RTAS_QUERY_FN           0
  40 #define RTAS_CHANGE_FN          1
  41 #define RTAS_RESET_FN           2
  42 #define RTAS_CHANGE_MSI_FN      3
  43 #define RTAS_CHANGE_MSIX_FN     4
  44
  45 /* Interrupt types to return on RTAS_CHANGE_* */
  46 #define RTAS_TYPE_MSI           1
  47 #define RTAS_TYPE_MSIX          2
  48
  49 static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
  50 {
  51     sPAPRPHBState *sphb;
  52
  53     QLIST_FOREACH(sphb, &spapr->phbs, list) {
  54         if (sphb->buid != buid) {
  55             continue;
  56         }
  57         return sphb;
  58     }
  59
  60     return NULL;
  61 }
  62
  63 static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
  64                            uint32_t config_addr)
  65 {
  66     sPAPRPHBState *sphb = find_phb(spapr, buid);
  67     PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
  68     BusState *bus = BUS(phb->bus);
  69     BusChild *kid;
  70     int devfn = (config_addr >> 8) & 0xFF;
  71
  72     if (!phb) {
  73         return NULL;
  74     }
  75
  76     QTAILQ_FOREACH(kid, &bus->children, sibling) {
  77         PCIDevice *dev = (PCIDevice *)kid->child;
  78         if (dev->devfn == devfn) {
  79             return dev;
  80         }
  81     }
  82
  83     return NULL;
  84 }
  85
  86 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
  87 {
  88     /* This handles the encoding of extended config space addresses */
  89     return ((arg >> 20) & 0xf00) | (arg & 0xff);
  90 }
  91
  92 static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
  93                                    uint32_t addr, uint32_t size,
  94                                    target_ulong rets)
  95 {
  96     PCIDevice *pci_dev;
  97     uint32_t val;
  98
  99     if ((size != 1) && (size != 2) && (size != 4)) {
 100         /* access must be 1, 2 or 4 bytes */
 101         rtas_st(rets, 0, -1);
 102         return;
 103     }
 104
 105     pci_dev = find_dev(spapr, buid, addr);
 106     addr = rtas_pci_cfgaddr(addr);
 107
 108     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
 109         /* Access must be to a valid device, within bounds and
 110          * naturally aligned */
 111         rtas_st(rets, 0, -1);
 112         return;
 113     }
 114
 115     val = pci_host_config_read_common(pci_dev, addr,
 116                                       pci_config_size(pci_dev), size);
 117
 118     rtas_st(rets, 0, 0);
 119     rtas_st(rets, 1, val);
 120 }
 121
 122 static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
 123                                      uint32_t token, uint32_t nargs,
 124                                      target_ulong args,
 125                                      uint32_t nret, target_ulong rets)
 126 {
 127     uint64_t buid;
 128     uint32_t size, addr;
 129
 130     if ((nargs != 4) || (nret != 2)) {
 131         rtas_st(rets, 0, -1);
 132         return;
 133     }
 134
 135     buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 136     size = rtas_ld(args, 3);
 137     addr = rtas_ld(args, 0);
 138
 139     finish_read_pci_config(spapr, buid, addr, size, rets);
 140 }
 141
 142 static void rtas_read_pci_config(sPAPREnvironment *spapr,
 143                                  uint32_t token, uint32_t nargs,
 144                                  target_ulong args,
 145                                  uint32_t nret, target_ulong rets)
 146 {
 147     uint32_t size, addr;
 148
 149     if ((nargs != 2) || (nret != 2)) {
 150         rtas_st(rets, 0, -1);
 151         return;
 152     }
 153
 154     size = rtas_ld(args, 1);
 155     addr = rtas_ld(args, 0);
 156
 157     finish_read_pci_config(spapr, 0, addr, size, rets);
 158 }
 159
 160 static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
 161                                     uint32_t addr, uint32_t size,
 162                                     uint32_t val, target_ulong rets)
 163 {
 164     PCIDevice *pci_dev;
 165
 166     if ((size != 1) && (size != 2) && (size != 4)) {
 167         /* access must be 1, 2 or 4 bytes */
 168         rtas_st(rets, 0, -1);
 169         return;
 170     }
 171
 172     pci_dev = find_dev(spapr, buid, addr);
 173     addr = rtas_pci_cfgaddr(addr);
 174
 175     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
 176         /* Access must be to a valid device, within bounds and
 177          * naturally aligned */
 178         rtas_st(rets, 0, -1);
 179         return;
 180     }
 181
 182     pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
 183                                  val, size);
 184
 185     rtas_st(rets, 0, 0);
 186 }
 187
 188 static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
 189                                       uint32_t token, uint32_t nargs,
 190                                       target_ulong args,
 191                                       uint32_t nret, target_ulong rets)
 192 {
 193     uint64_t buid;
 194     uint32_t val, size, addr;
 195
 196     if ((nargs != 5) || (nret != 1)) {
 197         rtas_st(rets, 0, -1);
 198         return;
 199     }
 200
 201     buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 202     val = rtas_ld(args, 4);
 203     size = rtas_ld(args, 3);
 204     addr = rtas_ld(args, 0);
 205
 206     finish_write_pci_config(spapr, buid, addr, size, val, rets);
 207 }
 208
 209 static void rtas_write_pci_config(sPAPREnvironment *spapr,
 210                                   uint32_t token, uint32_t nargs,
 211                                   target_ulong args,
 212                                   uint32_t nret, target_ulong rets)
 213 {
 214     uint32_t val, size, addr;
 215
 216     if ((nargs != 3) || (nret != 1)) {
 217         rtas_st(rets, 0, -1);
 218         return;
 219     }
 220
 221
 222     val = rtas_ld(args, 2);
 223     size = rtas_ld(args, 1);
 224     addr = rtas_ld(args, 0);
 225
 226     finish_write_pci_config(spapr, 0, addr, size, val, rets);
 227 }
 228
 229 /*
 230  * Find an entry with config_addr or returns the empty one if not found AND
 231  * alloc_new is set.
 232  * At the moment the msi_table entries are never released so there is
 233  * no point to look till the end of the list if we need to find the free entry.
 234  */
 235 static int spapr_msicfg_find(sPAPRPHBState *phb, uint32_t config_addr,
 236                              bool alloc_new)
 237 {
 238     int i;
 239
 240     for (i = 0; i < SPAPR_MSIX_MAX_DEVS; ++i) {
 241         if (!phb->msi_table[i].nvec) {
 242             break;
 243         }
 244         if (phb->msi_table[i].config_addr == config_addr) {
 245             return i;
 246         }
 247     }
 248     if ((i < SPAPR_MSIX_MAX_DEVS) && alloc_new) {
 249         trace_spapr_pci_msi("Allocating new MSI config", i, config_addr);
 250         return i;
 251     }
 252
 253     return -1;
 254 }
 255
 256 /*
 257  * Set MSI/MSIX message data.
 258  * This is required for msi_notify()/msix_notify() which
 259  * will write at the addresses via spapr_msi_write().
 260  */
 261 static void spapr_msi_setmsg(PCIDevice *pdev, target_phys_addr_t addr,
 262                              bool msix, unsigned req_num)
 263 {
 264     unsigned i;
 265     MSIMessage msg = { .address = addr, .data = 0 };
 266
 267     if (!msix) {
 268         msi_set_message(pdev, msg);
 269         trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
 270         return;
 271     }
 272
 273     for (i = 0; i < req_num; ++i) {
 274         msg.address = addr | (i << 2);
 275         msix_set_message(pdev, i, msg);
 276         trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
 277     }
 278 }
 279
 280 static void rtas_ibm_change_msi(sPAPREnvironment *spapr,
 281                                 uint32_t token, uint32_t nargs,
 282                                 target_ulong args, uint32_t nret,
 283                                 target_ulong rets)
 284 {
 285     uint32_t config_addr = rtas_ld(args, 0);
 286     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 287     unsigned int func = rtas_ld(args, 3);
 288     unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
 289     unsigned int seq_num = rtas_ld(args, 5);
 290     unsigned int ret_intr_type;
 291     int ndev, irq;
 292     sPAPRPHBState *phb = NULL;
 293     PCIDevice *pdev = NULL;
 294
 295     switch (func) {
 296     case RTAS_CHANGE_MSI_FN:
 297     case RTAS_CHANGE_FN:
 298         ret_intr_type = RTAS_TYPE_MSI;
 299         break;
 300     case RTAS_CHANGE_MSIX_FN:
 301         ret_intr_type = RTAS_TYPE_MSIX;
 302         break;
 303     default:
 304         fprintf(stderr, "rtas_ibm_change_msi(%u) is not implemented\n", func);
 305         rtas_st(rets, 0, -3); /* Parameter error */
 306         return;
 307     }
 308
 309     /* Fins sPAPRPHBState */
 310     phb = find_phb(spapr, buid);
 311     if (phb) {
 312         pdev = find_dev(spapr, buid, config_addr);
 313     }
 314     if (!phb || !pdev) {
 315         rtas_st(rets, 0, -3); /* Parameter error */
 316         return;
 317     }
 318
 319     /* Releasing MSIs */
 320     if (!req_num) {
 321         ndev = spapr_msicfg_find(phb, config_addr, false);
 322         if (ndev < 0) {
 323             trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr);
 324             rtas_st(rets, 0, -1); /* Hardware error */
 325             return;
 326         }
 327         trace_spapr_pci_msi("Released MSIs", ndev, config_addr);
 328         rtas_st(rets, 0, 0);
 329         rtas_st(rets, 1, 0);
 330         return;
 331     }
 332
 333     /* Enabling MSI */
 334
 335     /* Find a device number in the map to add or reuse the existing one */
 336     ndev = spapr_msicfg_find(phb, config_addr, true);
 337     if (ndev >= SPAPR_MSIX_MAX_DEVS || ndev < 0) {
 338         fprintf(stderr, "No free entry for a new MSI device\n");
 339         rtas_st(rets, 0, -1); /* Hardware error */
 340         return;
 341     }
 342     trace_spapr_pci_msi("Configuring MSI", ndev, config_addr);
 343
 344     /* Check if there is an old config and MSI number has not changed */
 345     if (phb->msi_table[ndev].nvec && (req_num != phb->msi_table[ndev].nvec)) {
 346         /* Unexpected behaviour */
 347         fprintf(stderr, "Cannot reuse MSI config for device#%d", ndev);
 348         rtas_st(rets, 0, -1); /* Hardware error */
 349         return;
 350     }
 351
 352     /* There is no cached config, allocate MSIs */
 353     if (!phb->msi_table[ndev].nvec) {
 354         irq = spapr_allocate_irq_block(req_num, true);
 355         if (irq < 0) {
 356             fprintf(stderr, "Cannot allocate MSIs for device#%d", ndev);
 357             rtas_st(rets, 0, -1); /* Hardware error */
 358             return;
 359         }
 360         phb->msi_table[ndev].irq = irq;
 361         phb->msi_table[ndev].nvec = req_num;
 362         phb->msi_table[ndev].config_addr = config_addr;
 363     }
 364
 365     /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
 366     spapr_msi_setmsg(pdev, phb->msi_win_addr | (ndev << 16),
 367                      ret_intr_type == RTAS_TYPE_MSIX, req_num);
 368
 369     rtas_st(rets, 0, 0);
 370     rtas_st(rets, 1, req_num);
 371     rtas_st(rets, 2, ++seq_num);
 372     rtas_st(rets, 3, ret_intr_type);
 373
 374     trace_spapr_pci_rtas_ibm_change_msi(func, req_num);
 375 }
 376
 377 static void rtas_ibm_query_interrupt_source_number(sPAPREnvironment *spapr,
 378                                                    uint32_t token,
 379                                                    uint32_t nargs,
 380                                                    target_ulong args,
 381                                                    uint32_t nret,
 382                                                    target_ulong rets)
 383 {
 384     uint32_t config_addr = rtas_ld(args, 0);
 385     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 386     unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
 387     int ndev;
 388     sPAPRPHBState *phb = NULL;
 389
 390     /* Fins sPAPRPHBState */
 391     phb = find_phb(spapr, buid);
 392     if (!phb) {
 393         rtas_st(rets, 0, -3); /* Parameter error */
 394         return;
 395     }
 396
 397     /* Find device descriptor and start IRQ */
 398     ndev = spapr_msicfg_find(phb, config_addr, false);
 399     if (ndev < 0) {
 400         trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr);
 401         rtas_st(rets, 0, -1); /* Hardware error */
 402         return;
 403     }
 404
 405     intr_src_num = phb->msi_table[ndev].irq + ioa_intr_num;
 406     trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
 407                                                            intr_src_num);
 408
 409     rtas_st(rets, 0, 0);
 410     rtas_st(rets, 1, intr_src_num);
 411     rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
 412 }
 413
 414 static int pci_spapr_swizzle(int slot, int pin)
 415 {
 416     return (slot + pin) % PCI_NUM_PINS;
 417 }
 418
 419 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
 420 {
 421     /*
 422      * Here we need to convert pci_dev + irq_num to some unique value
 423      * which is less than number of IRQs on the specific bus (4).  We
 424      * use standard PCI swizzling, that is (slot number + pin number)
 425      * % 4.
 426      */
 427     return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
 428 }
 429
 430 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
 431 {
 432     /*
 433      * Here we use the number returned by pci_spapr_map_irq to find a
 434      * corresponding qemu_irq.
 435      */
 436     sPAPRPHBState *phb = opaque;
 437
 438     trace_spapr_pci_lsi_set(phb->busname, irq_num, phb->lsi_table[irq_num].irq);
 439     qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
 440 }
 441
 442 static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
 443                               unsigned size)
 444 {
 445     switch (size) {
 446     case 1:
 447         return cpu_inb(addr);
 448     case 2:
 449         return cpu_inw(addr);
 450     case 4:
 451         return cpu_inl(addr);
 452     }
 453     assert(0);
 454 }
 455
 456 static void spapr_io_write(void *opaque, target_phys_addr_t addr,
 457                            uint64_t data, unsigned size)
 458 {
 459     switch (size) {
 460     case 1:
 461         cpu_outb(addr, data);
 462         return;
 463     case 2:
 464         cpu_outw(addr, data);
 465         return;
 466     case 4:
 467         cpu_outl(addr, data);
 468         return;
 469     }
 470     assert(0);
 471 }
 472
 473 static const MemoryRegionOps spapr_io_ops = {
 474     .endianness = DEVICE_LITTLE_ENDIAN,
 475     .read = spapr_io_read,
 476     .write = spapr_io_write
 477 };
 478
 479 /*
 480  * MSI/MSIX memory region implementation.
 481  * The handler handles both MSI and MSIX.
 482  * For MSI-X, the vector number is encoded as a part of the address,
 483  * data is set to 0.
 484  * For MSI, the vector number is encoded in least bits in data.
 485  */
 486 static void spapr_msi_write(void *opaque, target_phys_addr_t addr,
 487                             uint64_t data, unsigned size)
 488 {
 489     sPAPRPHBState *phb = opaque;
 490     int ndev = addr >> 16;
 491     int vec = ((addr & 0xFFFF) >> 2) | data;
 492     uint32_t irq = phb->msi_table[ndev].irq + vec;
 493
 494     trace_spapr_pci_msi_write(addr, data, irq);
 495
 496     qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));
 497 }
 498
 499 static const MemoryRegionOps spapr_msi_ops = {
 500     /* There is no .read as the read result is undefined by PCI spec */
 501     .read = NULL,
 502     .write = spapr_msi_write,
 503     .endianness = DEVICE_LITTLE_ENDIAN
 504 };
 505
 506 /*
 507  * PHB PCI device
 508  */
 509 static DMAContext *spapr_pci_dma_context_fn(PCIBus *bus, void *opaque,
 510                                             int devfn)
 511 {
 512     sPAPRPHBState *phb = opaque;
 513
 514     return phb->dma;
 515 }
 516
 517 static int spapr_phb_init(SysBusDevice *s)
 518 {
 519     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
 520     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 521     char *namebuf;
 522     int i;
 523     PCIBus *bus;
 524
 525     sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
 526     namebuf = alloca(strlen(sphb->dtbusname) + 32);
 527
 528     /* Initialize memory regions */
 529     sprintf(namebuf, "%s.mmio", sphb->dtbusname);
 530     memory_region_init(&sphb->memspace, namebuf, INT64_MAX);
 531
 532     sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname);
 533     memory_region_init_alias(&sphb->memwindow, namebuf, &sphb->memspace,
 534                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
 535     memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
 536                                 &sphb->memwindow);
 537
 538     /* On ppc, we only have MMIO no specific IO space from the CPU
 539      * perspective.  In theory we ought to be able to embed the PCI IO
 540      * memory region direction in the system memory space.  However,
 541      * if any of the IO BAR subregions use the old_portio mechanism,
 542      * that won't be processed properly unless accessed from the
 543      * system io address space.  This hack to bounce things via
 544      * system_io works around the problem until all the users of
 545      * old_portion are updated */
 546     sprintf(namebuf, "%s.io", sphb->dtbusname);
 547     memory_region_init(&sphb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
 548     /* FIXME: fix to support multiple PHBs */
 549     memory_region_add_subregion(get_system_io(), 0, &sphb->iospace);
 550
 551     sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
 552     memory_region_init_io(&sphb->iowindow, &spapr_io_ops, sphb,
 553                           namebuf, SPAPR_PCI_IO_WIN_SIZE);
 554     memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
 555                                 &sphb->iowindow);
 556
 557     /* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
 558      * we need to allocate some memory to catch those writes coming
 559      * from msi_notify()/msix_notify() */
 560     if (msi_supported) {
 561         sprintf(namebuf, "%s.msi", sphb->dtbusname);
 562         memory_region_init_io(&sphb->msiwindow, &spapr_msi_ops, sphb,
 563                               namebuf, SPAPR_MSIX_MAX_DEVS * 0x10000);
 564         memory_region_add_subregion(get_system_memory(), sphb->msi_win_addr,
 565                                     &sphb->msiwindow);
 566     }
 567
 568     bus = pci_register_bus(DEVICE(s),
 569                            sphb->busname ? sphb->busname : sphb->dtbusname,
 570                            pci_spapr_set_irq, pci_spapr_map_irq, sphb,
 571                            &sphb->memspace, &sphb->iospace,
 572                            PCI_DEVFN(0, 0), PCI_NUM_PINS);
 573     phb->bus = bus;
 574
 575     sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN | (pci_find_domain(bus) << 16);
 576     sphb->dma_window_start = 0;
 577     sphb->dma_window_size = 0x40000000;
 578     sphb->dma = spapr_tce_new_dma_context(sphb->dma_liobn, sphb->dma_window_size);
 579     pci_setup_iommu(bus, spapr_pci_dma_context_fn, sphb);
 580
 581     QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
 582
 583     /* Initialize the LSI table */
 584     for (i = 0; i < PCI_NUM_PINS; i++) {
 585         uint32_t irq;
 586
 587         irq = spapr_allocate_lsi(0);
 588         if (!irq) {
 589             return -1;
 590         }
 591
 592         sphb->lsi_table[i].irq = irq;
 593     }
 594
 595     return 0;
 596 }
 597
 598 static void spapr_phb_reset(DeviceState *qdev)
 599 {
 600     SysBusDevice *s = sysbus_from_qdev(qdev);
 601     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
 602
 603     /* Reset the IOMMU state */
 604     spapr_tce_reset(sphb->dma);
 605 }
 606
 607 static Property spapr_phb_properties[] = {
 608     DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
 609     DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
 610     DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
 611     DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
 612     DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
 613     DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
 614     DEFINE_PROP_HEX64("msi_win_addr", sPAPRPHBState, msi_win_addr, 0),
 615     DEFINE_PROP_END_OF_LIST(),
 616 };
 617
 618 static void spapr_phb_class_init(ObjectClass *klass, void *data)
 619 {
 620     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 621     DeviceClass *dc = DEVICE_CLASS(klass);
 622
 623     sdc->init = spapr_phb_init;
 624     dc->props = spapr_phb_properties;
 625     dc->reset = spapr_phb_reset;
 626 }
 627
 628 static const TypeInfo spapr_phb_info = {
 629     .name          = TYPE_SPAPR_PCI_HOST_BRIDGE,
 630     .parent        = TYPE_PCI_HOST_BRIDGE,
 631     .instance_size = sizeof(sPAPRPHBState),
 632     .class_init    = spapr_phb_class_init,
 633 };
 634
 635 void spapr_create_phb(sPAPREnvironment *spapr,
 636                       const char *busname, uint64_t buid,
 637                       uint64_t mem_win_addr, uint64_t mem_win_size,
 638                       uint64_t io_win_addr, uint64_t msi_win_addr)
 639 {
 640     DeviceState *dev;
 641
 642     dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
 643
 644     if (busname) {
 645         qdev_prop_set_string(dev, "busname", g_strdup(busname));
 646     }
 647     qdev_prop_set_uint64(dev, "buid", buid);
 648     qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
 649     qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
 650     qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);
 651     qdev_prop_set_uint64(dev, "msi_win_addr", msi_win_addr);
 652
 653     qdev_init_nofail(dev);
 654 }
 655
 656 /* Macros to operate with address in OF binding to PCI */
 657 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
 658 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
 659 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
 660 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
 661 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
 662 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
 663 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
 664 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
 665 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
 666
 667 int spapr_populate_pci_dt(sPAPRPHBState *phb,
 668                           uint32_t xics_phandle,
 669                           void *fdt)
 670 {
 671     int bus_off, i, j;
 672     char nodename[256];
 673     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
 674     struct {
 675         uint32_t hi;
 676         uint64_t child;
 677         uint64_t parent;
 678         uint64_t size;
 679     } QEMU_PACKED ranges[] = {
 680         {
 681             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
 682             cpu_to_be64(phb->io_win_addr),
 683             cpu_to_be64(memory_region_size(&phb->iospace)),
 684         },
 685         {
 686             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
 687             cpu_to_be64(phb->mem_win_addr),
 688             cpu_to_be64(memory_region_size(&phb->memwindow)),
 689         },
 690     };
 691     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
 692     uint32_t interrupt_map_mask[] = {
 693         cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
 694     uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
 695
 696     /* Start populating the FDT */
 697     sprintf(nodename, "pci@%" PRIx64, phb->buid);
 698     bus_off = fdt_add_subnode(fdt, 0, nodename);
 699     if (bus_off < 0) {
 700         return bus_off;
 701     }
 702
 703 #define _FDT(exp) \
 704     do { \
 705         int ret = (exp);                                           \
 706         if (ret < 0) {                                             \
 707             return ret;                                            \
 708         }                                                          \
 709     } while (0)
 710
 711     /* Write PHB properties */
 712     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
 713     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
 714     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
 715     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
 716     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
 717     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
 718     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
 719     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
 720     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
 721     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
 722
 723     /* Build the interrupt-map, this must matches what is done
 724      * in pci_spapr_map_irq
 725      */
 726     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
 727                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
 728     for (i = 0; i < PCI_SLOT_MAX; i++) {
 729         for (j = 0; j < PCI_NUM_PINS; j++) {
 730             uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
 731             int lsi_num = pci_spapr_swizzle(i, j);
 732
 733             irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
 734             irqmap[1] = 0;
 735             irqmap[2] = 0;
 736             irqmap[3] = cpu_to_be32(j+1);
 737             irqmap[4] = cpu_to_be32(xics_phandle);
 738             irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
 739             irqmap[6] = cpu_to_be32(0x8);
 740         }
 741     }
 742     /* Write interrupt map */
 743     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
 744                      sizeof(interrupt_map)));
 745
 746     spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
 747                  phb->dma_liobn, phb->dma_window_start,
 748                  phb->dma_window_size);
 749
 750     return 0;
 751 }
 752
 753 void spapr_pci_rtas_init(void)
 754 {
 755     spapr_rtas_register("read-pci-config", rtas_read_pci_config);
 756     spapr_rtas_register("write-pci-config", rtas_write_pci_config);
 757     spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
 758     spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
 759     if (msi_supported) {
 760         spapr_rtas_register("ibm,query-interrupt-source-number",
 761                             rtas_ibm_query_interrupt_source_number);
 762         spapr_rtas_register("ibm,change-msi", rtas_ibm_change_msi);
 763     }
 764 }
 765
 766 static void spapr_pci_register_types(void)
 767 {
 768     type_register_static(&spapr_phb_info);
 769 }
 770
 771 type_init(spapr_pci_register_types)