?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-i386: Use mulu2 and muls2
[qemu/pbrook.git] / target-mips / op_helper.c
blob45cbb2f1c254f454dd4c7b843a93b1190d30b935
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22
23 #include "helper.h"
24
25 #if !defined(CONFIG_USER_ONLY)
26 #include "exec/softmmu_exec.h"
27 #endif /* !defined(CONFIG_USER_ONLY) */
28
29 #ifndef CONFIG_USER_ONLY
30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
31 #endif
32
33 /*****************************************************************************/
34 /* Exceptions processing helpers */
35
36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
37 uint32_t exception,
38 int error_code,
39 uintptr_t pc)
40 {
41 if (exception < EXCP_SC) {
42 qemu_log("%s: %d %d\n", __func__, exception, error_code);
43 }
44 env->exception_index = exception;
45 env->error_code = error_code;
46
47 if (pc) {
48 /* now we have a real cpu fault */
49 cpu_restore_state(env, pc);
50 }
51
52 cpu_loop_exit(env);
53 }
54
55 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
56 uint32_t exception,
57 uintptr_t pc)
58 {
59 do_raise_exception_err(env, exception, 0, pc);
60 }
61
62 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
63 int error_code)
64 {
65 do_raise_exception_err(env, exception, error_code, 0);
66 }
67
68 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
69 {
70 do_raise_exception(env, exception, 0);
71 }
72
73 #if defined(CONFIG_USER_ONLY)
74 #define HELPER_LD(name, insn, type) \
75 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
76 int mem_idx) \
77 { \
78 return (type) insn##_raw(addr); \
79 }
80 #else
81 #define HELPER_LD(name, insn, type) \
82 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
83 int mem_idx) \
84 { \
85 switch (mem_idx) \
86 { \
87 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
88 case 1: return (type) cpu_##insn##_super(env, addr); break; \
89 default: \
90 case 2: return (type) cpu_##insn##_user(env, addr); break; \
91 } \
92 }
93 #endif
94 HELPER_LD(lbu, ldub, uint8_t)
95 HELPER_LD(lw, ldl, int32_t)
96 #ifdef TARGET_MIPS64
97 HELPER_LD(ld, ldq, int64_t)
98 #endif
99 #undef HELPER_LD
100
101 #if defined(CONFIG_USER_ONLY)
102 #define HELPER_ST(name, insn, type) \
103 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
104 type val, int mem_idx) \
105 { \
106 insn##_raw(addr, val); \
107 }
108 #else
109 #define HELPER_ST(name, insn, type) \
110 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
111 type val, int mem_idx) \
112 { \
113 switch (mem_idx) \
114 { \
115 case 0: cpu_##insn##_kernel(env, addr, val); break; \
116 case 1: cpu_##insn##_super(env, addr, val); break; \
117 default: \
118 case 2: cpu_##insn##_user(env, addr, val); break; \
119 } \
120 }
121 #endif
122 HELPER_ST(sb, stb, uint8_t)
123 HELPER_ST(sw, stl, uint32_t)
124 #ifdef TARGET_MIPS64
125 HELPER_ST(sd, stq, uint64_t)
126 #endif
127 #undef HELPER_ST
128
129 target_ulong helper_clo (target_ulong arg1)
130 {
131 return clo32(arg1);
132 }
133
134 target_ulong helper_clz (target_ulong arg1)
135 {
136 return clz32(arg1);
137 }
138
139 #if defined(TARGET_MIPS64)
140 target_ulong helper_dclo (target_ulong arg1)
141 {
142 return clo64(arg1);
143 }
144
145 target_ulong helper_dclz (target_ulong arg1)
146 {
147 return clz64(arg1);
148 }
149 #endif /* TARGET_MIPS64 */
150
151 /* 64 bits arithmetic for 32 bits hosts */
152 static inline uint64_t get_HILO(CPUMIPSState *env)
153 {
154 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
155 }
156
157 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
158 {
159 target_ulong tmp;
160 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
161 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
162 return tmp;
163 }
164
165 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
166 {
167 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
168 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
169 return tmp;
170 }
171
172 /* Multiplication variants of the vr54xx. */
173 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
174 target_ulong arg2)
175 {
176 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
177 (int64_t)(int32_t)arg2));
178 }
179
180 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
181 target_ulong arg2)
182 {
183 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
184 (uint64_t)(uint32_t)arg2);
185 }
186
187 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
188 target_ulong arg2)
189 {
190 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
191 (int64_t)(int32_t)arg2);
192 }
193
194 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
195 target_ulong arg2)
196 {
197 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
198 (int64_t)(int32_t)arg2);
199 }
200
201 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
202 target_ulong arg2)
203 {
204 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
205 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
206 }
207
208 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
209 target_ulong arg2)
210 {
211 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
212 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
213 }
214
215 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
216 target_ulong arg2)
217 {
218 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
219 (int64_t)(int32_t)arg2);
220 }
221
222 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
223 target_ulong arg2)
224 {
225 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
226 (int64_t)(int32_t)arg2);
227 }
228
229 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
230 target_ulong arg2)
231 {
232 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
233 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
234 }
235
236 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
237 target_ulong arg2)
238 {
239 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
240 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
241 }
242
243 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
244 target_ulong arg2)
245 {
246 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
247 }
248
249 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
250 target_ulong arg2)
251 {
252 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
253 (uint64_t)(uint32_t)arg2);
254 }
255
256 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
257 target_ulong arg2)
258 {
259 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
260 (int64_t)(int32_t)arg2);
261 }
262
263 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
264 target_ulong arg2)
265 {
266 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
267 (uint64_t)(uint32_t)arg2);
268 }
269
270 #ifndef CONFIG_USER_ONLY
271
272 static inline hwaddr do_translate_address(CPUMIPSState *env,
273 target_ulong address,
274 int rw)
275 {
276 hwaddr lladdr;
277
278 lladdr = cpu_mips_translate_address(env, address, rw);
279
280 if (lladdr == -1LL) {
281 cpu_loop_exit(env);
282 } else {
283 return lladdr;
284 }
285 }
286
287 #define HELPER_LD_ATOMIC(name, insn) \
288 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
289 { \
290 env->lladdr = do_translate_address(env, arg, 0); \
291 env->llval = do_##insn(env, arg, mem_idx); \
292 return env->llval; \
293 }
294 HELPER_LD_ATOMIC(ll, lw)
295 #ifdef TARGET_MIPS64
296 HELPER_LD_ATOMIC(lld, ld)
297 #endif
298 #undef HELPER_LD_ATOMIC
299
300 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
301 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
302 target_ulong arg2, int mem_idx) \
303 { \
304 target_long tmp; \
305 \
306 if (arg2 & almask) { \
307 env->CP0_BadVAddr = arg2; \
308 helper_raise_exception(env, EXCP_AdES); \
309 } \
310 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
311 tmp = do_##ld_insn(env, arg2, mem_idx); \
312 if (tmp == env->llval) { \
313 do_##st_insn(env, arg2, arg1, mem_idx); \
314 return 1; \
315 } \
316 } \
317 return 0; \
318 }
319 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
320 #ifdef TARGET_MIPS64
321 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
322 #endif
323 #undef HELPER_ST_ATOMIC
324 #endif
325
326 #ifdef TARGET_WORDS_BIGENDIAN
327 #define GET_LMASK(v) ((v) & 3)
328 #define GET_OFFSET(addr, offset) (addr + (offset))
329 #else
330 #define GET_LMASK(v) (((v) & 3) ^ 3)
331 #define GET_OFFSET(addr, offset) (addr - (offset))
332 #endif
333
334 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
335 int mem_idx)
336 {
337 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
338
339 if (GET_LMASK(arg2) <= 2)
340 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
341
342 if (GET_LMASK(arg2) <= 1)
343 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
344
345 if (GET_LMASK(arg2) == 0)
346 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
347 }
348
349 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
350 int mem_idx)
351 {
352 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
353
354 if (GET_LMASK(arg2) >= 1)
355 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
356
357 if (GET_LMASK(arg2) >= 2)
358 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
359
360 if (GET_LMASK(arg2) == 3)
361 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
362 }
363
364 #if defined(TARGET_MIPS64)
365 /* "half" load and stores. We must do the memory access inline,
366 or fault handling won't work. */
367
368 #ifdef TARGET_WORDS_BIGENDIAN
369 #define GET_LMASK64(v) ((v) & 7)
370 #else
371 #define GET_LMASK64(v) (((v) & 7) ^ 7)
372 #endif
373
374 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
375 int mem_idx)
376 {
377 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
378
379 if (GET_LMASK64(arg2) <= 6)
380 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
381
382 if (GET_LMASK64(arg2) <= 5)
383 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
384
385 if (GET_LMASK64(arg2) <= 4)
386 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
387
388 if (GET_LMASK64(arg2) <= 3)
389 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
390
391 if (GET_LMASK64(arg2) <= 2)
392 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
393
394 if (GET_LMASK64(arg2) <= 1)
395 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
396
397 if (GET_LMASK64(arg2) <= 0)
398 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
399 }
400
401 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
402 int mem_idx)
403 {
404 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
405
406 if (GET_LMASK64(arg2) >= 1)
407 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
408
409 if (GET_LMASK64(arg2) >= 2)
410 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
411
412 if (GET_LMASK64(arg2) >= 3)
413 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
414
415 if (GET_LMASK64(arg2) >= 4)
416 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
417
418 if (GET_LMASK64(arg2) >= 5)
419 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
420
421 if (GET_LMASK64(arg2) >= 6)
422 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
423
424 if (GET_LMASK64(arg2) == 7)
425 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
426 }
427 #endif /* TARGET_MIPS64 */
428
429 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
430
431 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
432 uint32_t mem_idx)
433 {
434 target_ulong base_reglist = reglist & 0xf;
435 target_ulong do_r31 = reglist & 0x10;
436
437 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
438 target_ulong i;
439
440 for (i = 0; i < base_reglist; i++) {
441 env->active_tc.gpr[multiple_regs[i]] =
442 (target_long)do_lw(env, addr, mem_idx);
443 addr += 4;
444 }
445 }
446
447 if (do_r31) {
448 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
449 }
450 }
451
452 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
453 uint32_t mem_idx)
454 {
455 target_ulong base_reglist = reglist & 0xf;
456 target_ulong do_r31 = reglist & 0x10;
457
458 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
459 target_ulong i;
460
461 for (i = 0; i < base_reglist; i++) {
462 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
463 addr += 4;
464 }
465 }
466
467 if (do_r31) {
468 do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
469 }
470 }
471
472 #if defined(TARGET_MIPS64)
473 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
474 uint32_t mem_idx)
475 {
476 target_ulong base_reglist = reglist & 0xf;
477 target_ulong do_r31 = reglist & 0x10;
478
479 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
480 target_ulong i;
481
482 for (i = 0; i < base_reglist; i++) {
483 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
484 addr += 8;
485 }
486 }
487
488 if (do_r31) {
489 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
490 }
491 }
492
493 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
494 uint32_t mem_idx)
495 {
496 target_ulong base_reglist = reglist & 0xf;
497 target_ulong do_r31 = reglist & 0x10;
498
499 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
500 target_ulong i;
501
502 for (i = 0; i < base_reglist; i++) {
503 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
504 addr += 8;
505 }
506 }
507
508 if (do_r31) {
509 do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
510 }
511 }
512 #endif
513
514 #ifndef CONFIG_USER_ONLY
515 /* SMP helpers. */
516 static bool mips_vpe_is_wfi(MIPSCPU *c)
517 {
518 CPUMIPSState *env = &c->env;
519
520 /* If the VPE is halted but otherwise active, it means it's waiting for
521 an interrupt. */
522 return env->halted && mips_vpe_active(env);
523 }
524
525 static inline void mips_vpe_wake(CPUMIPSState *c)
526 {
527 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
528 because there might be other conditions that state that c should
529 be sleeping. */
530 cpu_interrupt(c, CPU_INTERRUPT_WAKE);
531 }
532
533 static inline void mips_vpe_sleep(MIPSCPU *cpu)
534 {
535 CPUMIPSState *c = &cpu->env;
536
537 /* The VPE was shut off, really go to bed.
538 Reset any old _WAKE requests. */
539 c->halted = 1;
540 cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
541 }
542
543 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
544 {
545 CPUMIPSState *c = &cpu->env;
546
547 /* FIXME: TC reschedule. */
548 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
549 mips_vpe_wake(c);
550 }
551 }
552
553 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
554 {
555 CPUMIPSState *c = &cpu->env;
556
557 /* FIXME: TC reschedule. */
558 if (!mips_vpe_active(c)) {
559 mips_vpe_sleep(cpu);
560 }
561 }
562
563 /**
564 * mips_cpu_map_tc:
565 * @env: CPU from which mapping is performed.
566 * @tc: Should point to an int with the value of the global TC index.
567 *
568 * This function will transform @tc into a local index within the
569 * returned #CPUMIPSState.
570 */
571 /* FIXME: This code assumes that all VPEs have the same number of TCs,
572 which depends on runtime setup. Can probably be fixed by
573 walking the list of CPUMIPSStates. */
574 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
575 {
576 MIPSCPU *cpu;
577 CPUState *cs;
578 CPUState *other_cs;
579 int vpe_idx;
580 int tc_idx = *tc;
581
582 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
583 /* Not allowed to address other CPUs. */
584 *tc = env->current_tc;
585 return env;
586 }
587
588 cs = CPU(mips_env_get_cpu(env));
589 vpe_idx = tc_idx / cs->nr_threads;
590 *tc = tc_idx % cs->nr_threads;
591 other_cs = qemu_get_cpu(vpe_idx);
592 if (other_cs == NULL) {
593 return env;
594 }
595 cpu = MIPS_CPU(other_cs);
596 return &cpu->env;
597 }
598
599 /* The per VPE CP0_Status register shares some fields with the per TC
600 CP0_TCStatus registers. These fields are wired to the same registers,
601 so changes to either of them should be reflected on both registers.
602
603 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
604
605 These helper call synchronizes the regs for a given cpu. */
606
607 /* Called for updates to CP0_Status. */
608 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
609 {
610 int32_t tcstatus, *tcst;
611 uint32_t v = cpu->CP0_Status;
612 uint32_t cu, mx, asid, ksu;
613 uint32_t mask = ((1 << CP0TCSt_TCU3)
614 | (1 << CP0TCSt_TCU2)
615 | (1 << CP0TCSt_TCU1)
616 | (1 << CP0TCSt_TCU0)
617 | (1 << CP0TCSt_TMX)
618 | (3 << CP0TCSt_TKSU)
619 | (0xff << CP0TCSt_TASID));
620
621 cu = (v >> CP0St_CU0) & 0xf;
622 mx = (v >> CP0St_MX) & 0x1;
623 ksu = (v >> CP0St_KSU) & 0x3;
624 asid = env->CP0_EntryHi & 0xff;
625
626 tcstatus = cu << CP0TCSt_TCU0;
627 tcstatus |= mx << CP0TCSt_TMX;
628 tcstatus |= ksu << CP0TCSt_TKSU;
629 tcstatus |= asid;
630
631 if (tc == cpu->current_tc) {
632 tcst = &cpu->active_tc.CP0_TCStatus;
633 } else {
634 tcst = &cpu->tcs[tc].CP0_TCStatus;
635 }
636
637 *tcst &= ~mask;
638 *tcst |= tcstatus;
639 compute_hflags(cpu);
640 }
641
642 /* Called for updates to CP0_TCStatus. */
643 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
644 target_ulong v)
645 {
646 uint32_t status;
647 uint32_t tcu, tmx, tasid, tksu;
648 uint32_t mask = ((1 << CP0St_CU3)
649 | (1 << CP0St_CU2)
650 | (1 << CP0St_CU1)
651 | (1 << CP0St_CU0)
652 | (1 << CP0St_MX)
653 | (3 << CP0St_KSU));
654
655 tcu = (v >> CP0TCSt_TCU0) & 0xf;
656 tmx = (v >> CP0TCSt_TMX) & 0x1;
657 tasid = v & 0xff;
658 tksu = (v >> CP0TCSt_TKSU) & 0x3;
659
660 status = tcu << CP0St_CU0;
661 status |= tmx << CP0St_MX;
662 status |= tksu << CP0St_KSU;
663
664 cpu->CP0_Status &= ~mask;
665 cpu->CP0_Status |= status;
666
667 /* Sync the TASID with EntryHi. */
668 cpu->CP0_EntryHi &= ~0xff;
669 cpu->CP0_EntryHi = tasid;
670
671 compute_hflags(cpu);
672 }
673
674 /* Called for updates to CP0_EntryHi. */
675 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
676 {
677 int32_t *tcst;
678 uint32_t asid, v = cpu->CP0_EntryHi;
679
680 asid = v & 0xff;
681
682 if (tc == cpu->current_tc) {
683 tcst = &cpu->active_tc.CP0_TCStatus;
684 } else {
685 tcst = &cpu->tcs[tc].CP0_TCStatus;
686 }
687
688 *tcst &= ~0xff;
689 *tcst |= asid;
690 }
691
692 /* CP0 helpers */
693 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
694 {
695 return env->mvp->CP0_MVPControl;
696 }
697
698 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
699 {
700 return env->mvp->CP0_MVPConf0;
701 }
702
703 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
704 {
705 return env->mvp->CP0_MVPConf1;
706 }
707
708 target_ulong helper_mfc0_random(CPUMIPSState *env)
709 {
710 return (int32_t)cpu_mips_get_random(env);
711 }
712
713 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
714 {
715 return env->active_tc.CP0_TCStatus;
716 }
717
718 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
719 {
720 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
721 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
722
723 if (other_tc == other->current_tc)
724 return other->active_tc.CP0_TCStatus;
725 else
726 return other->tcs[other_tc].CP0_TCStatus;
727 }
728
729 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
730 {
731 return env->active_tc.CP0_TCBind;
732 }
733
734 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
735 {
736 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
737 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
738
739 if (other_tc == other->current_tc)
740 return other->active_tc.CP0_TCBind;
741 else
742 return other->tcs[other_tc].CP0_TCBind;
743 }
744
745 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
746 {
747 return env->active_tc.PC;
748 }
749
750 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
751 {
752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
753 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
754
755 if (other_tc == other->current_tc)
756 return other->active_tc.PC;
757 else
758 return other->tcs[other_tc].PC;
759 }
760
761 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
762 {
763 return env->active_tc.CP0_TCHalt;
764 }
765
766 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
767 {
768 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
769 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
770
771 if (other_tc == other->current_tc)
772 return other->active_tc.CP0_TCHalt;
773 else
774 return other->tcs[other_tc].CP0_TCHalt;
775 }
776
777 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
778 {
779 return env->active_tc.CP0_TCContext;
780 }
781
782 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
783 {
784 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
785 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
786
787 if (other_tc == other->current_tc)
788 return other->active_tc.CP0_TCContext;
789 else
790 return other->tcs[other_tc].CP0_TCContext;
791 }
792
793 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
794 {
795 return env->active_tc.CP0_TCSchedule;
796 }
797
798 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
799 {
800 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
801 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
802
803 if (other_tc == other->current_tc)
804 return other->active_tc.CP0_TCSchedule;
805 else
806 return other->tcs[other_tc].CP0_TCSchedule;
807 }
808
809 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
810 {
811 return env->active_tc.CP0_TCScheFBack;
812 }
813
814 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
815 {
816 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
817 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
818
819 if (other_tc == other->current_tc)
820 return other->active_tc.CP0_TCScheFBack;
821 else
822 return other->tcs[other_tc].CP0_TCScheFBack;
823 }
824
825 target_ulong helper_mfc0_count(CPUMIPSState *env)
826 {
827 return (int32_t)cpu_mips_get_count(env);
828 }
829
830 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
831 {
832 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
833 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
834
835 return other->CP0_EntryHi;
836 }
837
838 target_ulong helper_mftc0_cause(CPUMIPSState *env)
839 {
840 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
841 int32_t tccause;
842 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
843
844 if (other_tc == other->current_tc) {
845 tccause = other->CP0_Cause;
846 } else {
847 tccause = other->CP0_Cause;
848 }
849
850 return tccause;
851 }
852
853 target_ulong helper_mftc0_status(CPUMIPSState *env)
854 {
855 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
856 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
857
858 return other->CP0_Status;
859 }
860
861 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
862 {
863 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
864 }
865
866 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
867 {
868 return (int32_t)env->CP0_WatchLo[sel];
869 }
870
871 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
872 {
873 return env->CP0_WatchHi[sel];
874 }
875
876 target_ulong helper_mfc0_debug(CPUMIPSState *env)
877 {
878 target_ulong t0 = env->CP0_Debug;
879 if (env->hflags & MIPS_HFLAG_DM)
880 t0 |= 1 << CP0DB_DM;
881
882 return t0;
883 }
884
885 target_ulong helper_mftc0_debug(CPUMIPSState *env)
886 {
887 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
888 int32_t tcstatus;
889 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
890
891 if (other_tc == other->current_tc)
892 tcstatus = other->active_tc.CP0_Debug_tcstatus;
893 else
894 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
895
896 /* XXX: Might be wrong, check with EJTAG spec. */
897 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
898 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
899 }
900
901 #if defined(TARGET_MIPS64)
902 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
903 {
904 return env->active_tc.PC;
905 }
906
907 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
908 {
909 return env->active_tc.CP0_TCHalt;
910 }
911
912 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
913 {
914 return env->active_tc.CP0_TCContext;
915 }
916
917 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
918 {
919 return env->active_tc.CP0_TCSchedule;
920 }
921
922 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
923 {
924 return env->active_tc.CP0_TCScheFBack;
925 }
926
927 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
928 {
929 return env->lladdr >> env->CP0_LLAddr_shift;
930 }
931
932 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
933 {
934 return env->CP0_WatchLo[sel];
935 }
936 #endif /* TARGET_MIPS64 */
937
938 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
939 {
940 int num = 1;
941 unsigned int tmp = env->tlb->nb_tlb;
942
943 do {
944 tmp >>= 1;
945 num <<= 1;
946 } while (tmp);
947 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
948 }
949
950 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
951 {
952 uint32_t mask = 0;
953 uint32_t newval;
954
955 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
956 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
957 (1 << CP0MVPCo_EVP);
958 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
959 mask |= (1 << CP0MVPCo_STLB);
960 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
961
962 // TODO: Enable/disable shared TLB, enable/disable VPEs.
963
964 env->mvp->CP0_MVPControl = newval;
965 }
966
967 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
968 {
969 uint32_t mask;
970 uint32_t newval;
971
972 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
973 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
974 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
975
976 /* Yield scheduler intercept not implemented. */
977 /* Gating storage scheduler intercept not implemented. */
978
979 // TODO: Enable/disable TCs.
980
981 env->CP0_VPEControl = newval;
982 }
983
984 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
985 {
986 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
987 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
988 uint32_t mask;
989 uint32_t newval;
990
991 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
992 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
993 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
994
995 /* TODO: Enable/disable TCs. */
996
997 other->CP0_VPEControl = newval;
998 }
999
1000 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1001 {
1002 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1003 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1004 /* FIXME: Mask away return zero on read bits. */
1005 return other->CP0_VPEControl;
1006 }
1007
1008 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1009 {
1010 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1011 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1012
1013 return other->CP0_VPEConf0;
1014 }
1015
1016 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1017 {
1018 uint32_t mask = 0;
1019 uint32_t newval;
1020
1021 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1022 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1023 mask |= (0xff << CP0VPEC0_XTC);
1024 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1025 }
1026 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1027
1028 // TODO: TC exclusive handling due to ERL/EXL.
1029
1030 env->CP0_VPEConf0 = newval;
1031 }
1032
1033 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1034 {
1035 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1036 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1037 uint32_t mask = 0;
1038 uint32_t newval;
1039
1040 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1041 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1042
1043 /* TODO: TC exclusive handling due to ERL/EXL. */
1044 other->CP0_VPEConf0 = newval;
1045 }
1046
1047 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1048 {
1049 uint32_t mask = 0;
1050 uint32_t newval;
1051
1052 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1053 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1054 (0xff << CP0VPEC1_NCP1);
1055 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1056
1057 /* UDI not implemented. */
1058 /* CP2 not implemented. */
1059
1060 // TODO: Handle FPU (CP1) binding.
1061
1062 env->CP0_VPEConf1 = newval;
1063 }
1064
1065 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1066 {
1067 /* Yield qualifier inputs not implemented. */
1068 env->CP0_YQMask = 0x00000000;
1069 }
1070
1071 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1072 {
1073 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1074 }
1075
1076 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1077 {
1078 /* Large physaddr (PABITS) not implemented */
1079 /* 1k pages not implemented */
1080 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1081 }
1082
1083 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1084 {
1085 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1086 uint32_t newval;
1087
1088 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1089
1090 env->active_tc.CP0_TCStatus = newval;
1091 sync_c0_tcstatus(env, env->current_tc, newval);
1092 }
1093
1094 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1095 {
1096 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1097 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1098
1099 if (other_tc == other->current_tc)
1100 other->active_tc.CP0_TCStatus = arg1;
1101 else
1102 other->tcs[other_tc].CP0_TCStatus = arg1;
1103 sync_c0_tcstatus(other, other_tc, arg1);
1104 }
1105
1106 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1107 {
1108 uint32_t mask = (1 << CP0TCBd_TBE);
1109 uint32_t newval;
1110
1111 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1112 mask |= (1 << CP0TCBd_CurVPE);
1113 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1114 env->active_tc.CP0_TCBind = newval;
1115 }
1116
1117 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1118 {
1119 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1120 uint32_t mask = (1 << CP0TCBd_TBE);
1121 uint32_t newval;
1122 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1123
1124 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1125 mask |= (1 << CP0TCBd_CurVPE);
1126 if (other_tc == other->current_tc) {
1127 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1128 other->active_tc.CP0_TCBind = newval;
1129 } else {
1130 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1131 other->tcs[other_tc].CP0_TCBind = newval;
1132 }
1133 }
1134
1135 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1136 {
1137 env->active_tc.PC = arg1;
1138 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1139 env->lladdr = 0ULL;
1140 /* MIPS16 not implemented. */
1141 }
1142
1143 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1144 {
1145 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1146 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1147
1148 if (other_tc == other->current_tc) {
1149 other->active_tc.PC = arg1;
1150 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1151 other->lladdr = 0ULL;
1152 /* MIPS16 not implemented. */
1153 } else {
1154 other->tcs[other_tc].PC = arg1;
1155 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1156 other->lladdr = 0ULL;
1157 /* MIPS16 not implemented. */
1158 }
1159 }
1160
1161 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1162 {
1163 MIPSCPU *cpu = mips_env_get_cpu(env);
1164
1165 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1166
1167 // TODO: Halt TC / Restart (if allocated+active) TC.
1168 if (env->active_tc.CP0_TCHalt & 1) {
1169 mips_tc_sleep(cpu, env->current_tc);
1170 } else {
1171 mips_tc_wake(cpu, env->current_tc);
1172 }
1173 }
1174
1175 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1176 {
1177 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1178 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1179 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1180
1181 // TODO: Halt TC / Restart (if allocated+active) TC.
1182
1183 if (other_tc == other->current_tc)
1184 other->active_tc.CP0_TCHalt = arg1;
1185 else
1186 other->tcs[other_tc].CP0_TCHalt = arg1;
1187
1188 if (arg1 & 1) {
1189 mips_tc_sleep(other_cpu, other_tc);
1190 } else {
1191 mips_tc_wake(other_cpu, other_tc);
1192 }
1193 }
1194
1195 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1196 {
1197 env->active_tc.CP0_TCContext = arg1;
1198 }
1199
1200 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1201 {
1202 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1203 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1204
1205 if (other_tc == other->current_tc)
1206 other->active_tc.CP0_TCContext = arg1;
1207 else
1208 other->tcs[other_tc].CP0_TCContext = arg1;
1209 }
1210
1211 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1212 {
1213 env->active_tc.CP0_TCSchedule = arg1;
1214 }
1215
1216 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1217 {
1218 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1219 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1220
1221 if (other_tc == other->current_tc)
1222 other->active_tc.CP0_TCSchedule = arg1;
1223 else
1224 other->tcs[other_tc].CP0_TCSchedule = arg1;
1225 }
1226
1227 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1228 {
1229 env->active_tc.CP0_TCScheFBack = arg1;
1230 }
1231
1232 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1233 {
1234 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1235 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1236
1237 if (other_tc == other->current_tc)
1238 other->active_tc.CP0_TCScheFBack = arg1;
1239 else
1240 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1241 }
1242
1243 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1244 {
1245 /* Large physaddr (PABITS) not implemented */
1246 /* 1k pages not implemented */
1247 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1248 }
1249
1250 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1251 {
1252 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1253 }
1254
1255 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1256 {
1257 /* 1k pages not implemented */
1258 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1259 }
1260
1261 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1262 {
1263 /* SmartMIPS not implemented */
1264 /* Large physaddr (PABITS) not implemented */
1265 /* 1k pages not implemented */
1266 env->CP0_PageGrain = 0;
1267 }
1268
1269 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1270 {
1271 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1272 }
1273
1274 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1275 {
1276 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1277 }
1278
1279 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1280 {
1281 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1282 }
1283
1284 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1285 {
1286 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1287 }
1288
1289 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1290 {
1291 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1292 }
1293
1294 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1295 {
1296 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1297 }
1298
1299 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1300 {
1301 env->CP0_HWREna = arg1 & 0x0000000F;
1302 }
1303
1304 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1305 {
1306 cpu_mips_store_count(env, arg1);
1307 }
1308
1309 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1310 {
1311 target_ulong old, val;
1312
1313 /* 1k pages not implemented */
1314 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1315 #if defined(TARGET_MIPS64)
1316 val &= env->SEGMask;
1317 #endif
1318 old = env->CP0_EntryHi;
1319 env->CP0_EntryHi = val;
1320 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1321 sync_c0_entryhi(env, env->current_tc);
1322 }
1323 /* If the ASID changes, flush qemu's TLB. */
1324 if ((old & 0xFF) != (val & 0xFF))
1325 cpu_mips_tlb_flush(env, 1);
1326 }
1327
1328 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1329 {
1330 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1331 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1332
1333 other->CP0_EntryHi = arg1;
1334 sync_c0_entryhi(other, other_tc);
1335 }
1336
1337 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1338 {
1339 cpu_mips_store_compare(env, arg1);
1340 }
1341
1342 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1343 {
1344 uint32_t val, old;
1345 uint32_t mask = env->CP0_Status_rw_bitmask;
1346
1347 val = arg1 & mask;
1348 old = env->CP0_Status;
1349 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1350 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1351 sync_c0_status(env, env, env->current_tc);
1352 } else {
1353 compute_hflags(env);
1354 }
1355
1356 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1357 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1358 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1359 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1360 env->CP0_Cause);
1361 switch (env->hflags & MIPS_HFLAG_KSU) {
1362 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1363 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1364 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1365 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1366 }
1367 }
1368 }
1369
1370 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1371 {
1372 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1373 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1374
1375 other->CP0_Status = arg1 & ~0xf1000018;
1376 sync_c0_status(env, other, other_tc);
1377 }
1378
1379 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1380 {
1381 /* vectored interrupts not implemented, no performance counters. */
1382 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1383 }
1384
1385 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1386 {
1387 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1388 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1389 }
1390
1391 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1392 {
1393 uint32_t mask = 0x00C00300;
1394 uint32_t old = cpu->CP0_Cause;
1395 int i;
1396
1397 if (cpu->insn_flags & ISA_MIPS32R2) {
1398 mask |= 1 << CP0Ca_DC;
1399 }
1400
1401 cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1402
1403 if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1404 if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1405 cpu_mips_stop_count(cpu);
1406 } else {
1407 cpu_mips_start_count(cpu);
1408 }
1409 }
1410
1411 /* Set/reset software interrupts */
1412 for (i = 0 ; i < 2 ; i++) {
1413 if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1414 cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1415 }
1416 }
1417 }
1418
1419 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1420 {
1421 mtc0_cause(env, arg1);
1422 }
1423
1424 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1425 {
1426 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1427 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1428
1429 mtc0_cause(other, arg1);
1430 }
1431
1432 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1433 {
1434 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1435 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1436
1437 return other->CP0_EPC;
1438 }
1439
1440 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1441 {
1442 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1443 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1444
1445 return other->CP0_EBase;
1446 }
1447
1448 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1449 {
1450 /* vectored interrupts not implemented */
1451 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1452 }
1453
1454 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1455 {
1456 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1457 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1458 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1459 }
1460
1461 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1462 {
1463 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1464 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1465
1466 switch (idx) {
1467 case 0: return other->CP0_Config0;
1468 case 1: return other->CP0_Config1;
1469 case 2: return other->CP0_Config2;
1470 case 3: return other->CP0_Config3;
1471 /* 4 and 5 are reserved. */
1472 case 6: return other->CP0_Config6;
1473 case 7: return other->CP0_Config7;
1474 default:
1475 break;
1476 }
1477 return 0;
1478 }
1479
1480 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1481 {
1482 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1483 }
1484
1485 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1486 {
1487 /* tertiary/secondary caches not implemented */
1488 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1489 }
1490
1491 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1492 {
1493 target_long mask = env->CP0_LLAddr_rw_bitmask;
1494 arg1 = arg1 << env->CP0_LLAddr_shift;
1495 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1496 }
1497
1498 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1499 {
1500 /* Watch exceptions for instructions, data loads, data stores
1501 not implemented. */
1502 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1503 }
1504
1505 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1506 {
1507 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1508 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1509 }
1510
1511 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1512 {
1513 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1514 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1515 }
1516
1517 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1518 {
1519 env->CP0_Framemask = arg1; /* XXX */
1520 }
1521
1522 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1523 {
1524 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1525 if (arg1 & (1 << CP0DB_DM))
1526 env->hflags |= MIPS_HFLAG_DM;
1527 else
1528 env->hflags &= ~MIPS_HFLAG_DM;
1529 }
1530
1531 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1532 {
1533 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1534 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1535 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1536
1537 /* XXX: Might be wrong, check with EJTAG spec. */
1538 if (other_tc == other->current_tc)
1539 other->active_tc.CP0_Debug_tcstatus = val;
1540 else
1541 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1542 other->CP0_Debug = (other->CP0_Debug &
1543 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1544 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1545 }
1546
1547 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1548 {
1549 env->CP0_Performance0 = arg1 & 0x000007ff;
1550 }
1551
1552 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1553 {
1554 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1555 }
1556
1557 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1558 {
1559 env->CP0_DataLo = arg1; /* XXX */
1560 }
1561
1562 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1563 {
1564 env->CP0_TagHi = arg1; /* XXX */
1565 }
1566
1567 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1568 {
1569 env->CP0_DataHi = arg1; /* XXX */
1570 }
1571
1572 /* MIPS MT functions */
1573 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1574 {
1575 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1576 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1577
1578 if (other_tc == other->current_tc)
1579 return other->active_tc.gpr[sel];
1580 else
1581 return other->tcs[other_tc].gpr[sel];
1582 }
1583
1584 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1585 {
1586 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1587 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1588
1589 if (other_tc == other->current_tc)
1590 return other->active_tc.LO[sel];
1591 else
1592 return other->tcs[other_tc].LO[sel];
1593 }
1594
1595 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1596 {
1597 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1598 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1599
1600 if (other_tc == other->current_tc)
1601 return other->active_tc.HI[sel];
1602 else
1603 return other->tcs[other_tc].HI[sel];
1604 }
1605
1606 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1607 {
1608 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1609 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1610
1611 if (other_tc == other->current_tc)
1612 return other->active_tc.ACX[sel];
1613 else
1614 return other->tcs[other_tc].ACX[sel];
1615 }
1616
1617 target_ulong helper_mftdsp(CPUMIPSState *env)
1618 {
1619 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1620 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1621
1622 if (other_tc == other->current_tc)
1623 return other->active_tc.DSPControl;
1624 else
1625 return other->tcs[other_tc].DSPControl;
1626 }
1627
1628 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1629 {
1630 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1631 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1632
1633 if (other_tc == other->current_tc)
1634 other->active_tc.gpr[sel] = arg1;
1635 else
1636 other->tcs[other_tc].gpr[sel] = arg1;
1637 }
1638
1639 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1640 {
1641 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1642 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1643
1644 if (other_tc == other->current_tc)
1645 other->active_tc.LO[sel] = arg1;
1646 else
1647 other->tcs[other_tc].LO[sel] = arg1;
1648 }
1649
1650 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1651 {
1652 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1653 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1654
1655 if (other_tc == other->current_tc)
1656 other->active_tc.HI[sel] = arg1;
1657 else
1658 other->tcs[other_tc].HI[sel] = arg1;
1659 }
1660
1661 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1662 {
1663 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1664 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1665
1666 if (other_tc == other->current_tc)
1667 other->active_tc.ACX[sel] = arg1;
1668 else
1669 other->tcs[other_tc].ACX[sel] = arg1;
1670 }
1671
1672 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1673 {
1674 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1675 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1676
1677 if (other_tc == other->current_tc)
1678 other->active_tc.DSPControl = arg1;
1679 else
1680 other->tcs[other_tc].DSPControl = arg1;
1681 }
1682
1683 /* MIPS MT functions */
1684 target_ulong helper_dmt(void)
1685 {
1686 // TODO
1687 return 0;
1688 }
1689
1690 target_ulong helper_emt(void)
1691 {
1692 // TODO
1693 return 0;
1694 }
1695
1696 target_ulong helper_dvpe(CPUMIPSState *env)
1697 {
1698 CPUMIPSState *other_cpu_env = first_cpu;
1699 target_ulong prev = env->mvp->CP0_MVPControl;
1700
1701 do {
1702 /* Turn off all VPEs except the one executing the dvpe. */
1703 if (other_cpu_env != env) {
1704 MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1705
1706 other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1707 mips_vpe_sleep(other_cpu);
1708 }
1709 other_cpu_env = other_cpu_env->next_cpu;
1710 } while (other_cpu_env);
1711 return prev;
1712 }
1713
1714 target_ulong helper_evpe(CPUMIPSState *env)
1715 {
1716 CPUMIPSState *other_cpu_env = first_cpu;
1717 target_ulong prev = env->mvp->CP0_MVPControl;
1718
1719 do {
1720 MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1721
1722 if (other_cpu_env != env
1723 /* If the VPE is WFI, don't disturb its sleep. */
1724 && !mips_vpe_is_wfi(other_cpu)) {
1725 /* Enable the VPE. */
1726 other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1727 mips_vpe_wake(other_cpu_env); /* And wake it up. */
1728 }
1729 other_cpu_env = other_cpu_env->next_cpu;
1730 } while (other_cpu_env);
1731 return prev;
1732 }
1733 #endif /* !CONFIG_USER_ONLY */
1734
1735 void helper_fork(target_ulong arg1, target_ulong arg2)
1736 {
1737 // arg1 = rt, arg2 = rs
1738 arg1 = 0;
1739 // TODO: store to TC register
1740 }
1741
1742 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1743 {
1744 target_long arg1 = arg;
1745
1746 if (arg1 < 0) {
1747 /* No scheduling policy implemented. */
1748 if (arg1 != -2) {
1749 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1750 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1751 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1752 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1753 helper_raise_exception(env, EXCP_THREAD);
1754 }
1755 }
1756 } else if (arg1 == 0) {
1757 if (0 /* TODO: TC underflow */) {
1758 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1759 helper_raise_exception(env, EXCP_THREAD);
1760 } else {
1761 // TODO: Deallocate TC
1762 }
1763 } else if (arg1 > 0) {
1764 /* Yield qualifier inputs not implemented. */
1765 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1766 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1767 helper_raise_exception(env, EXCP_THREAD);
1768 }
1769 return env->CP0_YQMask;
1770 }
1771
1772 #ifndef CONFIG_USER_ONLY
1773 /* TLB management */
1774 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1775 {
1776 /* Flush qemu's TLB and discard all shadowed entries. */
1777 tlb_flush (env, flush_global);
1778 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1779 }
1780
1781 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1782 {
1783 /* Discard entries from env->tlb[first] onwards. */
1784 while (env->tlb->tlb_in_use > first) {
1785 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1786 }
1787 }
1788
1789 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1790 {
1791 r4k_tlb_t *tlb;
1792
1793 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1794 tlb = &env->tlb->mmu.r4k.tlb[idx];
1795 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1796 #if defined(TARGET_MIPS64)
1797 tlb->VPN &= env->SEGMask;
1798 #endif
1799 tlb->ASID = env->CP0_EntryHi & 0xFF;
1800 tlb->PageMask = env->CP0_PageMask;
1801 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1802 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1803 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1804 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1805 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1806 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1807 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1808 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1809 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1810 }
1811
1812 void r4k_helper_tlbwi(CPUMIPSState *env)
1813 {
1814 r4k_tlb_t *tlb;
1815 int idx;
1816 target_ulong VPN;
1817 uint8_t ASID;
1818 bool G, V0, D0, V1, D1;
1819
1820 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1821 tlb = &env->tlb->mmu.r4k.tlb[idx];
1822 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1823 #if defined(TARGET_MIPS64)
1824 VPN &= env->SEGMask;
1825 #endif
1826 ASID = env->CP0_EntryHi & 0xff;
1827 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1828 V0 = (env->CP0_EntryLo0 & 2) != 0;
1829 D0 = (env->CP0_EntryLo0 & 4) != 0;
1830 V1 = (env->CP0_EntryLo1 & 2) != 0;
1831 D1 = (env->CP0_EntryLo1 & 4) != 0;
1832
1833 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1834 permissions on the current entry. */
1835 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1836 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1837 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1838 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1839 }
1840
1841 r4k_invalidate_tlb(env, idx, 0);
1842 r4k_fill_tlb(env, idx);
1843 }
1844
1845 void r4k_helper_tlbwr(CPUMIPSState *env)
1846 {
1847 int r = cpu_mips_get_random(env);
1848
1849 r4k_invalidate_tlb(env, r, 1);
1850 r4k_fill_tlb(env, r);
1851 }
1852
1853 void r4k_helper_tlbp(CPUMIPSState *env)
1854 {
1855 r4k_tlb_t *tlb;
1856 target_ulong mask;
1857 target_ulong tag;
1858 target_ulong VPN;
1859 uint8_t ASID;
1860 int i;
1861
1862 ASID = env->CP0_EntryHi & 0xFF;
1863 for (i = 0; i < env->tlb->nb_tlb; i++) {
1864 tlb = &env->tlb->mmu.r4k.tlb[i];
1865 /* 1k pages are not supported. */
1866 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1867 tag = env->CP0_EntryHi & ~mask;
1868 VPN = tlb->VPN & ~mask;
1869 #if defined(TARGET_MIPS64)
1870 tag &= env->SEGMask;
1871 #endif
1872 /* Check ASID, virtual page number & size */
1873 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1874 /* TLB match */
1875 env->CP0_Index = i;
1876 break;
1877 }
1878 }
1879 if (i == env->tlb->nb_tlb) {
1880 /* No match. Discard any shadow entries, if any of them match. */
1881 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1882 tlb = &env->tlb->mmu.r4k.tlb[i];
1883 /* 1k pages are not supported. */
1884 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1885 tag = env->CP0_EntryHi & ~mask;
1886 VPN = tlb->VPN & ~mask;
1887 #if defined(TARGET_MIPS64)
1888 tag &= env->SEGMask;
1889 #endif
1890 /* Check ASID, virtual page number & size */
1891 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1892 r4k_mips_tlb_flush_extra (env, i);
1893 break;
1894 }
1895 }
1896
1897 env->CP0_Index |= 0x80000000;
1898 }
1899 }
1900
1901 void r4k_helper_tlbr(CPUMIPSState *env)
1902 {
1903 r4k_tlb_t *tlb;
1904 uint8_t ASID;
1905 int idx;
1906
1907 ASID = env->CP0_EntryHi & 0xFF;
1908 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1909 tlb = &env->tlb->mmu.r4k.tlb[idx];
1910
1911 /* If this will change the current ASID, flush qemu's TLB. */
1912 if (ASID != tlb->ASID)
1913 cpu_mips_tlb_flush (env, 1);
1914
1915 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1916
1917 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1918 env->CP0_PageMask = tlb->PageMask;
1919 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1920 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1921 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1922 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1923 }
1924
1925 void helper_tlbwi(CPUMIPSState *env)
1926 {
1927 env->tlb->helper_tlbwi(env);
1928 }
1929
1930 void helper_tlbwr(CPUMIPSState *env)
1931 {
1932 env->tlb->helper_tlbwr(env);
1933 }
1934
1935 void helper_tlbp(CPUMIPSState *env)
1936 {
1937 env->tlb->helper_tlbp(env);
1938 }
1939
1940 void helper_tlbr(CPUMIPSState *env)
1941 {
1942 env->tlb->helper_tlbr(env);
1943 }
1944
1945 /* Specials */
1946 target_ulong helper_di(CPUMIPSState *env)
1947 {
1948 target_ulong t0 = env->CP0_Status;
1949
1950 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1951 return t0;
1952 }
1953
1954 target_ulong helper_ei(CPUMIPSState *env)
1955 {
1956 target_ulong t0 = env->CP0_Status;
1957
1958 env->CP0_Status = t0 | (1 << CP0St_IE);
1959 return t0;
1960 }
1961
1962 static void debug_pre_eret(CPUMIPSState *env)
1963 {
1964 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1965 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1966 env->active_tc.PC, env->CP0_EPC);
1967 if (env->CP0_Status & (1 << CP0St_ERL))
1968 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1969 if (env->hflags & MIPS_HFLAG_DM)
1970 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1971 qemu_log("\n");
1972 }
1973 }
1974
1975 static void debug_post_eret(CPUMIPSState *env)
1976 {
1977 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1978 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1979 env->active_tc.PC, env->CP0_EPC);
1980 if (env->CP0_Status & (1 << CP0St_ERL))
1981 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1982 if (env->hflags & MIPS_HFLAG_DM)
1983 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1984 switch (env->hflags & MIPS_HFLAG_KSU) {
1985 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1986 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1987 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1988 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1989 }
1990 }
1991 }
1992
1993 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
1994 {
1995 env->active_tc.PC = error_pc & ~(target_ulong)1;
1996 if (error_pc & 1) {
1997 env->hflags |= MIPS_HFLAG_M16;
1998 } else {
1999 env->hflags &= ~(MIPS_HFLAG_M16);
2000 }
2001 }
2002
2003 void helper_eret(CPUMIPSState *env)
2004 {
2005 debug_pre_eret(env);
2006 if (env->CP0_Status & (1 << CP0St_ERL)) {
2007 set_pc(env, env->CP0_ErrorEPC);
2008 env->CP0_Status &= ~(1 << CP0St_ERL);
2009 } else {
2010 set_pc(env, env->CP0_EPC);
2011 env->CP0_Status &= ~(1 << CP0St_EXL);
2012 }
2013 compute_hflags(env);
2014 debug_post_eret(env);
2015 env->lladdr = 1;
2016 }
2017
2018 void helper_deret(CPUMIPSState *env)
2019 {
2020 debug_pre_eret(env);
2021 set_pc(env, env->CP0_DEPC);
2022
2023 env->hflags &= MIPS_HFLAG_DM;
2024 compute_hflags(env);
2025 debug_post_eret(env);
2026 env->lladdr = 1;
2027 }
2028 #endif /* !CONFIG_USER_ONLY */
2029
2030 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2031 {
2032 if ((env->hflags & MIPS_HFLAG_CP0) ||
2033 (env->CP0_HWREna & (1 << 0)))
2034 return env->CP0_EBase & 0x3ff;
2035 else
2036 helper_raise_exception(env, EXCP_RI);
2037
2038 return 0;
2039 }
2040
2041 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2042 {
2043 if ((env->hflags & MIPS_HFLAG_CP0) ||
2044 (env->CP0_HWREna & (1 << 1)))
2045 return env->SYNCI_Step;
2046 else
2047 helper_raise_exception(env, EXCP_RI);
2048
2049 return 0;
2050 }
2051
2052 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2053 {
2054 if ((env->hflags & MIPS_HFLAG_CP0) ||
2055 (env->CP0_HWREna & (1 << 2)))
2056 return env->CP0_Count;
2057 else
2058 helper_raise_exception(env, EXCP_RI);
2059
2060 return 0;
2061 }
2062
2063 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2064 {
2065 if ((env->hflags & MIPS_HFLAG_CP0) ||
2066 (env->CP0_HWREna & (1 << 3)))
2067 return env->CCRes;
2068 else
2069 helper_raise_exception(env, EXCP_RI);
2070
2071 return 0;
2072 }
2073
2074 void helper_pmon(CPUMIPSState *env, int function)
2075 {
2076 function /= 2;
2077 switch (function) {
2078 case 2: /* TODO: char inbyte(int waitflag); */
2079 if (env->active_tc.gpr[4] == 0)
2080 env->active_tc.gpr[2] = -1;
2081 /* Fall through */
2082 case 11: /* TODO: char inbyte (void); */
2083 env->active_tc.gpr[2] = -1;
2084 break;
2085 case 3:
2086 case 12:
2087 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2088 break;
2089 case 17:
2090 break;
2091 case 158:
2092 {
2093 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2094 printf("%s", fmt);
2095 }
2096 break;
2097 }
2098 }
2099
2100 void helper_wait(CPUMIPSState *env)
2101 {
2102 env->halted = 1;
2103 cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2104 helper_raise_exception(env, EXCP_HLT);
2105 }
2106
2107 #if !defined(CONFIG_USER_ONLY)
2108
2109 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2110 target_ulong addr, int is_write,
2111 int is_user, uintptr_t retaddr);
2112
2113 #define MMUSUFFIX _mmu
2114 #define ALIGNED_ONLY
2115
2116 #define SHIFT 0
2117 #include "exec/softmmu_template.h"
2118
2119 #define SHIFT 1
2120 #include "exec/softmmu_template.h"
2121
2122 #define SHIFT 2
2123 #include "exec/softmmu_template.h"
2124
2125 #define SHIFT 3
2126 #include "exec/softmmu_template.h"
2127
2128 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2129 int is_write, int is_user, uintptr_t retaddr)
2130 {
2131 env->CP0_BadVAddr = addr;
2132 do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2133 }
2134
2135 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2136 uintptr_t retaddr)
2137 {
2138 int ret;
2139
2140 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2141 if (ret) {
2142 do_raise_exception_err(env, env->exception_index,
2143 env->error_code, retaddr);
2144 }
2145 }
2146
2147 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
2148 int is_write, int is_exec, int unused, int size)
2149 {
2150 if (is_exec)
2151 helper_raise_exception(env, EXCP_IBE);
2152 else
2153 helper_raise_exception(env, EXCP_DBE);
2154 }
2155 #endif /* !CONFIG_USER_ONLY */
2156
2157 /* Complex FPU operations which may need stack space. */
2158
2159 #define FLOAT_TWO32 make_float32(1 << 30)
2160 #define FLOAT_TWO64 make_float64(1ULL << 62)
2161 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2162 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2163
2164 /* convert MIPS rounding mode in FCR31 to IEEE library */
2165 static unsigned int ieee_rm[] = {
2166 float_round_nearest_even,
2167 float_round_to_zero,
2168 float_round_up,
2169 float_round_down
2170 };
2171
2172 static inline void restore_rounding_mode(CPUMIPSState *env)
2173 {
2174 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2175 &env->active_fpu.fp_status);
2176 }
2177
2178 static inline void restore_flush_mode(CPUMIPSState *env)
2179 {
2180 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2181 &env->active_fpu.fp_status);
2182 }
2183
2184 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2185 {
2186 target_ulong arg1;
2187
2188 switch (reg) {
2189 case 0:
2190 arg1 = (int32_t)env->active_fpu.fcr0;
2191 break;
2192 case 25:
2193 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2194 break;
2195 case 26:
2196 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2197 break;
2198 case 28:
2199 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2200 break;
2201 default:
2202 arg1 = (int32_t)env->active_fpu.fcr31;
2203 break;
2204 }
2205
2206 return arg1;
2207 }
2208
2209 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2210 {
2211 switch(reg) {
2212 case 25:
2213 if (arg1 & 0xffffff00)
2214 return;
2215 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2216 ((arg1 & 0x1) << 23);
2217 break;
2218 case 26:
2219 if (arg1 & 0x007c0000)
2220 return;
2221 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2222 break;
2223 case 28:
2224 if (arg1 & 0x007c0000)
2225 return;
2226 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2227 ((arg1 & 0x4) << 22);
2228 break;
2229 case 31:
2230 if (arg1 & 0x007c0000)
2231 return;
2232 env->active_fpu.fcr31 = arg1;
2233 break;
2234 default:
2235 return;
2236 }
2237 /* set rounding mode */
2238 restore_rounding_mode(env);
2239 /* set flush-to-zero mode */
2240 restore_flush_mode(env);
2241 set_float_exception_flags(0, &env->active_fpu.fp_status);
2242 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2243 do_raise_exception(env, EXCP_FPE, GETPC());
2244 }
2245
2246 static inline int ieee_ex_to_mips(int xcpt)
2247 {
2248 int ret = 0;
2249 if (xcpt) {
2250 if (xcpt & float_flag_invalid) {
2251 ret |= FP_INVALID;
2252 }
2253 if (xcpt & float_flag_overflow) {
2254 ret |= FP_OVERFLOW;
2255 }
2256 if (xcpt & float_flag_underflow) {
2257 ret |= FP_UNDERFLOW;
2258 }
2259 if (xcpt & float_flag_divbyzero) {
2260 ret |= FP_DIV0;
2261 }
2262 if (xcpt & float_flag_inexact) {
2263 ret |= FP_INEXACT;
2264 }
2265 }
2266 return ret;
2267 }
2268
2269 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2270 {
2271 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2272
2273 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2274
2275 if (tmp) {
2276 set_float_exception_flags(0, &env->active_fpu.fp_status);
2277
2278 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2279 do_raise_exception(env, EXCP_FPE, pc);
2280 } else {
2281 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2282 }
2283 }
2284 }
2285
2286 /* Float support.
2287 Single precition routines have a "s" suffix, double precision a
2288 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2289 paired single lower "pl", paired single upper "pu". */
2290
2291 /* unary operations, modifying fp status */
2292 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2293 {
2294 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2295 update_fcr31(env, GETPC());
2296 return fdt0;
2297 }
2298
2299 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2300 {
2301 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2302 update_fcr31(env, GETPC());
2303 return fst0;
2304 }
2305
2306 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2307 {
2308 uint64_t fdt2;
2309
2310 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2311 update_fcr31(env, GETPC());
2312 return fdt2;
2313 }
2314
2315 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2316 {
2317 uint64_t fdt2;
2318
2319 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2320 update_fcr31(env, GETPC());
2321 return fdt2;
2322 }
2323
2324 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2325 {
2326 uint64_t fdt2;
2327
2328 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2329 update_fcr31(env, GETPC());
2330 return fdt2;
2331 }
2332
2333 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2334 {
2335 uint64_t dt2;
2336
2337 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2338 if (get_float_exception_flags(&env->active_fpu.fp_status)
2339 & (float_flag_invalid | float_flag_overflow)) {
2340 dt2 = FP_TO_INT64_OVERFLOW;
2341 }
2342 update_fcr31(env, GETPC());
2343 return dt2;
2344 }
2345
2346 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2347 {
2348 uint64_t dt2;
2349
2350 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2351 if (get_float_exception_flags(&env->active_fpu.fp_status)
2352 & (float_flag_invalid | float_flag_overflow)) {
2353 dt2 = FP_TO_INT64_OVERFLOW;
2354 }
2355 update_fcr31(env, GETPC());
2356 return dt2;
2357 }
2358
2359 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2360 {
2361 uint32_t fst2;
2362 uint32_t fsth2;
2363
2364 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2365 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2366 update_fcr31(env, GETPC());
2367 return ((uint64_t)fsth2 << 32) | fst2;
2368 }
2369
2370 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2371 {
2372 uint32_t wt2;
2373 uint32_t wth2;
2374 int excp, excph;
2375
2376 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2377 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2378 if (excp & (float_flag_overflow | float_flag_invalid)) {
2379 wt2 = FP_TO_INT32_OVERFLOW;
2380 }
2381
2382 set_float_exception_flags(0, &env->active_fpu.fp_status);
2383 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2384 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2385 if (excph & (float_flag_overflow | float_flag_invalid)) {
2386 wth2 = FP_TO_INT32_OVERFLOW;
2387 }
2388
2389 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2390 update_fcr31(env, GETPC());
2391
2392 return ((uint64_t)wth2 << 32) | wt2;
2393 }
2394
2395 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2396 {
2397 uint32_t fst2;
2398
2399 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2400 update_fcr31(env, GETPC());
2401 return fst2;
2402 }
2403
2404 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2405 {
2406 uint32_t fst2;
2407
2408 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2409 update_fcr31(env, GETPC());
2410 return fst2;
2411 }
2412
2413 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2414 {
2415 uint32_t fst2;
2416
2417 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2418 update_fcr31(env, GETPC());
2419 return fst2;
2420 }
2421
2422 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2423 {
2424 uint32_t wt2;
2425
2426 wt2 = wt0;
2427 update_fcr31(env, GETPC());
2428 return wt2;
2429 }
2430
2431 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2432 {
2433 uint32_t wt2;
2434
2435 wt2 = wth0;
2436 update_fcr31(env, GETPC());
2437 return wt2;
2438 }
2439
2440 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2441 {
2442 uint32_t wt2;
2443
2444 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2445 update_fcr31(env, GETPC());
2446 if (get_float_exception_flags(&env->active_fpu.fp_status)
2447 & (float_flag_invalid | float_flag_overflow)) {
2448 wt2 = FP_TO_INT32_OVERFLOW;
2449 }
2450 return wt2;
2451 }
2452
2453 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2454 {
2455 uint32_t wt2;
2456
2457 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2458 if (get_float_exception_flags(&env->active_fpu.fp_status)
2459 & (float_flag_invalid | float_flag_overflow)) {
2460 wt2 = FP_TO_INT32_OVERFLOW;
2461 }
2462 update_fcr31(env, GETPC());
2463 return wt2;
2464 }
2465
2466 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2467 {
2468 uint64_t dt2;
2469
2470 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2471 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2472 restore_rounding_mode(env);
2473 if (get_float_exception_flags(&env->active_fpu.fp_status)
2474 & (float_flag_invalid | float_flag_overflow)) {
2475 dt2 = FP_TO_INT64_OVERFLOW;
2476 }
2477 update_fcr31(env, GETPC());
2478 return dt2;
2479 }
2480
2481 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2482 {
2483 uint64_t dt2;
2484
2485 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2486 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2487 restore_rounding_mode(env);
2488 if (get_float_exception_flags(&env->active_fpu.fp_status)
2489 & (float_flag_invalid | float_flag_overflow)) {
2490 dt2 = FP_TO_INT64_OVERFLOW;
2491 }
2492 update_fcr31(env, GETPC());
2493 return dt2;
2494 }
2495
2496 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2497 {
2498 uint32_t wt2;
2499
2500 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2501 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2502 restore_rounding_mode(env);
2503 if (get_float_exception_flags(&env->active_fpu.fp_status)
2504 & (float_flag_invalid | float_flag_overflow)) {
2505 wt2 = FP_TO_INT32_OVERFLOW;
2506 }
2507 update_fcr31(env, GETPC());
2508 return wt2;
2509 }
2510
2511 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2512 {
2513 uint32_t wt2;
2514
2515 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2516 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2517 restore_rounding_mode(env);
2518 if (get_float_exception_flags(&env->active_fpu.fp_status)
2519 & (float_flag_invalid | float_flag_overflow)) {
2520 wt2 = FP_TO_INT32_OVERFLOW;
2521 }
2522 update_fcr31(env, GETPC());
2523 return wt2;
2524 }
2525
2526 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2527 {
2528 uint64_t dt2;
2529
2530 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2531 if (get_float_exception_flags(&env->active_fpu.fp_status)
2532 & (float_flag_invalid | float_flag_overflow)) {
2533 dt2 = FP_TO_INT64_OVERFLOW;
2534 }
2535 update_fcr31(env, GETPC());
2536 return dt2;
2537 }
2538
2539 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2540 {
2541 uint64_t dt2;
2542
2543 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2544 if (get_float_exception_flags(&env->active_fpu.fp_status)
2545 & (float_flag_invalid | float_flag_overflow)) {
2546 dt2 = FP_TO_INT64_OVERFLOW;
2547 }
2548 update_fcr31(env, GETPC());
2549 return dt2;
2550 }
2551
2552 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2553 {
2554 uint32_t wt2;
2555
2556 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2557 if (get_float_exception_flags(&env->active_fpu.fp_status)
2558 & (float_flag_invalid | float_flag_overflow)) {
2559 wt2 = FP_TO_INT32_OVERFLOW;
2560 }
2561 update_fcr31(env, GETPC());
2562 return wt2;
2563 }
2564
2565 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2566 {
2567 uint32_t wt2;
2568
2569 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2570 if (get_float_exception_flags(&env->active_fpu.fp_status)
2571 & (float_flag_invalid | float_flag_overflow)) {
2572 wt2 = FP_TO_INT32_OVERFLOW;
2573 }
2574 update_fcr31(env, GETPC());
2575 return wt2;
2576 }
2577
2578 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2579 {
2580 uint64_t dt2;
2581
2582 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2583 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2584 restore_rounding_mode(env);
2585 if (get_float_exception_flags(&env->active_fpu.fp_status)
2586 & (float_flag_invalid | float_flag_overflow)) {
2587 dt2 = FP_TO_INT64_OVERFLOW;
2588 }
2589 update_fcr31(env, GETPC());
2590 return dt2;
2591 }
2592
2593 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2594 {
2595 uint64_t dt2;
2596
2597 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2598 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2599 restore_rounding_mode(env);
2600 if (get_float_exception_flags(&env->active_fpu.fp_status)
2601 & (float_flag_invalid | float_flag_overflow)) {
2602 dt2 = FP_TO_INT64_OVERFLOW;
2603 }
2604 update_fcr31(env, GETPC());
2605 return dt2;
2606 }
2607
2608 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2609 {
2610 uint32_t wt2;
2611
2612 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2613 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2614 restore_rounding_mode(env);
2615 if (get_float_exception_flags(&env->active_fpu.fp_status)
2616 & (float_flag_invalid | float_flag_overflow)) {
2617 wt2 = FP_TO_INT32_OVERFLOW;
2618 }
2619 update_fcr31(env, GETPC());
2620 return wt2;
2621 }
2622
2623 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2624 {
2625 uint32_t wt2;
2626
2627 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2628 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2629 restore_rounding_mode(env);
2630 if (get_float_exception_flags(&env->active_fpu.fp_status)
2631 & (float_flag_invalid | float_flag_overflow)) {
2632 wt2 = FP_TO_INT32_OVERFLOW;
2633 }
2634 update_fcr31(env, GETPC());
2635 return wt2;
2636 }
2637
2638 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2639 {
2640 uint64_t dt2;
2641
2642 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2643 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2644 restore_rounding_mode(env);
2645 if (get_float_exception_flags(&env->active_fpu.fp_status)
2646 & (float_flag_invalid | float_flag_overflow)) {
2647 dt2 = FP_TO_INT64_OVERFLOW;
2648 }
2649 update_fcr31(env, GETPC());
2650 return dt2;
2651 }
2652
2653 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2654 {
2655 uint64_t dt2;
2656
2657 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2658 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2659 restore_rounding_mode(env);
2660 if (get_float_exception_flags(&env->active_fpu.fp_status)
2661 & (float_flag_invalid | float_flag_overflow)) {
2662 dt2 = FP_TO_INT64_OVERFLOW;
2663 }
2664 update_fcr31(env, GETPC());
2665 return dt2;
2666 }
2667
2668 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2669 {
2670 uint32_t wt2;
2671
2672 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2673 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2674 restore_rounding_mode(env);
2675 if (get_float_exception_flags(&env->active_fpu.fp_status)
2676 & (float_flag_invalid | float_flag_overflow)) {
2677 wt2 = FP_TO_INT32_OVERFLOW;
2678 }
2679 update_fcr31(env, GETPC());
2680 return wt2;
2681 }
2682
2683 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2684 {
2685 uint32_t wt2;
2686
2687 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2688 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2689 restore_rounding_mode(env);
2690 if (get_float_exception_flags(&env->active_fpu.fp_status)
2691 & (float_flag_invalid | float_flag_overflow)) {
2692 wt2 = FP_TO_INT32_OVERFLOW;
2693 }
2694 update_fcr31(env, GETPC());
2695 return wt2;
2696 }
2697
2698 /* unary operations, not modifying fp status */
2699 #define FLOAT_UNOP(name) \
2700 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2701 { \
2702 return float64_ ## name(fdt0); \
2703 } \
2704 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2705 { \
2706 return float32_ ## name(fst0); \
2707 } \
2708 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2709 { \
2710 uint32_t wt0; \
2711 uint32_t wth0; \
2712 \
2713 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2714 wth0 = float32_ ## name(fdt0 >> 32); \
2715 return ((uint64_t)wth0 << 32) | wt0; \
2716 }
2717 FLOAT_UNOP(abs)
2718 FLOAT_UNOP(chs)
2719 #undef FLOAT_UNOP
2720
2721 /* MIPS specific unary operations */
2722 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2723 {
2724 uint64_t fdt2;
2725
2726 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2727 update_fcr31(env, GETPC());
2728 return fdt2;
2729 }
2730
2731 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2732 {
2733 uint32_t fst2;
2734
2735 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2736 update_fcr31(env, GETPC());
2737 return fst2;
2738 }
2739
2740 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2741 {
2742 uint64_t fdt2;
2743
2744 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2745 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2746 update_fcr31(env, GETPC());
2747 return fdt2;
2748 }
2749
2750 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2751 {
2752 uint32_t fst2;
2753
2754 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2755 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2756 update_fcr31(env, GETPC());
2757 return fst2;
2758 }
2759
2760 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2761 {
2762 uint64_t fdt2;
2763
2764 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2765 update_fcr31(env, GETPC());
2766 return fdt2;
2767 }
2768
2769 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2770 {
2771 uint32_t fst2;
2772
2773 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2774 update_fcr31(env, GETPC());
2775 return fst2;
2776 }
2777
2778 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2779 {
2780 uint32_t fst2;
2781 uint32_t fsth2;
2782
2783 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2784 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2785 update_fcr31(env, GETPC());
2786 return ((uint64_t)fsth2 << 32) | fst2;
2787 }
2788
2789 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2790 {
2791 uint64_t fdt2;
2792
2793 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2794 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2795 update_fcr31(env, GETPC());
2796 return fdt2;
2797 }
2798
2799 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2800 {
2801 uint32_t fst2;
2802
2803 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2804 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2805 update_fcr31(env, GETPC());
2806 return fst2;
2807 }
2808
2809 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2810 {
2811 uint32_t fst2;
2812 uint32_t fsth2;
2813
2814 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2815 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2816 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2817 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2818 update_fcr31(env, GETPC());
2819 return ((uint64_t)fsth2 << 32) | fst2;
2820 }
2821
2822 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2823
2824 /* binary operations */
2825 #define FLOAT_BINOP(name) \
2826 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2827 uint64_t fdt0, uint64_t fdt1) \
2828 { \
2829 uint64_t dt2; \
2830 \
2831 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2832 update_fcr31(env, GETPC()); \
2833 return dt2; \
2834 } \
2835 \
2836 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2837 uint32_t fst0, uint32_t fst1) \
2838 { \
2839 uint32_t wt2; \
2840 \
2841 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2842 update_fcr31(env, GETPC()); \
2843 return wt2; \
2844 } \
2845 \
2846 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2847 uint64_t fdt0, \
2848 uint64_t fdt1) \
2849 { \
2850 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2851 uint32_t fsth0 = fdt0 >> 32; \
2852 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2853 uint32_t fsth1 = fdt1 >> 32; \
2854 uint32_t wt2; \
2855 uint32_t wth2; \
2856 \
2857 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2858 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2859 update_fcr31(env, GETPC()); \
2860 return ((uint64_t)wth2 << 32) | wt2; \
2861 }
2862
2863 FLOAT_BINOP(add)
2864 FLOAT_BINOP(sub)
2865 FLOAT_BINOP(mul)
2866 FLOAT_BINOP(div)
2867 #undef FLOAT_BINOP
2868
2869 #define UNFUSED_FMA(prefix, a, b, c, flags) \
2870 { \
2871 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
2872 if ((flags) & float_muladd_negate_c) { \
2873 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
2874 } else { \
2875 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
2876 } \
2877 if ((flags) & float_muladd_negate_result) { \
2878 a = prefix##_chs(a); \
2879 } \
2880 }
2881
2882 /* FMA based operations */
2883 #define FLOAT_FMA(name, type) \
2884 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2885 uint64_t fdt0, uint64_t fdt1, \
2886 uint64_t fdt2) \
2887 { \
2888 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
2889 update_fcr31(env, GETPC()); \
2890 return fdt0; \
2891 } \
2892 \
2893 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2894 uint32_t fst0, uint32_t fst1, \
2895 uint32_t fst2) \
2896 { \
2897 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2898 update_fcr31(env, GETPC()); \
2899 return fst0; \
2900 } \
2901 \
2902 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2903 uint64_t fdt0, uint64_t fdt1, \
2904 uint64_t fdt2) \
2905 { \
2906 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2907 uint32_t fsth0 = fdt0 >> 32; \
2908 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2909 uint32_t fsth1 = fdt1 >> 32; \
2910 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2911 uint32_t fsth2 = fdt2 >> 32; \
2912 \
2913 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2914 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
2915 update_fcr31(env, GETPC()); \
2916 return ((uint64_t)fsth0 << 32) | fst0; \
2917 }
2918 FLOAT_FMA(madd, 0)
2919 FLOAT_FMA(msub, float_muladd_negate_c)
2920 FLOAT_FMA(nmadd, float_muladd_negate_result)
2921 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2922 #undef FLOAT_FMA
2923
2924 /* MIPS specific binary operations */
2925 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2926 {
2927 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2928 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2929 update_fcr31(env, GETPC());
2930 return fdt2;
2931 }
2932
2933 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2934 {
2935 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2936 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2937 update_fcr31(env, GETPC());
2938 return fst2;
2939 }
2940
2941 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2942 {
2943 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2944 uint32_t fsth0 = fdt0 >> 32;
2945 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2946 uint32_t fsth2 = fdt2 >> 32;
2947
2948 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2949 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2950 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2951 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
2952 update_fcr31(env, GETPC());
2953 return ((uint64_t)fsth2 << 32) | fst2;
2954 }
2955
2956 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2957 {
2958 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2959 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
2960 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2961 update_fcr31(env, GETPC());
2962 return fdt2;
2963 }
2964
2965 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2966 {
2967 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2968 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2969 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2970 update_fcr31(env, GETPC());
2971 return fst2;
2972 }
2973
2974 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2975 {
2976 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2977 uint32_t fsth0 = fdt0 >> 32;
2978 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2979 uint32_t fsth2 = fdt2 >> 32;
2980
2981 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2982 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2983 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2984 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
2985 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2986 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2987 update_fcr31(env, GETPC());
2988 return ((uint64_t)fsth2 << 32) | fst2;
2989 }
2990
2991 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
2992 {
2993 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2994 uint32_t fsth0 = fdt0 >> 32;
2995 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2996 uint32_t fsth1 = fdt1 >> 32;
2997 uint32_t fst2;
2998 uint32_t fsth2;
2999
3000 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3001 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3002 update_fcr31(env, GETPC());
3003 return ((uint64_t)fsth2 << 32) | fst2;
3004 }
3005
3006 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3007 {
3008 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3009 uint32_t fsth0 = fdt0 >> 32;
3010 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3011 uint32_t fsth1 = fdt1 >> 32;
3012 uint32_t fst2;
3013 uint32_t fsth2;
3014
3015 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3016 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3017 update_fcr31(env, GETPC());
3018 return ((uint64_t)fsth2 << 32) | fst2;
3019 }
3020
3021 /* compare operations */
3022 #define FOP_COND_D(op, cond) \
3023 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3024 uint64_t fdt1, int cc) \
3025 { \
3026 int c; \
3027 c = cond; \
3028 update_fcr31(env, GETPC()); \
3029 if (c) \
3030 SET_FP_COND(cc, env->active_fpu); \
3031 else \
3032 CLEAR_FP_COND(cc, env->active_fpu); \
3033 } \
3034 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3035 uint64_t fdt1, int cc) \
3036 { \
3037 int c; \
3038 fdt0 = float64_abs(fdt0); \
3039 fdt1 = float64_abs(fdt1); \
3040 c = cond; \
3041 update_fcr31(env, GETPC()); \
3042 if (c) \
3043 SET_FP_COND(cc, env->active_fpu); \
3044 else \
3045 CLEAR_FP_COND(cc, env->active_fpu); \
3046 }
3047
3048 /* NOTE: the comma operator will make "cond" to eval to false,
3049 * but float64_unordered_quiet() is still called. */
3050 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3051 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3052 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3053 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3054 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3055 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3056 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3057 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3058 /* NOTE: the comma operator will make "cond" to eval to false,
3059 * but float64_unordered() is still called. */
3060 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3061 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3062 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3063 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3064 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3065 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3066 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3067 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3068
3069 #define FOP_COND_S(op, cond) \
3070 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3071 uint32_t fst1, int cc) \
3072 { \
3073 int c; \
3074 c = cond; \
3075 update_fcr31(env, GETPC()); \
3076 if (c) \
3077 SET_FP_COND(cc, env->active_fpu); \
3078 else \
3079 CLEAR_FP_COND(cc, env->active_fpu); \
3080 } \
3081 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3082 uint32_t fst1, int cc) \
3083 { \
3084 int c; \
3085 fst0 = float32_abs(fst0); \
3086 fst1 = float32_abs(fst1); \
3087 c = cond; \
3088 update_fcr31(env, GETPC()); \
3089 if (c) \
3090 SET_FP_COND(cc, env->active_fpu); \
3091 else \
3092 CLEAR_FP_COND(cc, env->active_fpu); \
3093 }
3094
3095 /* NOTE: the comma operator will make "cond" to eval to false,
3096 * but float32_unordered_quiet() is still called. */
3097 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3098 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3099 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3100 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3101 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3102 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3103 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3104 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3105 /* NOTE: the comma operator will make "cond" to eval to false,
3106 * but float32_unordered() is still called. */
3107 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3108 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3109 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3110 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3111 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3112 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3113 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3114 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3115
3116 #define FOP_COND_PS(op, condl, condh) \
3117 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3118 uint64_t fdt1, int cc) \
3119 { \
3120 uint32_t fst0, fsth0, fst1, fsth1; \
3121 int ch, cl; \
3122 fst0 = fdt0 & 0XFFFFFFFF; \
3123 fsth0 = fdt0 >> 32; \
3124 fst1 = fdt1 & 0XFFFFFFFF; \
3125 fsth1 = fdt1 >> 32; \
3126 cl = condl; \
3127 ch = condh; \
3128 update_fcr31(env, GETPC()); \
3129 if (cl) \
3130 SET_FP_COND(cc, env->active_fpu); \
3131 else \
3132 CLEAR_FP_COND(cc, env->active_fpu); \
3133 if (ch) \
3134 SET_FP_COND(cc + 1, env->active_fpu); \
3135 else \
3136 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3137 } \
3138 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3139 uint64_t fdt1, int cc) \
3140 { \
3141 uint32_t fst0, fsth0, fst1, fsth1; \
3142 int ch, cl; \
3143 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3144 fsth0 = float32_abs(fdt0 >> 32); \
3145 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3146 fsth1 = float32_abs(fdt1 >> 32); \
3147 cl = condl; \
3148 ch = condh; \
3149 update_fcr31(env, GETPC()); \
3150 if (cl) \
3151 SET_FP_COND(cc, env->active_fpu); \
3152 else \
3153 CLEAR_FP_COND(cc, env->active_fpu); \
3154 if (ch) \
3155 SET_FP_COND(cc + 1, env->active_fpu); \
3156 else \
3157 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3158 }
3159
3160 /* NOTE: the comma operator will make "cond" to eval to false,
3161 * but float32_unordered_quiet() is still called. */
3162 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3163 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3164 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3165 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3166 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3167 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3168 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3169 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3170 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3171 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3172 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3173 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3174 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3175 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3176 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3177 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3178 /* NOTE: the comma operator will make "cond" to eval to false,
3179 * but float32_unordered() is still called. */
3180 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3181 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3182 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3183 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3184 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3185 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3186 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3187 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3188 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3189 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3190 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3191 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3192 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3193 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3194 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3195 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Various patches