tcg/sparc/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #ifndef TCG_TARGET_SPARC
  25 #define TCG_TARGET_SPARC 1
  26
  27 #define TCG_TARGET_WORDS_BIGENDIAN
  28
  29 #define TCG_TARGET_NB_REGS 32
  30
  31 typedef enum {
  32     TCG_REG_G0 = 0,
  33     TCG_REG_G1,
  34     TCG_REG_G2,
  35     TCG_REG_G3,
  36     TCG_REG_G4,
  37     TCG_REG_G5,
  38     TCG_REG_G6,
  39     TCG_REG_G7,
  40     TCG_REG_O0,
  41     TCG_REG_O1,
  42     TCG_REG_O2,
  43     TCG_REG_O3,
  44     TCG_REG_O4,
  45     TCG_REG_O5,
  46     TCG_REG_O6,
  47     TCG_REG_O7,
  48     TCG_REG_L0,
  49     TCG_REG_L1,
  50     TCG_REG_L2,
  51     TCG_REG_L3,
  52     TCG_REG_L4,
  53     TCG_REG_L5,
  54     TCG_REG_L6,
  55     TCG_REG_L7,
  56     TCG_REG_I0,
  57     TCG_REG_I1,
  58     TCG_REG_I2,
  59     TCG_REG_I3,
  60     TCG_REG_I4,
  61     TCG_REG_I5,
  62     TCG_REG_I6,
  63     TCG_REG_I7,
  64 } TCGReg;
  65
  66 #define TCG_CT_CONST_S11  0x100
  67 #define TCG_CT_CONST_S13  0x200
  68 #define TCG_CT_CONST_ZERO 0x400
  69
  70 /* used for function call generation */
  71 #define TCG_REG_CALL_STACK TCG_REG_O6
  72
  73 #if TCG_TARGET_REG_BITS == 64
  74 #define TCG_TARGET_STACK_BIAS           2047
  75 #define TCG_TARGET_STACK_ALIGN          16
  76 #define TCG_TARGET_CALL_STACK_OFFSET    (128 + 6*8 + TCG_TARGET_STACK_BIAS)
  77 #else
  78 #define TCG_TARGET_STACK_BIAS           0
  79 #define TCG_TARGET_STACK_ALIGN          8
  80 #define TCG_TARGET_CALL_STACK_OFFSET    (64 + 4 + 6*4)
  81 #endif
  82
  83 #if TCG_TARGET_REG_BITS == 64
  84 #define TCG_TARGET_EXTEND_ARGS 1
  85 #endif
  86
  87 /* optional instructions */
  88 #define TCG_TARGET_HAS_div_i32          1
  89 #define TCG_TARGET_HAS_rot_i32          0
  90 #define TCG_TARGET_HAS_ext8s_i32        0
  91 #define TCG_TARGET_HAS_ext16s_i32       0
  92 #define TCG_TARGET_HAS_ext8u_i32        0
  93 #define TCG_TARGET_HAS_ext16u_i32       0
  94 #define TCG_TARGET_HAS_bswap16_i32      0
  95 #define TCG_TARGET_HAS_bswap32_i32      0
  96 #define TCG_TARGET_HAS_neg_i32          1
  97 #define TCG_TARGET_HAS_not_i32          1
  98 #define TCG_TARGET_HAS_andc_i32         1
  99 #define TCG_TARGET_HAS_orc_i32          1
 100 #define TCG_TARGET_HAS_eqv_i32          0
 101 #define TCG_TARGET_HAS_nand_i32         0
 102 #define TCG_TARGET_HAS_nor_i32          0
 103 #define TCG_TARGET_HAS_deposit_i32      0
 104 #define TCG_TARGET_HAS_movcond_i32      1
 105 #define TCG_TARGET_HAS_add2_i32         1
 106 #define TCG_TARGET_HAS_sub2_i32         1
 107 #define TCG_TARGET_HAS_mulu2_i32        1
 108 #define TCG_TARGET_HAS_muls2_i32        0
 109
 110 #if TCG_TARGET_REG_BITS == 64
 111 #define TCG_TARGET_HAS_div_i64          1
 112 #define TCG_TARGET_HAS_rot_i64          0
 113 #define TCG_TARGET_HAS_ext8s_i64        0
 114 #define TCG_TARGET_HAS_ext16s_i64       0
 115 #define TCG_TARGET_HAS_ext32s_i64       1
 116 #define TCG_TARGET_HAS_ext8u_i64        0
 117 #define TCG_TARGET_HAS_ext16u_i64       0
 118 #define TCG_TARGET_HAS_ext32u_i64       1
 119 #define TCG_TARGET_HAS_bswap16_i64      0
 120 #define TCG_TARGET_HAS_bswap32_i64      0
 121 #define TCG_TARGET_HAS_bswap64_i64      0
 122 #define TCG_TARGET_HAS_neg_i64          1
 123 #define TCG_TARGET_HAS_not_i64          1
 124 #define TCG_TARGET_HAS_andc_i64         1
 125 #define TCG_TARGET_HAS_orc_i64          1
 126 #define TCG_TARGET_HAS_eqv_i64          0
 127 #define TCG_TARGET_HAS_nand_i64         0
 128 #define TCG_TARGET_HAS_nor_i64          0
 129 #define TCG_TARGET_HAS_deposit_i64      0
 130 #define TCG_TARGET_HAS_movcond_i64      1
 131 #define TCG_TARGET_HAS_add2_i64         0
 132 #define TCG_TARGET_HAS_sub2_i64         0
 133 #define TCG_TARGET_HAS_mulu2_i64        0
 134 #define TCG_TARGET_HAS_muls2_i64        0
 135 #endif
 136
 137 #define TCG_AREG0 TCG_REG_I0
 138
 139 static inline void flush_icache_range(tcg_target_ulong start,
 140                                       tcg_target_ulong stop)
 141 {
 142     unsigned long p;
 143
 144     p = start & ~(8UL - 1UL);
 145     stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
 146
 147     for (; p < stop; p += 8)
 148         __asm__ __volatile__("flush\t%0" : : "r" (p));
 149 }
 150
 151 #endif