hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "apic.h"
  26 #include "ioapic.h"
  27 #include "ioapic_internal.h"
  28
  29 //#define DEBUG_IOAPIC
  30
  31 #ifdef DEBUG_IOAPIC
  32 #define DPRINTF(fmt, ...)                                       \
  33     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...)
  36 #endif
  37
  38 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  39
  40 static void ioapic_service(IOAPICCommonState *s)
  41 {
  42     uint8_t i;
  43     uint8_t trig_mode;
  44     uint8_t vector;
  45     uint8_t delivery_mode;
  46     uint32_t mask;
  47     uint64_t entry;
  48     uint8_t dest;
  49     uint8_t dest_mode;
  50
  51     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  52         mask = 1 << i;
  53         if (s->irr & mask) {
  54             entry = s->ioredtbl[i];
  55             if (!(entry & IOAPIC_LVT_MASKED)) {
  56                 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
  57                 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
  58                 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  59                 delivery_mode =
  60                     (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
  61                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
  62                     s->irr &= ~mask;
  63                 } else {
  64                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
  65                 }
  66                 if (delivery_mode == IOAPIC_DM_EXTINT) {
  67                     vector = pic_read_irq(isa_pic);
  68                 } else {
  69                     vector = entry & IOAPIC_VECTOR_MASK;
  70                 }
  71                 apic_deliver_irq(dest, dest_mode, delivery_mode,
  72                                  vector, trig_mode);
  73             }
  74         }
  75     }
  76 }
  77
  78 static void ioapic_set_irq(void *opaque, int vector, int level)
  79 {
  80     IOAPICCommonState *s = opaque;
  81
  82     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
  83      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
  84      * the cleanest way of doing it but it should work. */
  85
  86     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
  87     if (vector == 0) {
  88         vector = 2;
  89     }
  90     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
  91         uint32_t mask = 1 << vector;
  92         uint64_t entry = s->ioredtbl[vector];
  93
  94         if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) {
  95             level = !level;
  96         }
  97         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
  98             IOAPIC_TRIGGER_LEVEL) {
  99             /* level triggered */
 100             if (level) {
 101                 s->irr |= mask;
 102                 ioapic_service(s);
 103             } else {
 104                 s->irr &= ~mask;
 105             }
 106         } else {
 107             /* According to the 82093AA manual, we must ignore edge requests
 108              * if the input pin is masked. */
 109             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 110                 s->irr |= mask;
 111                 ioapic_service(s);
 112             }
 113         }
 114     }
 115 }
 116
 117 void ioapic_eoi_broadcast(int vector)
 118 {
 119     IOAPICCommonState *s;
 120     uint64_t entry;
 121     int i, n;
 122
 123     for (i = 0; i < MAX_IOAPICS; i++) {
 124         s = ioapics[i];
 125         if (!s) {
 126             continue;
 127         }
 128         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 129             entry = s->ioredtbl[n];
 130             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 131                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 132                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 133                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 134                     ioapic_service(s);
 135                 }
 136             }
 137         }
 138     }
 139 }
 140
 141 static uint64_t
 142 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 143 {
 144     IOAPICCommonState *s = opaque;
 145     int index;
 146     uint32_t val = 0;
 147
 148     switch (addr & 0xff) {
 149     case IOAPIC_IOREGSEL:
 150         val = s->ioregsel;
 151         break;
 152     case IOAPIC_IOWIN:
 153         if (size != 4) {
 154             break;
 155         }
 156         switch (s->ioregsel) {
 157         case IOAPIC_REG_ID:
 158             val = s->id << IOAPIC_ID_SHIFT;
 159             break;
 160         case IOAPIC_REG_VER:
 161             val = IOAPIC_VERSION |
 162                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 163             break;
 164         case IOAPIC_REG_ARB:
 165             val = 0;
 166             break;
 167         default:
 168             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 169             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 170                 if (s->ioregsel & 1) {
 171                     val = s->ioredtbl[index] >> 32;
 172                 } else {
 173                     val = s->ioredtbl[index] & 0xffffffff;
 174                 }
 175             }
 176         }
 177         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 178         break;
 179     }
 180     return val;
 181 }
 182
 183 static void
 184 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 185                  unsigned int size)
 186 {
 187     IOAPICCommonState *s = opaque;
 188     int index;
 189
 190     switch (addr & 0xff) {
 191     case IOAPIC_IOREGSEL:
 192         s->ioregsel = val;
 193         break;
 194     case IOAPIC_IOWIN:
 195         if (size != 4) {
 196             break;
 197         }
 198         DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
 199         switch (s->ioregsel) {
 200         case IOAPIC_REG_ID:
 201             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 202             break;
 203         case IOAPIC_REG_VER:
 204         case IOAPIC_REG_ARB:
 205             break;
 206         default:
 207             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 208             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 209                 if (s->ioregsel & 1) {
 210                     s->ioredtbl[index] &= 0xffffffff;
 211                     s->ioredtbl[index] |= (uint64_t)val << 32;
 212                 } else {
 213                     s->ioredtbl[index] &= ~0xffffffffULL;
 214                     s->ioredtbl[index] |= val;
 215                 }
 216                 ioapic_service(s);
 217             }
 218         }
 219         break;
 220     }
 221 }
 222
 223 static const MemoryRegionOps ioapic_io_ops = {
 224     .read = ioapic_mem_read,
 225     .write = ioapic_mem_write,
 226     .endianness = DEVICE_NATIVE_ENDIAN,
 227 };
 228
 229 static void ioapic_init(IOAPICCommonState *s, int instance_no)
 230 {
 231     memory_region_init_io(&s->io_memory, &ioapic_io_ops, s, "ioapic", 0x1000);
 232
 233     qdev_init_gpio_in(&s->busdev.qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
 234
 235     ioapics[instance_no] = s;
 236 }
 237
 238 static void ioapic_class_init(ObjectClass *klass, void *data)
 239 {
 240     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 241     DeviceClass *dc = DEVICE_CLASS(klass);
 242
 243     k->init = ioapic_init;
 244     dc->reset = ioapic_reset_common;
 245 }
 246
 247 static const TypeInfo ioapic_info = {
 248     .name          = "ioapic",
 249     .parent        = TYPE_IOAPIC_COMMON,
 250     .instance_size = sizeof(IOAPICCommonState),
 251     .class_init    = ioapic_class_init,
 252 };
 253
 254 static void ioapic_register_types(void)
 255 {
 256     type_register_static(&ioapic_info);
 257 }
 258
 259 type_init(ioapic_register_types)