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hw/pxa2xx_timer: Explicitly mark fallthroughs
[qemu/pbrook.git] / hw / ipoctal232.c
blobc1e3b197b5763c624f440893eed355ac3c2f42b6
1 /*
2 * QEMU GE IP-Octal 232 IndustryPack emulation
3 *
4 * Copyright (C) 2012 Igalia, S.L.
5 * Author: Alberto Garcia <agarcia@igalia.com>
6 *
7 * This code is licensed under the GNU GPL v2 or (at your option) any
8 * later version.
9 */
10
11 #include "ipack.h"
12 #include "qemu/bitops.h"
13 #include "char/char.h"
14
15 /* #define DEBUG_IPOCTAL */
16
17 #ifdef DEBUG_IPOCTAL
18 #define DPRINTF2(fmt, ...) \
19 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
20 #else
21 #define DPRINTF2(fmt, ...) do { } while (0)
22 #endif
23
24 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
25
26 #define RX_FIFO_SIZE 3
27
28 /* The IP-Octal has 8 channels (a-h)
29 divided into 4 blocks (A-D) */
30 #define N_CHANNELS 8
31 #define N_BLOCKS 4
32
33 #define REG_MRa 0x01
34 #define REG_MRb 0x11
35 #define REG_SRa 0x03
36 #define REG_SRb 0x13
37 #define REG_CSRa 0x03
38 #define REG_CSRb 0x13
39 #define REG_CRa 0x05
40 #define REG_CRb 0x15
41 #define REG_RHRa 0x07
42 #define REG_RHRb 0x17
43 #define REG_THRa 0x07
44 #define REG_THRb 0x17
45 #define REG_ACR 0x09
46 #define REG_ISR 0x0B
47 #define REG_IMR 0x0B
48 #define REG_OPCR 0x1B
49
50 #define CR_ENABLE_RX BIT(0)
51 #define CR_DISABLE_RX BIT(1)
52 #define CR_ENABLE_TX BIT(2)
53 #define CR_DISABLE_TX BIT(3)
54 #define CR_CMD(cr) ((cr) >> 4)
55 #define CR_NO_OP 0
56 #define CR_RESET_MR 1
57 #define CR_RESET_RX 2
58 #define CR_RESET_TX 3
59 #define CR_RESET_ERR 4
60 #define CR_RESET_BRKINT 5
61 #define CR_START_BRK 6
62 #define CR_STOP_BRK 7
63 #define CR_ASSERT_RTSN 8
64 #define CR_NEGATE_RTSN 9
65 #define CR_TIMEOUT_ON 10
66 #define CR_TIMEOUT_OFF 12
67
68 #define SR_RXRDY BIT(0)
69 #define SR_FFULL BIT(1)
70 #define SR_TXRDY BIT(2)
71 #define SR_TXEMT BIT(3)
72 #define SR_OVERRUN BIT(4)
73 #define SR_PARITY BIT(5)
74 #define SR_FRAMING BIT(6)
75 #define SR_BREAK BIT(7)
76
77 #define ISR_TXRDYA BIT(0)
78 #define ISR_RXRDYA BIT(1)
79 #define ISR_BREAKA BIT(2)
80 #define ISR_CNTRDY BIT(3)
81 #define ISR_TXRDYB BIT(4)
82 #define ISR_RXRDYB BIT(5)
83 #define ISR_BREAKB BIT(6)
84 #define ISR_MPICHG BIT(7)
85 #define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
86 #define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
87 #define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
88
89 typedef struct IPOctalState IPOctalState;
90 typedef struct SCC2698Channel SCC2698Channel;
91 typedef struct SCC2698Block SCC2698Block;
92
93 struct SCC2698Channel {
94 IPOctalState *ipoctal;
95 CharDriverState *dev;
96 char *devpath;
97 bool rx_enabled;
98 uint8_t mr[2];
99 uint8_t mr_idx;
100 uint8_t sr;
101 uint8_t rhr[RX_FIFO_SIZE];
102 uint8_t rhr_idx;
103 uint8_t rx_pending;
104 };
105
106 struct SCC2698Block {
107 uint8_t imr;
108 uint8_t isr;
109 };
110
111 struct IPOctalState {
112 IPackDevice dev;
113 SCC2698Channel ch[N_CHANNELS];
114 SCC2698Block blk[N_BLOCKS];
115 uint8_t irq_vector;
116 };
117
118 #define TYPE_IPOCTAL "ipoctal232"
119
120 #define IPOCTAL(obj) \
121 OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
122
123 static const VMStateDescription vmstate_scc2698_channel = {
124 .name = "scc2698_channel",
125 .version_id = 1,
126 .minimum_version_id = 1,
127 .minimum_version_id_old = 1,
128 .fields = (VMStateField[]) {
129 VMSTATE_BOOL(rx_enabled, SCC2698Channel),
130 VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
131 VMSTATE_UINT8(mr_idx, SCC2698Channel),
132 VMSTATE_UINT8(sr, SCC2698Channel),
133 VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
134 VMSTATE_UINT8(rhr_idx, SCC2698Channel),
135 VMSTATE_UINT8(rx_pending, SCC2698Channel),
136 VMSTATE_END_OF_LIST()
137 }
138 };
139
140 static const VMStateDescription vmstate_scc2698_block = {
141 .name = "scc2698_block",
142 .version_id = 1,
143 .minimum_version_id = 1,
144 .minimum_version_id_old = 1,
145 .fields = (VMStateField[]) {
146 VMSTATE_UINT8(imr, SCC2698Block),
147 VMSTATE_UINT8(isr, SCC2698Block),
148 VMSTATE_END_OF_LIST()
149 }
150 };
151
152 static const VMStateDescription vmstate_ipoctal = {
153 .name = "ipoctal232",
154 .version_id = 1,
155 .minimum_version_id = 1,
156 .minimum_version_id_old = 1,
157 .fields = (VMStateField[]) {
158 VMSTATE_IPACK_DEVICE(dev, IPOctalState),
159 VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
160 vmstate_scc2698_channel, SCC2698Channel),
161 VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
162 vmstate_scc2698_block, SCC2698Block),
163 VMSTATE_UINT8(irq_vector, IPOctalState),
164 VMSTATE_END_OF_LIST()
165 }
166 };
167
168 /* data[10] is 0x0C, not 0x0B as the doc says */
169 static const uint8_t id_prom_data[] = {
170 0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
171 0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
172 };
173
174 static void update_irq(IPOctalState *dev, unsigned block)
175 {
176 /* Blocks A and B interrupt on INT0#, C and D on INT1#.
177 Thus, to get the status we have to check two blocks. */
178 SCC2698Block *blk0 = &dev->blk[block];
179 SCC2698Block *blk1 = &dev->blk[block^1];
180 unsigned intno = block / 2;
181
182 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
183 qemu_irq_raise(dev->dev.irq[intno]);
184 } else {
185 qemu_irq_lower(dev->dev.irq[intno]);
186 }
187 }
188
189 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
190 {
191 SCC2698Channel *ch = &dev->ch[channel];
192 SCC2698Block *blk = &dev->blk[channel / 2];
193
194 DPRINTF("Write CR%c %u: ", channel + 'a', val);
195
196 /* The lower 4 bits are used to enable and disable Tx and Rx */
197 if (val & CR_ENABLE_RX) {
198 DPRINTF2("Rx on, ");
199 ch->rx_enabled = true;
200 }
201 if (val & CR_DISABLE_RX) {
202 DPRINTF2("Rx off, ");
203 ch->rx_enabled = false;
204 }
205 if (val & CR_ENABLE_TX) {
206 DPRINTF2("Tx on, ");
207 ch->sr |= SR_TXRDY | SR_TXEMT;
208 blk->isr |= ISR_TXRDY(channel);
209 }
210 if (val & CR_DISABLE_TX) {
211 DPRINTF2("Tx off, ");
212 ch->sr &= ~(SR_TXRDY | SR_TXEMT);
213 blk->isr &= ~ISR_TXRDY(channel);
214 }
215
216 DPRINTF2("cmd: ");
217
218 /* The rest of the bits implement different commands */
219 switch (CR_CMD(val)) {
220 case CR_NO_OP:
221 DPRINTF2("none");
222 break;
223 case CR_RESET_MR:
224 DPRINTF2("reset MR");
225 ch->mr_idx = 0;
226 break;
227 case CR_RESET_RX:
228 DPRINTF2("reset Rx");
229 ch->rx_enabled = false;
230 ch->rx_pending = 0;
231 ch->sr &= ~SR_RXRDY;
232 blk->isr &= ~ISR_RXRDY(channel);
233 break;
234 case CR_RESET_TX:
235 DPRINTF2("reset Tx");
236 ch->sr &= ~(SR_TXRDY | SR_TXEMT);
237 blk->isr &= ~ISR_TXRDY(channel);
238 break;
239 case CR_RESET_ERR:
240 DPRINTF2("reset err");
241 ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
242 break;
243 case CR_RESET_BRKINT:
244 DPRINTF2("reset brk ch int");
245 blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
246 break;
247 default:
248 DPRINTF2("unsupported 0x%x", CR_CMD(val));
249 }
250
251 DPRINTF2("\n");
252 }
253
254 static uint16_t io_read(IPackDevice *ip, uint8_t addr)
255 {
256 IPOctalState *dev = IPOCTAL(ip);
257 uint16_t ret = 0;
258 /* addr[7:6]: block (A-D)
259 addr[7:5]: channel (a-h)
260 addr[5:0]: register */
261 unsigned block = addr >> 5;
262 unsigned channel = addr >> 4;
263 /* Big endian, accessed using 8-bit bytes at odd locations */
264 unsigned offset = (addr & 0x1F) ^ 1;
265 SCC2698Channel *ch = &dev->ch[channel];
266 SCC2698Block *blk = &dev->blk[block];
267 uint8_t old_isr = blk->isr;
268
269 switch (offset) {
270
271 case REG_MRa:
272 case REG_MRb:
273 ret = ch->mr[ch->mr_idx];
274 DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
275 ch->mr_idx = 1;
276 break;
277
278 case REG_SRa:
279 case REG_SRb:
280 ret = ch->sr;
281 DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
282 break;
283
284 case REG_RHRa:
285 case REG_RHRb:
286 ret = ch->rhr[ch->rhr_idx];
287 if (ch->rx_pending > 0) {
288 ch->rx_pending--;
289 if (ch->rx_pending == 0) {
290 ch->sr &= ~SR_RXRDY;
291 blk->isr &= ~ISR_RXRDY(channel);
292 if (ch->dev) {
293 qemu_chr_accept_input(ch->dev);
294 }
295 } else {
296 ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
297 }
298 if (ch->sr & SR_BREAK) {
299 ch->sr &= ~SR_BREAK;
300 blk->isr |= ISR_BREAK(channel);
301 }
302 }
303 DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
304 break;
305
306 case REG_ISR:
307 ret = blk->isr;
308 DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
309 break;
310
311 default:
312 DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
313 }
314
315 if (old_isr != blk->isr) {
316 update_irq(dev, block);
317 }
318
319 return ret;
320 }
321
322 static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
323 {
324 IPOctalState *dev = IPOCTAL(ip);
325 unsigned reg = val & 0xFF;
326 /* addr[7:6]: block (A-D)
327 addr[7:5]: channel (a-h)
328 addr[5:0]: register */
329 unsigned block = addr >> 5;
330 unsigned channel = addr >> 4;
331 /* Big endian, accessed using 8-bit bytes at odd locations */
332 unsigned offset = (addr & 0x1F) ^ 1;
333 SCC2698Channel *ch = &dev->ch[channel];
334 SCC2698Block *blk = &dev->blk[block];
335 uint8_t old_isr = blk->isr;
336 uint8_t old_imr = blk->imr;
337
338 switch (offset) {
339
340 case REG_MRa:
341 case REG_MRb:
342 ch->mr[ch->mr_idx] = reg;
343 DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
344 ch->mr_idx = 1;
345 break;
346
347 /* Not implemented */
348 case REG_CSRa:
349 case REG_CSRb:
350 DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
351 break;
352
353 case REG_CRa:
354 case REG_CRb:
355 write_cr(dev, channel, reg);
356 break;
357
358 case REG_THRa:
359 case REG_THRb:
360 if (ch->sr & SR_TXRDY) {
361 DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
362 if (ch->dev) {
363 uint8_t thr = reg;
364 qemu_chr_fe_write(ch->dev, &thr, 1);
365 }
366 } else {
367 DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
368 }
369 break;
370
371 /* Not implemented */
372 case REG_ACR:
373 DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
374 break;
375
376 case REG_IMR:
377 DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
378 blk->imr = reg;
379 break;
380
381 /* Not implemented */
382 case REG_OPCR:
383 DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
384 break;
385
386 default:
387 DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
388 }
389
390 if (old_isr != blk->isr || old_imr != blk->imr) {
391 update_irq(dev, block);
392 }
393 }
394
395 static uint16_t id_read(IPackDevice *ip, uint8_t addr)
396 {
397 uint16_t ret = 0;
398 unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
399
400 if (pos < ARRAY_SIZE(id_prom_data)) {
401 ret = id_prom_data[pos];
402 } else {
403 DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr);
404 }
405
406 return ret;
407 }
408
409 static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
410 {
411 IPOctalState *dev = IPOCTAL(ip);
412 if (addr == 1) {
413 DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
414 dev->irq_vector = val; /* Undocumented, but the hw works like that */
415 } else {
416 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
417 }
418 }
419
420 static uint16_t int_read(IPackDevice *ip, uint8_t addr)
421 {
422 IPOctalState *dev = IPOCTAL(ip);
423 /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
424 if (addr != 0 && addr != 2) {
425 DPRINTF("Attempt to read from 0x%x\n", addr);
426 return 0;
427 } else {
428 /* Update interrupts if necessary */
429 update_irq(dev, addr);
430 return dev->irq_vector;
431 }
432 }
433
434 static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
435 {
436 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
437 }
438
439 static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
440 {
441 DPRINTF("Attempt to read from 0x%x\n", addr);
442 return 0;
443 }
444
445 static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
446 {
447 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
448 }
449
450 static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
451 {
452 DPRINTF("Attempt to read from 0x%x\n", addr);
453 return 0;
454 }
455
456 static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
457 {
458 IPOctalState *dev = IPOCTAL(ip);
459 if (addr == 1) {
460 DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
461 dev->irq_vector = val;
462 } else {
463 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
464 }
465 }
466
467 static int hostdev_can_receive(void *opaque)
468 {
469 SCC2698Channel *ch = opaque;
470 int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
471 return ch->rx_enabled ? available_bytes : 0;
472 }
473
474 static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
475 {
476 SCC2698Channel *ch = opaque;
477 IPOctalState *dev = ch->ipoctal;
478 unsigned pos = ch->rhr_idx + ch->rx_pending;
479 int i;
480
481 assert(size + ch->rx_pending <= RX_FIFO_SIZE);
482
483 /* Copy data to the RxFIFO */
484 for (i = 0; i < size; i++) {
485 pos %= RX_FIFO_SIZE;
486 ch->rhr[pos++] = buf[i];
487 }
488
489 ch->rx_pending += size;
490
491 /* If the RxFIFO was empty raise an interrupt */
492 if (!(ch->sr & SR_RXRDY)) {
493 unsigned block, channel = 0;
494 /* Find channel number to update the ISR register */
495 while (&dev->ch[channel] != ch) {
496 channel++;
497 }
498 block = channel / 2;
499 dev->blk[block].isr |= ISR_RXRDY(channel);
500 ch->sr |= SR_RXRDY;
501 update_irq(dev, block);
502 }
503 }
504
505 static void hostdev_event(void *opaque, int event)
506 {
507 SCC2698Channel *ch = opaque;
508 switch (event) {
509 case CHR_EVENT_OPENED:
510 DPRINTF("Device %s opened\n", ch->dev->label);
511 break;
512 case CHR_EVENT_BREAK: {
513 uint8_t zero = 0;
514 DPRINTF("Device %s received break\n", ch->dev->label);
515
516 if (!(ch->sr & SR_BREAK)) {
517 IPOctalState *dev = ch->ipoctal;
518 unsigned block, channel = 0;
519
520 while (&dev->ch[channel] != ch) {
521 channel++;
522 }
523 block = channel / 2;
524
525 ch->sr |= SR_BREAK;
526 dev->blk[block].isr |= ISR_BREAK(channel);
527 }
528
529 /* Put a zero character in the buffer */
530 hostdev_receive(ch, &zero, 1);
531 }
532 break;
533 default:
534 DPRINTF("Device %s received event %d\n", ch->dev->label, event);
535 }
536 }
537
538 static int ipoctal_init(IPackDevice *ip)
539 {
540 IPOctalState *s = IPOCTAL(ip);
541 unsigned i;
542
543 for (i = 0; i < N_CHANNELS; i++) {
544 SCC2698Channel *ch = &s->ch[i];
545 ch->ipoctal = s;
546
547 /* Redirect IP-Octal channels to host character devices */
548 if (ch->devpath) {
549 const char chr_name[] = "ipoctal";
550 char label[ARRAY_SIZE(chr_name) + 2];
551 static int index;
552
553 snprintf(label, sizeof(label), "%s%d", chr_name, index);
554
555 ch->dev = qemu_chr_new(label, ch->devpath, NULL);
556
557 if (ch->dev) {
558 index++;
559 qemu_chr_add_handlers(ch->dev, hostdev_can_receive,
560 hostdev_receive, hostdev_event, ch);
561 DPRINTF("Redirecting channel %u to %s (%s)\n",
562 i, ch->devpath, label);
563 } else {
564 DPRINTF("Could not redirect channel %u to %s\n",
565 i, ch->devpath);
566 }
567 }
568 }
569
570 return 0;
571 }
572
573 static Property ipoctal_properties[] = {
574 DEFINE_PROP_STRING("serial0", IPOctalState, ch[0].devpath),
575 DEFINE_PROP_STRING("serial1", IPOctalState, ch[1].devpath),
576 DEFINE_PROP_STRING("serial2", IPOctalState, ch[2].devpath),
577 DEFINE_PROP_STRING("serial3", IPOctalState, ch[3].devpath),
578 DEFINE_PROP_STRING("serial4", IPOctalState, ch[4].devpath),
579 DEFINE_PROP_STRING("serial5", IPOctalState, ch[5].devpath),
580 DEFINE_PROP_STRING("serial6", IPOctalState, ch[6].devpath),
581 DEFINE_PROP_STRING("serial7", IPOctalState, ch[7].devpath),
582 DEFINE_PROP_END_OF_LIST(),
583 };
584
585 static void ipoctal_class_init(ObjectClass *klass, void *data)
586 {
587 DeviceClass *dc = DEVICE_CLASS(klass);
588 IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
589
590 ic->init = ipoctal_init;
591 ic->io_read = io_read;
592 ic->io_write = io_write;
593 ic->id_read = id_read;
594 ic->id_write = id_write;
595 ic->int_read = int_read;
596 ic->int_write = int_write;
597 ic->mem_read16 = mem_read16;
598 ic->mem_write16 = mem_write16;
599 ic->mem_read8 = mem_read8;
600 ic->mem_write8 = mem_write8;
601
602 dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
603 dc->props = ipoctal_properties;
604 dc->vmsd = &vmstate_ipoctal;
605 }
606
607 static const TypeInfo ipoctal_info = {
608 .name = TYPE_IPOCTAL,
609 .parent = TYPE_IPACK_DEVICE,
610 .instance_size = sizeof(IPOctalState),
611 .class_init = ipoctal_class_init,
612 };
613
614 static void ipoctal_register_types(void)
615 {
616 type_register_static(&ipoctal_info);
617 }
618
619 type_init(ipoctal_register_types)
Various patches