hw/openpic.c

   1 /*
   2  * OpenPIC emulation
   3  *
   4  * Copyright (c) 2004 Jocelyn Mayer
   5  *               2011 Alexander Graf
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 /*
  26  *
  27  * Based on OpenPic implementations:
  28  * - Intel GW80314 I/O companion chip developer's manual
  29  * - Motorola MPC8245 & MPC8540 user manuals.
  30  * - Motorola MCP750 (aka Raven) programmer manual.
  31  * - Motorola Harrier programmer manuel
  32  *
  33  * Serial interrupts, as implemented in Raven chipset are not supported yet.
  34  *
  35  */
  36 #include "hw.h"
  37 #include "ppc_mac.h"
  38 #include "pci/pci.h"
  39 #include "openpic.h"
  40 #include "sysbus.h"
  41 #include "pci/msi.h"
  42 #include "qemu/bitops.h"
  43 #include "ppc.h"
  44
  45 //#define DEBUG_OPENPIC
  46
  47 #ifdef DEBUG_OPENPIC
  48 static const int debug_openpic = 1;
  49 #else
  50 static const int debug_openpic = 0;
  51 #endif
  52
  53 #define DPRINTF(fmt, ...) do { \
  54         if (debug_openpic) { \
  55             printf(fmt , ## __VA_ARGS__); \
  56         } \
  57     } while (0)
  58
  59 #define MAX_CPU     15
  60 #define MAX_SRC     256
  61 #define MAX_TMR     4
  62 #define MAX_IPI     4
  63 #define MAX_MSI     8
  64 #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
  65 #define VID         0x03 /* MPIC version ID */
  66
  67 /* OpenPIC capability flags */
  68 #define OPENPIC_FLAG_IDR_CRIT     (1 << 0)
  69
  70 /* OpenPIC address map */
  71 #define OPENPIC_GLB_REG_START        0x0
  72 #define OPENPIC_GLB_REG_SIZE         0x10F0
  73 #define OPENPIC_TMR_REG_START        0x10F0
  74 #define OPENPIC_TMR_REG_SIZE         0x220
  75 #define OPENPIC_MSI_REG_START        0x1600
  76 #define OPENPIC_MSI_REG_SIZE         0x200
  77 #define OPENPIC_SRC_REG_START        0x10000
  78 #define OPENPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
  79 #define OPENPIC_CPU_REG_START        0x20000
  80 #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
  81
  82 /* Raven */
  83 #define RAVEN_MAX_CPU      2
  84 #define RAVEN_MAX_EXT     48
  85 #define RAVEN_MAX_IRQ     64
  86 #define RAVEN_MAX_TMR      MAX_TMR
  87 #define RAVEN_MAX_IPI      MAX_IPI
  88
  89 /* Interrupt definitions */
  90 #define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
  91 #define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
  92 #define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
  93 #define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
  94 /* First doorbell IRQ */
  95 #define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
  96
  97 /* FSL_MPIC_20 */
  98 #define FSL_MPIC_20_MAX_CPU      1
  99 #define FSL_MPIC_20_MAX_EXT     12
 100 #define FSL_MPIC_20_MAX_INT     64
 101 #define FSL_MPIC_20_MAX_IRQ     MAX_IRQ
 102
 103 /* Interrupt definitions */
 104 /* IRQs, accessible through the IRQ region */
 105 #define FSL_MPIC_20_EXT_IRQ      0x00
 106 #define FSL_MPIC_20_INT_IRQ      0x10
 107 #define FSL_MPIC_20_MSG_IRQ      0xb0
 108 #define FSL_MPIC_20_MSI_IRQ      0xe0
 109 /* These are available through separate regions, but
 110    for simplicity's sake mapped into the same number space */
 111 #define FSL_MPIC_20_TMR_IRQ      0x100
 112 #define FSL_MPIC_20_IPI_IRQ      0x104
 113
 114 /*
 115  * Block Revision Register1 (BRR1): QEMU does not fully emulate
 116  * any version on MPIC. So to start with, set the IP version to 0.
 117  *
 118  * NOTE: This is Freescale MPIC specific register. Keep it here till
 119  * this code is refactored for different variants of OPENPIC and MPIC.
 120  */
 121 #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */
 122 #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
 123 #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
 124
 125 #define FRR_NIRQ_SHIFT    16
 126 #define FRR_NCPU_SHIFT     8
 127 #define FRR_VID_SHIFT      0
 128
 129 #define VID_REVISION_1_2   2
 130 #define VID_REVISION_1_3   3
 131
 132 #define VIR_GENERIC      0x00000000 /* Generic Vendor ID */
 133
 134 #define GCR_RESET        0x80000000
 135 #define GCR_MODE_PASS    0x00000000
 136 #define GCR_MODE_MIXED   0x20000000
 137 #define GCR_MODE_PROXY   0x60000000
 138
 139 #define TBCR_CI           0x80000000 /* count inhibit */
 140 #define TCCR_TOG          0x80000000 /* toggles when decrement to zero */
 141
 142 #define IDR_EP_SHIFT      31
 143 #define IDR_EP_MASK       (1 << IDR_EP_SHIFT)
 144 #define IDR_CI0_SHIFT     30
 145 #define IDR_CI1_SHIFT     29
 146 #define IDR_P1_SHIFT      1
 147 #define IDR_P0_SHIFT      0
 148
 149 #define MSIIR_OFFSET       0x140
 150 #define MSIIR_SRS_SHIFT    29
 151 #define MSIIR_SRS_MASK     (0x7 << MSIIR_SRS_SHIFT)
 152 #define MSIIR_IBS_SHIFT    24
 153 #define MSIIR_IBS_MASK     (0x1f << MSIIR_IBS_SHIFT)
 154
 155 static int get_current_cpu(void)
 156 {
 157     CPUState *cpu_single_cpu;
 158
 159     if (!cpu_single_env) {
 160         return -1;
 161     }
 162
 163     cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
 164     return cpu_single_cpu->cpu_index;
 165 }
 166
 167 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
 168                                           int idx);
 169 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
 170                                        uint32_t val, int idx);
 171
 172 typedef enum IRQType {
 173     IRQ_TYPE_NORMAL = 0,
 174     IRQ_TYPE_FSLINT,        /* FSL internal interrupt -- level only */
 175     IRQ_TYPE_FSLSPECIAL,    /* FSL timer/IPI interrupt, edge, no polarity */
 176 } IRQType;
 177
 178 typedef struct IRQQueue {
 179     /* Round up to the nearest 64 IRQs so that the queue length
 180      * won't change when moving between 32 and 64 bit hosts.
 181      */
 182     unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)];
 183     int next;
 184     int priority;
 185 } IRQQueue;
 186
 187 typedef struct IRQSource {
 188     uint32_t ivpr;  /* IRQ vector/priority register */
 189     uint32_t idr;   /* IRQ destination register */
 190     uint32_t destmask; /* bitmap of CPU destinations */
 191     int last_cpu;
 192     int output;     /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
 193     int pending;    /* TRUE if IRQ is pending */
 194     IRQType type;
 195     bool level:1;   /* level-triggered */
 196     bool nomask:1;  /* critical interrupts ignore mask on some FSL MPICs */
 197 } IRQSource;
 198
 199 #define IVPR_MASK_SHIFT       31
 200 #define IVPR_MASK_MASK        (1 << IVPR_MASK_SHIFT)
 201 #define IVPR_ACTIVITY_SHIFT   30
 202 #define IVPR_ACTIVITY_MASK    (1 << IVPR_ACTIVITY_SHIFT)
 203 #define IVPR_MODE_SHIFT       29
 204 #define IVPR_MODE_MASK        (1 << IVPR_MODE_SHIFT)
 205 #define IVPR_POLARITY_SHIFT   23
 206 #define IVPR_POLARITY_MASK    (1 << IVPR_POLARITY_SHIFT)
 207 #define IVPR_SENSE_SHIFT      22
 208 #define IVPR_SENSE_MASK       (1 << IVPR_SENSE_SHIFT)
 209
 210 #define IVPR_PRIORITY_MASK     (0xF << 16)
 211 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
 212 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
 213
 214 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
 215 #define IDR_EP      0x80000000  /* external pin */
 216 #define IDR_CI      0x40000000  /* critical interrupt */
 217
 218 typedef struct IRQDest {
 219     int32_t ctpr; /* CPU current task priority */
 220     IRQQueue raised;
 221     IRQQueue servicing;
 222     qemu_irq *irqs;
 223
 224     /* Count of IRQ sources asserting on non-INT outputs */
 225     uint32_t outputs_active[OPENPIC_OUTPUT_NB];
 226 } IRQDest;
 227
 228 typedef struct OpenPICState {
 229     SysBusDevice busdev;
 230     MemoryRegion mem;
 231
 232     /* Behavior control */
 233     uint32_t model;
 234     uint32_t flags;
 235     uint32_t nb_irqs;
 236     uint32_t vid;
 237     uint32_t vir; /* Vendor identification register */
 238     uint32_t vector_mask;
 239     uint32_t tfrr_reset;
 240     uint32_t ivpr_reset;
 241     uint32_t idr_reset;
 242     uint32_t brr1;
 243     uint32_t mpic_mode_mask;
 244
 245     /* Sub-regions */
 246     MemoryRegion sub_io_mem[5];
 247
 248     /* Global registers */
 249     uint32_t frr; /* Feature reporting register */
 250     uint32_t gcr; /* Global configuration register  */
 251     uint32_t pir; /* Processor initialization register */
 252     uint32_t spve; /* Spurious vector register */
 253     uint32_t tfrr; /* Timer frequency reporting register */
 254     /* Source registers */
 255     IRQSource src[MAX_IRQ];
 256     /* Local registers per output pin */
 257     IRQDest dst[MAX_CPU];
 258     uint32_t nb_cpus;
 259     /* Timer registers */
 260     struct {
 261         uint32_t tccr;  /* Global timer current count register */
 262         uint32_t tbcr;  /* Global timer base count register */
 263     } timers[MAX_TMR];
 264     /* Shared MSI registers */
 265     struct {
 266         uint32_t msir;   /* Shared Message Signaled Interrupt Register */
 267     } msi[MAX_MSI];
 268     uint32_t max_irq;
 269     uint32_t irq_ipi0;
 270     uint32_t irq_tim0;
 271     uint32_t irq_msi;
 272 } OpenPICState;
 273
 274 static inline void IRQ_setbit(IRQQueue *q, int n_IRQ)
 275 {
 276     set_bit(n_IRQ, q->queue);
 277 }
 278
 279 static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ)
 280 {
 281     clear_bit(n_IRQ, q->queue);
 282 }
 283
 284 static inline int IRQ_testbit(IRQQueue *q, int n_IRQ)
 285 {
 286     return test_bit(n_IRQ, q->queue);
 287 }
 288
 289 static void IRQ_check(OpenPICState *opp, IRQQueue *q)
 290 {
 291     int irq = -1;
 292     int next = -1;
 293     int priority = -1;
 294
 295     for (;;) {
 296         irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
 297         if (irq == opp->max_irq) {
 298             break;
 299         }
 300
 301         DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
 302                 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
 303
 304         if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
 305             next = irq;
 306             priority = IVPR_PRIORITY(opp->src[irq].ivpr);
 307         }
 308     }
 309
 310     q->next = next;
 311     q->priority = priority;
 312 }
 313
 314 static int IRQ_get_next(OpenPICState *opp, IRQQueue *q)
 315 {
 316     /* XXX: optimize */
 317     IRQ_check(opp, q);
 318
 319     return q->next;
 320 }
 321
 322 static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
 323                            bool active, bool was_active)
 324 {
 325     IRQDest *dst;
 326     IRQSource *src;
 327     int priority;
 328
 329     dst = &opp->dst[n_CPU];
 330     src = &opp->src[n_IRQ];
 331
 332     DPRINTF("%s: IRQ %d active %d was %d\n",
 333             __func__, n_IRQ, active, was_active);
 334
 335     if (src->output != OPENPIC_OUTPUT_INT) {
 336         DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
 337                 __func__, src->output, n_IRQ, active, was_active,
 338                 dst->outputs_active[src->output]);
 339
 340         /* On Freescale MPIC, critical interrupts ignore priority,
 341          * IACK, EOI, etc.  Before MPIC v4.1 they also ignore
 342          * masking.
 343          */
 344         if (active) {
 345             if (!was_active && dst->outputs_active[src->output]++ == 0) {
 346                 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
 347                         __func__, src->output, n_CPU, n_IRQ);
 348                 qemu_irq_raise(dst->irqs[src->output]);
 349             }
 350         } else {
 351             if (was_active && --dst->outputs_active[src->output] == 0) {
 352                 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
 353                         __func__, src->output, n_CPU, n_IRQ);
 354                 qemu_irq_lower(dst->irqs[src->output]);
 355             }
 356         }
 357
 358         return;
 359     }
 360
 361     priority = IVPR_PRIORITY(src->ivpr);
 362
 363     /* Even if the interrupt doesn't have enough priority,
 364      * it is still raised, in case ctpr is lowered later.
 365      */
 366     if (active) {
 367         IRQ_setbit(&dst->raised, n_IRQ);
 368     } else {
 369         IRQ_resetbit(&dst->raised, n_IRQ);
 370     }
 371
 372     IRQ_check(opp, &dst->raised);
 373
 374     if (active && priority <= dst->ctpr) {
 375         DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
 376                 __func__, n_IRQ, priority, dst->ctpr, n_CPU);
 377         active = 0;
 378     }
 379
 380     if (active) {
 381         if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
 382                 priority <= dst->servicing.priority) {
 383             DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
 384                     __func__, n_IRQ, dst->servicing.next, n_CPU);
 385         } else {
 386             DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
 387                     __func__, n_CPU, n_IRQ, dst->raised.next);
 388             qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
 389         }
 390     } else {
 391         IRQ_get_next(opp, &dst->servicing);
 392         if (dst->raised.priority > dst->ctpr &&
 393                 dst->raised.priority > dst->servicing.priority) {
 394             DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
 395                     __func__, n_IRQ, dst->raised.next, dst->raised.priority,
 396                     dst->ctpr, dst->servicing.priority, n_CPU);
 397             /* IRQ line stays asserted */
 398         } else {
 399             DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
 400                     __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU);
 401             qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
 402         }
 403     }
 404 }
 405
 406 /* update pic state because registers for n_IRQ have changed value */
 407 static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
 408 {
 409     IRQSource *src;
 410     bool active, was_active;
 411     int i;
 412
 413     src = &opp->src[n_IRQ];
 414     active = src->pending;
 415
 416     if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
 417         /* Interrupt source is disabled */
 418         DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
 419         active = false;
 420     }
 421
 422     was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK);
 423
 424     /*
 425      * We don't have a similar check for already-active because
 426      * ctpr may have changed and we need to withdraw the interrupt.
 427      */
 428     if (!active && !was_active) {
 429         DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
 430         return;
 431     }
 432
 433     if (active) {
 434         src->ivpr |= IVPR_ACTIVITY_MASK;
 435     } else {
 436         src->ivpr &= ~IVPR_ACTIVITY_MASK;
 437     }
 438
 439     if (src->idr == 0) {
 440         /* No target */
 441         DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
 442         return;
 443     }
 444
 445     if (src->idr == (1 << src->last_cpu)) {
 446         /* Only one CPU is allowed to receive this IRQ */
 447         IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
 448     } else if (!(src->ivpr & IVPR_MODE_MASK)) {
 449         /* Directed delivery mode */
 450         for (i = 0; i < opp->nb_cpus; i++) {
 451             if (src->destmask & (1 << i)) {
 452                 IRQ_local_pipe(opp, i, n_IRQ, active, was_active);
 453             }
 454         }
 455     } else {
 456         /* Distributed delivery mode */
 457         for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
 458             if (i == opp->nb_cpus) {
 459                 i = 0;
 460             }
 461             if (src->destmask & (1 << i)) {
 462                 IRQ_local_pipe(opp, i, n_IRQ, active, was_active);
 463                 src->last_cpu = i;
 464                 break;
 465             }
 466         }
 467     }
 468 }
 469
 470 static void openpic_set_irq(void *opaque, int n_IRQ, int level)
 471 {
 472     OpenPICState *opp = opaque;
 473     IRQSource *src;
 474
 475     if (n_IRQ >= MAX_IRQ) {
 476         fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ);
 477         abort();
 478     }
 479
 480     src = &opp->src[n_IRQ];
 481     DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
 482             n_IRQ, level, src->ivpr);
 483     if (src->level) {
 484         /* level-sensitive irq */
 485         src->pending = level;
 486         openpic_update_irq(opp, n_IRQ);
 487     } else {
 488         /* edge-sensitive irq */
 489         if (level) {
 490             src->pending = 1;
 491             openpic_update_irq(opp, n_IRQ);
 492         }
 493
 494         if (src->output != OPENPIC_OUTPUT_INT) {
 495             /* Edge-triggered interrupts shouldn't be used
 496              * with non-INT delivery, but just in case,
 497              * try to make it do something sane rather than
 498              * cause an interrupt storm.  This is close to
 499              * what you'd probably see happen in real hardware.
 500              */
 501             src->pending = 0;
 502             openpic_update_irq(opp, n_IRQ);
 503         }
 504     }
 505 }
 506
 507 static void openpic_reset(DeviceState *d)
 508 {
 509     OpenPICState *opp = FROM_SYSBUS(typeof(*opp), SYS_BUS_DEVICE(d));
 510     int i;
 511
 512     opp->gcr = GCR_RESET;
 513     /* Initialise controller registers */
 514     opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
 515                ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) |
 516                (opp->vid << FRR_VID_SHIFT);
 517
 518     opp->pir = 0;
 519     opp->spve = -1 & opp->vector_mask;
 520     opp->tfrr = opp->tfrr_reset;
 521     /* Initialise IRQ sources */
 522     for (i = 0; i < opp->max_irq; i++) {
 523         opp->src[i].ivpr = opp->ivpr_reset;
 524         opp->src[i].idr  = opp->idr_reset;
 525
 526         switch (opp->src[i].type) {
 527         case IRQ_TYPE_NORMAL:
 528             opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK);
 529             break;
 530
 531         case IRQ_TYPE_FSLINT:
 532             opp->src[i].ivpr |= IVPR_POLARITY_MASK;
 533             break;
 534
 535         case IRQ_TYPE_FSLSPECIAL:
 536             break;
 537         }
 538     }
 539     /* Initialise IRQ destinations */
 540     for (i = 0; i < MAX_CPU; i++) {
 541         opp->dst[i].ctpr      = 15;
 542         memset(&opp->dst[i].raised, 0, sizeof(IRQQueue));
 543         opp->dst[i].raised.next = -1;
 544         memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue));
 545         opp->dst[i].servicing.next = -1;
 546     }
 547     /* Initialise timers */
 548     for (i = 0; i < MAX_TMR; i++) {
 549         opp->timers[i].tccr = 0;
 550         opp->timers[i].tbcr = TBCR_CI;
 551     }
 552     /* Go out of RESET state */
 553     opp->gcr = 0;
 554 }
 555
 556 static inline uint32_t read_IRQreg_idr(OpenPICState *opp, int n_IRQ)
 557 {
 558     return opp->src[n_IRQ].idr;
 559 }
 560
 561 static inline uint32_t read_IRQreg_ivpr(OpenPICState *opp, int n_IRQ)
 562 {
 563     return opp->src[n_IRQ].ivpr;
 564 }
 565
 566 static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val)
 567 {
 568     IRQSource *src = &opp->src[n_IRQ];
 569     uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;
 570     uint32_t crit_mask = 0;
 571     uint32_t mask = normal_mask;
 572     int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
 573     int i;
 574
 575     if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
 576         crit_mask = mask << crit_shift;
 577         mask |= crit_mask | IDR_EP;
 578     }
 579
 580     src->idr = val & mask;
 581     DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
 582
 583     if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
 584         if (src->idr & crit_mask) {
 585             if (src->idr & normal_mask) {
 586                 DPRINTF("%s: IRQ configured for multiple output types, using "
 587                         "critical\n", __func__);
 588             }
 589
 590             src->output = OPENPIC_OUTPUT_CINT;
 591             src->nomask = true;
 592             src->destmask = 0;
 593
 594             for (i = 0; i < opp->nb_cpus; i++) {
 595                 int n_ci = IDR_CI0_SHIFT - i;
 596
 597                 if (src->idr & (1UL << n_ci)) {
 598                     src->destmask |= 1UL << i;
 599                 }
 600             }
 601         } else {
 602             src->output = OPENPIC_OUTPUT_INT;
 603             src->nomask = false;
 604             src->destmask = src->idr & normal_mask;
 605         }
 606     } else {
 607         src->destmask = src->idr;
 608     }
 609 }
 610
 611 static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
 612 {
 613     uint32_t mask;
 614
 615     /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
 616      * the polarity bit is read-only on internal interrupts.
 617      */
 618     mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
 619            IVPR_POLARITY_MASK | opp->vector_mask;
 620
 621     /* ACTIVITY bit is read-only */
 622     opp->src[n_IRQ].ivpr =
 623         (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
 624
 625     /* For FSL internal interrupts, The sense bit is reserved and zero,
 626      * and the interrupt is always level-triggered.  Timers and IPIs
 627      * have no sense or polarity bits, and are edge-triggered.
 628      */
 629     switch (opp->src[n_IRQ].type) {
 630     case IRQ_TYPE_NORMAL:
 631         opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
 632         break;
 633
 634     case IRQ_TYPE_FSLINT:
 635         opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
 636         break;
 637
 638     case IRQ_TYPE_FSLSPECIAL:
 639         opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
 640         break;
 641     }
 642
 643     openpic_update_irq(opp, n_IRQ);
 644     DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
 645             opp->src[n_IRQ].ivpr);
 646 }
 647
 648 static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
 649 {
 650     bool mpic_proxy = false;
 651
 652     if (val & GCR_RESET) {
 653         openpic_reset(&opp->busdev.qdev);
 654         return;
 655     }
 656
 657     opp->gcr &= ~opp->mpic_mode_mask;
 658     opp->gcr |= val & opp->mpic_mode_mask;
 659
 660     /* Set external proxy mode */
 661     if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
 662         mpic_proxy = true;
 663     }
 664
 665     ppce500_set_mpic_proxy(mpic_proxy);
 666 }
 667
 668 static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
 669                               unsigned len)
 670 {
 671     OpenPICState *opp = opaque;
 672     IRQDest *dst;
 673     int idx;
 674
 675     DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
 676             __func__, addr, val);
 677     if (addr & 0xF) {
 678         return;
 679     }
 680     switch (addr) {
 681     case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
 682         break;
 683     case 0x40:
 684     case 0x50:
 685     case 0x60:
 686     case 0x70:
 687     case 0x80:
 688     case 0x90:
 689     case 0xA0:
 690     case 0xB0:
 691         openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
 692         break;
 693     case 0x1000: /* FRR */
 694         break;
 695     case 0x1020: /* GCR */
 696         openpic_gcr_write(opp, val);
 697         break;
 698     case 0x1080: /* VIR */
 699         break;
 700     case 0x1090: /* PIR */
 701         for (idx = 0; idx < opp->nb_cpus; idx++) {
 702             if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
 703                 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
 704                 dst = &opp->dst[idx];
 705                 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
 706             } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
 707                 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
 708                 dst = &opp->dst[idx];
 709                 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
 710             }
 711         }
 712         opp->pir = val;
 713         break;
 714     case 0x10A0: /* IPI_IVPR */
 715     case 0x10B0:
 716     case 0x10C0:
 717     case 0x10D0:
 718         {
 719             int idx;
 720             idx = (addr - 0x10A0) >> 4;
 721             write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
 722         }
 723         break;
 724     case 0x10E0: /* SPVE */
 725         opp->spve = val & opp->vector_mask;
 726         break;
 727     default:
 728         break;
 729     }
 730 }
 731
 732 static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
 733 {
 734     OpenPICState *opp = opaque;
 735     uint32_t retval;
 736
 737     DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
 738     retval = 0xFFFFFFFF;
 739     if (addr & 0xF) {
 740         return retval;
 741     }
 742     switch (addr) {
 743     case 0x1000: /* FRR */
 744         retval = opp->frr;
 745         break;
 746     case 0x1020: /* GCR */
 747         retval = opp->gcr;
 748         break;
 749     case 0x1080: /* VIR */
 750         retval = opp->vir;
 751         break;
 752     case 0x1090: /* PIR */
 753         retval = 0x00000000;
 754         break;
 755     case 0x00: /* Block Revision Register1 (BRR1) */
 756         retval = opp->brr1;
 757         break;
 758     case 0x40:
 759     case 0x50:
 760     case 0x60:
 761     case 0x70:
 762     case 0x80:
 763     case 0x90:
 764     case 0xA0:
 765     case 0xB0:
 766         retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
 767         break;
 768     case 0x10A0: /* IPI_IVPR */
 769     case 0x10B0:
 770     case 0x10C0:
 771     case 0x10D0:
 772         {
 773             int idx;
 774             idx = (addr - 0x10A0) >> 4;
 775             retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
 776         }
 777         break;
 778     case 0x10E0: /* SPVE */
 779         retval = opp->spve;
 780         break;
 781     default:
 782         break;
 783     }
 784     DPRINTF("%s: => 0x%08x\n", __func__, retval);
 785
 786     return retval;
 787 }
 788
 789 static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
 790                                 unsigned len)
 791 {
 792     OpenPICState *opp = opaque;
 793     int idx;
 794
 795     DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
 796             __func__, addr, val);
 797     if (addr & 0xF) {
 798         return;
 799     }
 800     idx = (addr >> 6) & 0x3;
 801     addr = addr & 0x30;
 802
 803     if (addr == 0x0) {
 804         /* TFRR */
 805         opp->tfrr = val;
 806         return;
 807     }
 808     switch (addr & 0x30) {
 809     case 0x00: /* TCCR */
 810         break;
 811     case 0x10: /* TBCR */
 812         if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&
 813             (val & TBCR_CI) == 0 &&
 814             (opp->timers[idx].tbcr & TBCR_CI) != 0) {
 815             opp->timers[idx].tccr &= ~TCCR_TOG;
 816         }
 817         opp->timers[idx].tbcr = val;
 818         break;
 819     case 0x20: /* TVPR */
 820         write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
 821         break;
 822     case 0x30: /* TDR */
 823         write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
 824         break;
 825     }
 826 }
 827
 828 static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
 829 {
 830     OpenPICState *opp = opaque;
 831     uint32_t retval = -1;
 832     int idx;
 833
 834     DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
 835     if (addr & 0xF) {
 836         goto out;
 837     }
 838     idx = (addr >> 6) & 0x3;
 839     if (addr == 0x0) {
 840         /* TFRR */
 841         retval = opp->tfrr;
 842         goto out;
 843     }
 844     switch (addr & 0x30) {
 845     case 0x00: /* TCCR */
 846         retval = opp->timers[idx].tccr;
 847         break;
 848     case 0x10: /* TBCR */
 849         retval = opp->timers[idx].tbcr;
 850         break;
 851     case 0x20: /* TIPV */
 852         retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
 853         break;
 854     case 0x30: /* TIDE (TIDR) */
 855         retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
 856         break;
 857     }
 858
 859 out:
 860     DPRINTF("%s: => 0x%08x\n", __func__, retval);
 861
 862     return retval;
 863 }
 864
 865 static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
 866                               unsigned len)
 867 {
 868     OpenPICState *opp = opaque;
 869     int idx;
 870
 871     DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
 872             __func__, addr, val);
 873     if (addr & 0xF) {
 874         return;
 875     }
 876     addr = addr & 0xFFF0;
 877     idx = addr >> 5;
 878     if (addr & 0x10) {
 879         /* EXDE / IFEDE / IEEDE */
 880         write_IRQreg_idr(opp, idx, val);
 881     } else {
 882         /* EXVP / IFEVP / IEEVP */
 883         write_IRQreg_ivpr(opp, idx, val);
 884     }
 885 }
 886
 887 static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
 888 {
 889     OpenPICState *opp = opaque;
 890     uint32_t retval;
 891     int idx;
 892
 893     DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
 894     retval = 0xFFFFFFFF;
 895     if (addr & 0xF) {
 896         return retval;
 897     }
 898     addr = addr & 0xFFF0;
 899     idx = addr >> 5;
 900     if (addr & 0x10) {
 901         /* EXDE / IFEDE / IEEDE */
 902         retval = read_IRQreg_idr(opp, idx);
 903     } else {
 904         /* EXVP / IFEVP / IEEVP */
 905         retval = read_IRQreg_ivpr(opp, idx);
 906     }
 907     DPRINTF("%s: => 0x%08x\n", __func__, retval);
 908
 909     return retval;
 910 }
 911
 912 static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val,
 913                               unsigned size)
 914 {
 915     OpenPICState *opp = opaque;
 916     int idx = opp->irq_msi;
 917     int srs, ibs;
 918
 919     DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n",
 920             __func__, addr, val);
 921     if (addr & 0xF) {
 922         return;
 923     }
 924
 925     switch (addr) {
 926     case MSIIR_OFFSET:
 927         srs = val >> MSIIR_SRS_SHIFT;
 928         idx += srs;
 929         ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
 930         opp->msi[srs].msir |= 1 << ibs;
 931         openpic_set_irq(opp, idx, 1);
 932         break;
 933     default:
 934         /* most registers are read-only, thus ignored */
 935         break;
 936     }
 937 }
 938
 939 static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
 940 {
 941     OpenPICState *opp = opaque;
 942     uint64_t r = 0;
 943     int i, srs;
 944
 945     DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
 946     if (addr & 0xF) {
 947         return -1;
 948     }
 949
 950     srs = addr >> 4;
 951
 952     switch (addr) {
 953     case 0x00:
 954     case 0x10:
 955     case 0x20:
 956     case 0x30:
 957     case 0x40:
 958     case 0x50:
 959     case 0x60:
 960     case 0x70: /* MSIRs */
 961         r = opp->msi[srs].msir;
 962         /* Clear on read */
 963         opp->msi[srs].msir = 0;
 964         openpic_set_irq(opp, opp->irq_msi + srs, 0);
 965         break;
 966     case 0x120: /* MSISR */
 967         for (i = 0; i < MAX_MSI; i++) {
 968             r |= (opp->msi[i].msir ? 1 : 0) << i;
 969         }
 970         break;
 971     }
 972
 973     return r;
 974 }
 975
 976 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
 977                                        uint32_t val, int idx)
 978 {
 979     OpenPICState *opp = opaque;
 980     IRQSource *src;
 981     IRQDest *dst;
 982     int s_IRQ, n_IRQ;
 983
 984     DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx,
 985             addr, val);
 986
 987     if (idx < 0) {
 988         return;
 989     }
 990
 991     if (addr & 0xF) {
 992         return;
 993     }
 994     dst = &opp->dst[idx];
 995     addr &= 0xFF0;
 996     switch (addr) {
 997     case 0x40: /* IPIDR */
 998     case 0x50:
 999     case 0x60:
1000     case 0x70:
1001         idx = (addr - 0x40) >> 4;
1002         /* we use IDE as mask which CPUs to deliver the IPI to still. */
1003         write_IRQreg_idr(opp, opp->irq_ipi0 + idx,
1004                          opp->src[opp->irq_ipi0 + idx].idr | val);
1005         openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
1006         openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
1007         break;
1008     case 0x80: /* CTPR */
1009         dst->ctpr = val & 0x0000000F;
1010
1011         DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1012                 __func__, idx, dst->ctpr, dst->raised.priority,
1013                 dst->servicing.priority);
1014
1015         if (dst->raised.priority <= dst->ctpr) {
1016             DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1017                     __func__, idx);
1018             qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
1019         } else if (dst->raised.priority > dst->servicing.priority) {
1020             DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1021                     __func__, idx, dst->raised.next);
1022             qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]);
1023         }
1024
1025         break;
1026     case 0x90: /* WHOAMI */
1027         /* Read-only register */
1028         break;
1029     case 0xA0: /* IACK */
1030         /* Read-only register */
1031         break;
1032     case 0xB0: /* EOI */
1033         DPRINTF("EOI\n");
1034         s_IRQ = IRQ_get_next(opp, &dst->servicing);
1035
1036         if (s_IRQ < 0) {
1037             DPRINTF("%s: EOI with no interrupt in service\n", __func__);
1038             break;
1039         }
1040
1041         IRQ_resetbit(&dst->servicing, s_IRQ);
1042         /* Set up next servicing IRQ */
1043         s_IRQ = IRQ_get_next(opp, &dst->servicing);
1044         /* Check queued interrupts. */
1045         n_IRQ = IRQ_get_next(opp, &dst->raised);
1046         src = &opp->src[n_IRQ];
1047         if (n_IRQ != -1 &&
1048             (s_IRQ == -1 ||
1049              IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
1050             DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
1051                     idx, n_IRQ);
1052             qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]);
1053         }
1054         break;
1055     default:
1056         break;
1057     }
1058 }
1059
1060 static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
1061                               unsigned len)
1062 {
1063     openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
1064 }
1065
1066
1067 static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu)
1068 {
1069     IRQSource *src;
1070     int retval, irq;
1071
1072     DPRINTF("Lower OpenPIC INT output\n");
1073     qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
1074
1075     irq = IRQ_get_next(opp, &dst->raised);
1076     DPRINTF("IACK: irq=%d\n", irq);
1077
1078     if (irq == -1) {
1079         /* No more interrupt pending */
1080         return opp->spve;
1081     }
1082
1083     src = &opp->src[irq];
1084     if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
1085             !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) {
1086         fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1087                 __func__, irq, dst->ctpr, src->ivpr);
1088         openpic_update_irq(opp, irq);
1089         retval = opp->spve;
1090     } else {
1091         /* IRQ enter servicing state */
1092         IRQ_setbit(&dst->servicing, irq);
1093         retval = IVPR_VECTOR(opp, src->ivpr);
1094     }
1095
1096     if (!src->level) {
1097         /* edge-sensitive IRQ */
1098         src->ivpr &= ~IVPR_ACTIVITY_MASK;
1099         src->pending = 0;
1100         IRQ_resetbit(&dst->raised, irq);
1101     }
1102
1103     if ((irq >= opp->irq_ipi0) &&  (irq < (opp->irq_ipi0 + MAX_IPI))) {
1104         src->idr &= ~(1 << cpu);
1105         if (src->idr && !src->level) {
1106             /* trigger on CPUs that didn't know about it yet */
1107             openpic_set_irq(opp, irq, 1);
1108             openpic_set_irq(opp, irq, 0);
1109             /* if all CPUs knew about it, set active bit again */
1110             src->ivpr |= IVPR_ACTIVITY_MASK;
1111         }
1112     }
1113
1114     return retval;
1115 }
1116
1117 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
1118                                           int idx)
1119 {
1120     OpenPICState *opp = opaque;
1121     IRQDest *dst;
1122     uint32_t retval;
1123
1124     DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr);
1125     retval = 0xFFFFFFFF;
1126
1127     if (idx < 0) {
1128         return retval;
1129     }
1130
1131     if (addr & 0xF) {
1132         return retval;
1133     }
1134     dst = &opp->dst[idx];
1135     addr &= 0xFF0;
1136     switch (addr) {
1137     case 0x80: /* CTPR */
1138         retval = dst->ctpr;
1139         break;
1140     case 0x90: /* WHOAMI */
1141         retval = idx;
1142         break;
1143     case 0xA0: /* IACK */
1144         retval = openpic_iack(opp, dst, idx);
1145         break;
1146     case 0xB0: /* EOI */
1147         retval = 0;
1148         break;
1149     default:
1150         break;
1151     }
1152     DPRINTF("%s: => 0x%08x\n", __func__, retval);
1153
1154     return retval;
1155 }
1156
1157 static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
1158 {
1159     return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
1160 }
1161
1162 static const MemoryRegionOps openpic_glb_ops_le = {
1163     .write = openpic_gbl_write,
1164     .read  = openpic_gbl_read,
1165     .endianness = DEVICE_LITTLE_ENDIAN,
1166     .impl = {
1167         .min_access_size = 4,
1168         .max_access_size = 4,
1169     },
1170 };
1171
1172 static const MemoryRegionOps openpic_glb_ops_be = {
1173     .write = openpic_gbl_write,
1174     .read  = openpic_gbl_read,
1175     .endianness = DEVICE_BIG_ENDIAN,
1176     .impl = {
1177         .min_access_size = 4,
1178         .max_access_size = 4,
1179     },
1180 };
1181
1182 static const MemoryRegionOps openpic_tmr_ops_le = {
1183     .write = openpic_tmr_write,
1184     .read  = openpic_tmr_read,
1185     .endianness = DEVICE_LITTLE_ENDIAN,
1186     .impl = {
1187         .min_access_size = 4,
1188         .max_access_size = 4,
1189     },
1190 };
1191
1192 static const MemoryRegionOps openpic_tmr_ops_be = {
1193     .write = openpic_tmr_write,
1194     .read  = openpic_tmr_read,
1195     .endianness = DEVICE_BIG_ENDIAN,
1196     .impl = {
1197         .min_access_size = 4,
1198         .max_access_size = 4,
1199     },
1200 };
1201
1202 static const MemoryRegionOps openpic_cpu_ops_le = {
1203     .write = openpic_cpu_write,
1204     .read  = openpic_cpu_read,
1205     .endianness = DEVICE_LITTLE_ENDIAN,
1206     .impl = {
1207         .min_access_size = 4,
1208         .max_access_size = 4,
1209     },
1210 };
1211
1212 static const MemoryRegionOps openpic_cpu_ops_be = {
1213     .write = openpic_cpu_write,
1214     .read  = openpic_cpu_read,
1215     .endianness = DEVICE_BIG_ENDIAN,
1216     .impl = {
1217         .min_access_size = 4,
1218         .max_access_size = 4,
1219     },
1220 };
1221
1222 static const MemoryRegionOps openpic_src_ops_le = {
1223     .write = openpic_src_write,
1224     .read  = openpic_src_read,
1225     .endianness = DEVICE_LITTLE_ENDIAN,
1226     .impl = {
1227         .min_access_size = 4,
1228         .max_access_size = 4,
1229     },
1230 };
1231
1232 static const MemoryRegionOps openpic_src_ops_be = {
1233     .write = openpic_src_write,
1234     .read  = openpic_src_read,
1235     .endianness = DEVICE_BIG_ENDIAN,
1236     .impl = {
1237         .min_access_size = 4,
1238         .max_access_size = 4,
1239     },
1240 };
1241
1242 static const MemoryRegionOps openpic_msi_ops_le = {
1243     .read = openpic_msi_read,
1244     .write = openpic_msi_write,
1245     .endianness = DEVICE_LITTLE_ENDIAN,
1246     .impl = {
1247         .min_access_size = 4,
1248         .max_access_size = 4,
1249     },
1250 };
1251
1252 static const MemoryRegionOps openpic_msi_ops_be = {
1253     .read = openpic_msi_read,
1254     .write = openpic_msi_write,
1255     .endianness = DEVICE_BIG_ENDIAN,
1256     .impl = {
1257         .min_access_size = 4,
1258         .max_access_size = 4,
1259     },
1260 };
1261
1262 static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q)
1263 {
1264     unsigned int i;
1265
1266     for (i = 0; i < ARRAY_SIZE(q->queue); i++) {
1267         /* Always put the lower half of a 64-bit long first, in case we
1268          * restore on a 32-bit host.  The least significant bits correspond
1269          * to lower IRQ numbers in the bitmap.
1270          */
1271         qemu_put_be32(f, (uint32_t)q->queue[i]);
1272 #if LONG_MAX > 0x7FFFFFFF
1273         qemu_put_be32(f, (uint32_t)(q->queue[i] >> 32));
1274 #endif
1275     }
1276
1277     qemu_put_sbe32s(f, &q->next);
1278     qemu_put_sbe32s(f, &q->priority);
1279 }
1280
1281 static void openpic_save(QEMUFile* f, void *opaque)
1282 {
1283     OpenPICState *opp = (OpenPICState *)opaque;
1284     unsigned int i;
1285
1286     qemu_put_be32s(f, &opp->gcr);
1287     qemu_put_be32s(f, &opp->vir);
1288     qemu_put_be32s(f, &opp->pir);
1289     qemu_put_be32s(f, &opp->spve);
1290     qemu_put_be32s(f, &opp->tfrr);
1291
1292     qemu_put_be32s(f, &opp->nb_cpus);
1293
1294     for (i = 0; i < opp->nb_cpus; i++) {
1295         qemu_put_sbe32s(f, &opp->dst[i].ctpr);
1296         openpic_save_IRQ_queue(f, &opp->dst[i].raised);
1297         openpic_save_IRQ_queue(f, &opp->dst[i].servicing);
1298         qemu_put_buffer(f, (uint8_t *)&opp->dst[i].outputs_active,
1299                         sizeof(opp->dst[i].outputs_active));
1300     }
1301
1302     for (i = 0; i < MAX_TMR; i++) {
1303         qemu_put_be32s(f, &opp->timers[i].tccr);
1304         qemu_put_be32s(f, &opp->timers[i].tbcr);
1305     }
1306
1307     for (i = 0; i < opp->max_irq; i++) {
1308         qemu_put_be32s(f, &opp->src[i].ivpr);
1309         qemu_put_be32s(f, &opp->src[i].idr);
1310         qemu_put_sbe32s(f, &opp->src[i].last_cpu);
1311         qemu_put_sbe32s(f, &opp->src[i].pending);
1312     }
1313 }
1314
1315 static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
1316 {
1317     unsigned int i;
1318
1319     for (i = 0; i < ARRAY_SIZE(q->queue); i++) {
1320         unsigned long val;
1321
1322         val = qemu_get_be32(f);
1323 #if LONG_MAX > 0x7FFFFFFF
1324         val <<= 32;
1325         val |= qemu_get_be32(f);
1326 #endif
1327
1328         q->queue[i] = val;
1329     }
1330
1331     qemu_get_sbe32s(f, &q->next);
1332     qemu_get_sbe32s(f, &q->priority);
1333 }
1334
1335 static int openpic_load(QEMUFile* f, void *opaque, int version_id)
1336 {
1337     OpenPICState *opp = (OpenPICState *)opaque;
1338     unsigned int i;
1339
1340     if (version_id != 1) {
1341         return -EINVAL;
1342     }
1343
1344     qemu_get_be32s(f, &opp->gcr);
1345     qemu_get_be32s(f, &opp->vir);
1346     qemu_get_be32s(f, &opp->pir);
1347     qemu_get_be32s(f, &opp->spve);
1348     qemu_get_be32s(f, &opp->tfrr);
1349
1350     qemu_get_be32s(f, &opp->nb_cpus);
1351
1352     for (i = 0; i < opp->nb_cpus; i++) {
1353         qemu_get_sbe32s(f, &opp->dst[i].ctpr);
1354         openpic_load_IRQ_queue(f, &opp->dst[i].raised);
1355         openpic_load_IRQ_queue(f, &opp->dst[i].servicing);
1356         qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active,
1357                         sizeof(opp->dst[i].outputs_active));
1358     }
1359
1360     for (i = 0; i < MAX_TMR; i++) {
1361         qemu_get_be32s(f, &opp->timers[i].tccr);
1362         qemu_get_be32s(f, &opp->timers[i].tbcr);
1363     }
1364
1365     for (i = 0; i < opp->max_irq; i++) {
1366         uint32_t val;
1367
1368         val = qemu_get_be32(f);
1369         write_IRQreg_idr(opp, i, val);
1370         val = qemu_get_be32(f);
1371         write_IRQreg_ivpr(opp, i, val);
1372
1373         qemu_get_be32s(f, &opp->src[i].ivpr);
1374         qemu_get_be32s(f, &opp->src[i].idr);
1375         qemu_get_sbe32s(f, &opp->src[i].last_cpu);
1376         qemu_get_sbe32s(f, &opp->src[i].pending);
1377     }
1378
1379     return 0;
1380 }
1381
1382 typedef struct MemReg {
1383     const char             *name;
1384     MemoryRegionOps const  *ops;
1385     bool                   map;
1386     hwaddr      start_addr;
1387     ram_addr_t              size;
1388 } MemReg;
1389
1390 static int openpic_init(SysBusDevice *dev)
1391 {
1392     OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev);
1393     int i, j;
1394     MemReg list_le[] = {
1395         {"glb", &openpic_glb_ops_le, true,
1396                 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1397         {"tmr", &openpic_tmr_ops_le, true,
1398                 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1399         {"msi", &openpic_msi_ops_le, true,
1400                 OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
1401         {"src", &openpic_src_ops_le, true,
1402                 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1403         {"cpu", &openpic_cpu_ops_le, true,
1404                 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1405     };
1406     MemReg list_be[] = {
1407         {"glb", &openpic_glb_ops_be, true,
1408                 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1409         {"tmr", &openpic_tmr_ops_be, true,
1410                 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1411         {"msi", &openpic_msi_ops_be, true,
1412                 OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
1413         {"src", &openpic_src_ops_be, true,
1414                 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1415         {"cpu", &openpic_cpu_ops_be, true,
1416                 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1417     };
1418     MemReg *list;
1419
1420     switch (opp->model) {
1421     case OPENPIC_MODEL_FSL_MPIC_20:
1422     default:
1423         opp->flags |= OPENPIC_FLAG_IDR_CRIT;
1424         opp->nb_irqs = 80;
1425         opp->vid = VID_REVISION_1_2;
1426         opp->vir = VIR_GENERIC;
1427         opp->vector_mask = 0xFFFF;
1428         opp->tfrr_reset = 0;
1429         opp->ivpr_reset = IVPR_MASK_MASK;
1430         opp->idr_reset = 1 << 0;
1431         opp->max_irq = FSL_MPIC_20_MAX_IRQ;
1432         opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
1433         opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
1434         opp->irq_msi = FSL_MPIC_20_MSI_IRQ;
1435         opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
1436         /* XXX really only available as of MPIC 4.0 */
1437         opp->mpic_mode_mask = GCR_MODE_PROXY;
1438
1439         msi_supported = true;
1440         list = list_be;
1441
1442         for (i = 0; i < FSL_MPIC_20_MAX_EXT; i++) {
1443             opp->src[i].level = false;
1444         }
1445
1446         /* Internal interrupts, including message and MSI */
1447         for (i = 16; i < MAX_SRC; i++) {
1448             opp->src[i].type = IRQ_TYPE_FSLINT;
1449             opp->src[i].level = true;
1450         }
1451
1452         /* timers and IPIs */
1453         for (i = MAX_SRC; i < MAX_IRQ; i++) {
1454             opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
1455             opp->src[i].level = false;
1456         }
1457
1458         break;
1459
1460     case OPENPIC_MODEL_RAVEN:
1461         opp->nb_irqs = RAVEN_MAX_EXT;
1462         opp->vid = VID_REVISION_1_3;
1463         opp->vir = VIR_GENERIC;
1464         opp->vector_mask = 0xFF;
1465         opp->tfrr_reset = 4160000;
1466         opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK;
1467         opp->idr_reset = 0;
1468         opp->max_irq = RAVEN_MAX_IRQ;
1469         opp->irq_ipi0 = RAVEN_IPI_IRQ;
1470         opp->irq_tim0 = RAVEN_TMR_IRQ;
1471         opp->brr1 = -1;
1472         opp->mpic_mode_mask = GCR_MODE_MIXED;
1473         list = list_le;
1474         /* Don't map MSI region */
1475         list[2].map = false;
1476
1477         /* Only UP supported today */
1478         if (opp->nb_cpus != 1) {
1479             return -EINVAL;
1480         }
1481         break;
1482     }
1483
1484     memory_region_init(&opp->mem, "openpic", 0x40000);
1485
1486     for (i = 0; i < ARRAY_SIZE(list_le); i++) {
1487         if (!list[i].map) {
1488             continue;
1489         }
1490
1491         memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
1492                               list[i].name, list[i].size);
1493
1494         memory_region_add_subregion(&opp->mem, list[i].start_addr,
1495                                     &opp->sub_io_mem[i]);
1496     }
1497
1498     for (i = 0; i < opp->nb_cpus; i++) {
1499         opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB);
1500         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
1501             sysbus_init_irq(dev, &opp->dst[i].irqs[j]);
1502         }
1503     }
1504
1505     register_savevm(&opp->busdev.qdev, "openpic", 0, 2,
1506                     openpic_save, openpic_load, opp);
1507
1508     sysbus_init_mmio(dev, &opp->mem);
1509     qdev_init_gpio_in(&dev->qdev, openpic_set_irq, opp->max_irq);
1510
1511     return 0;
1512 }
1513
1514 static Property openpic_properties[] = {
1515     DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20),
1516     DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1),
1517     DEFINE_PROP_END_OF_LIST(),
1518 };
1519
1520 static void openpic_class_init(ObjectClass *klass, void *data)
1521 {
1522     DeviceClass *dc = DEVICE_CLASS(klass);
1523     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1524
1525     k->init = openpic_init;
1526     dc->props = openpic_properties;
1527     dc->reset = openpic_reset;
1528 }
1529
1530 static const TypeInfo openpic_info = {
1531     .name          = "openpic",
1532     .parent        = TYPE_SYS_BUS_DEVICE,
1533     .instance_size = sizeof(OpenPICState),
1534     .class_init    = openpic_class_init,
1535 };
1536
1537 static void openpic_register_types(void)
1538 {
1539     type_register_static(&openpic_info);
1540 }
1541
1542 type_init(openpic_register_types)