hw/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "sysbus.h"
  19 #include "arm-misc.h"
  20 #include "net.h"
  21 #include "exec-memory.h"
  22 #include "sysemu.h"
  23 #include "boards.h"
  24 #include "flash.h"
  25 #include "blockdev.h"
  26 #include "loader.h"
  27 #include "ssi.h"
  28
  29 #define NUM_SPI_FLASHES 4
  30
  31 #define FLASH_SIZE (64 * 1024 * 1024)
  32 #define FLASH_SECTOR_SIZE (128 * 1024)
  33
  34 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  35
  36 static struct arm_boot_info zynq_binfo = {};
  37
  38 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  39 {
  40     DeviceState *dev;
  41     SysBusDevice *s;
  42
  43     qemu_check_nic_model(nd, "cadence_gem");
  44     dev = qdev_create(NULL, "cadence_gem");
  45     qdev_set_nic_properties(dev, nd);
  46     qdev_init_nofail(dev);
  47     s = sysbus_from_qdev(dev);
  48     sysbus_mmio_map(s, 0, base);
  49     sysbus_connect_irq(s, 0, irq);
  50 }
  51
  52 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq)
  53 {
  54     DeviceState *dev;
  55     SysBusDevice *busdev;
  56     SSIBus *spi;
  57     int i;
  58
  59     dev = qdev_create(NULL, "xilinx,spips");
  60     qdev_init_nofail(dev);
  61     busdev = sysbus_from_qdev(dev);
  62     sysbus_mmio_map(busdev, 0, base_addr);
  63     sysbus_connect_irq(busdev, 0, irq);
  64
  65     spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
  66
  67     for (i = 0; i < NUM_SPI_FLASHES; ++i) {
  68         qemu_irq cs_line;
  69
  70         dev = ssi_create_slave_no_init(spi, "m25p80");
  71         qdev_prop_set_string(dev, "partname", "n25q128");
  72         qdev_init_nofail(dev);
  73
  74         cs_line = qdev_get_gpio_in(dev, 0);
  75         sysbus_connect_irq(busdev, i+1, cs_line);
  76     }
  77
  78 }
  79
  80 static void zynq_init(QEMUMachineInitArgs *args)
  81 {
  82     ram_addr_t ram_size = args->ram_size;
  83     const char *cpu_model = args->cpu_model;
  84     const char *kernel_filename = args->kernel_filename;
  85     const char *kernel_cmdline = args->kernel_cmdline;
  86     const char *initrd_filename = args->initrd_filename;
  87     ARMCPU *cpu;
  88     MemoryRegion *address_space_mem = get_system_memory();
  89     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
  90     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
  91     DeviceState *dev;
  92     SysBusDevice *busdev;
  93     qemu_irq *irqp;
  94     qemu_irq pic[64];
  95     NICInfo *nd;
  96     int n;
  97     qemu_irq cpu_irq;
  98
  99     if (!cpu_model) {
 100         cpu_model = "cortex-a9";
 101     }
 102
 103     cpu = cpu_arm_init(cpu_model);
 104     if (!cpu) {
 105         fprintf(stderr, "Unable to find CPU definition\n");
 106         exit(1);
 107     }
 108     irqp = arm_pic_init_cpu(cpu);
 109     cpu_irq = irqp[ARM_PIC_CPU_IRQ];
 110
 111     /* max 2GB ram */
 112     if (ram_size > 0x80000000) {
 113         ram_size = 0x80000000;
 114     }
 115
 116     /* DDR remapped to address zero.  */
 117     memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
 118     vmstate_register_ram_global(ext_ram);
 119     memory_region_add_subregion(address_space_mem, 0, ext_ram);
 120
 121     /* 256K of on-chip memory */
 122     memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
 123     vmstate_register_ram_global(ocm_ram);
 124     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
 125
 126     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 127
 128     /* AMD */
 129     pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
 130                           dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
 131                           FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
 132                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
 133                               0);
 134
 135     dev = qdev_create(NULL, "xilinx,zynq_slcr");
 136     qdev_init_nofail(dev);
 137     sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000);
 138
 139     dev = qdev_create(NULL, "a9mpcore_priv");
 140     qdev_prop_set_uint32(dev, "num-cpu", 1);
 141     qdev_init_nofail(dev);
 142     busdev = sysbus_from_qdev(dev);
 143     sysbus_mmio_map(busdev, 0, 0xF8F00000);
 144     sysbus_connect_irq(busdev, 0, cpu_irq);
 145
 146     for (n = 0; n < 64; n++) {
 147         pic[n] = qdev_get_gpio_in(dev, n);
 148     }
 149
 150     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]);
 151     zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]);
 152
 153     sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
 154     sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
 155
 156     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 157             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 158     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 159             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 160
 161     for (n = 0; n < nb_nics; n++) {
 162         nd = &nd_table[n];
 163         if (n == 0) {
 164             gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]);
 165         } else if (n == 1) {
 166             gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]);
 167         }
 168     }
 169
 170     zynq_binfo.ram_size = ram_size;
 171     zynq_binfo.kernel_filename = kernel_filename;
 172     zynq_binfo.kernel_cmdline = kernel_cmdline;
 173     zynq_binfo.initrd_filename = initrd_filename;
 174     zynq_binfo.nb_cpus = 1;
 175     zynq_binfo.board_id = 0xd32;
 176     zynq_binfo.loader_start = 0;
 177     arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo);
 178 }
 179
 180 static QEMUMachine zynq_machine = {
 181     .name = "xilinx-zynq-a9",
 182     .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
 183     .init = zynq_init,
 184     .use_scsi = 1,
 185     .max_cpus = 1,
 186     .no_sdcard = 1
 187 };
 188
 189 static void zynq_machine_init(void)
 190 {
 191     qemu_register_machine(&zynq_machine);
 192 }
 193
 194 machine_init(zynq_machine_init);