target-sparc: Revert setting cpu_dst to gen_dest_gpr
[qemu/pbrook.git] / target-xtensa / overlay_tool.h
blobe39505316ba39f5c350b2850bba2f1290d2ce749
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
29 a1, a2, a3, a4, a5, a6) \
30 { .targno = (no), .type = (typ), .group = (grp) },
32 #ifndef XCHAL_HAVE_DIV32
33 #define XCHAL_HAVE_DIV32 0
34 #endif
36 #ifndef XCHAL_UNALIGNED_LOAD_HW
37 #define XCHAL_UNALIGNED_LOAD_HW 0
38 #endif
40 #ifndef XCHAL_HAVE_VECBASE
41 #define XCHAL_HAVE_VECBASE 0
42 #define XCHAL_VECBASE_RESET_VADDR 0
43 #endif
45 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
47 #define XTENSA_OPTIONS ( \
48 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
49 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
50 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
51 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
52 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
53 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
54 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
55 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
56 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
57 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
58 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
59 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
60 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
61 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
62 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
63 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
64 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
65 /* Interrupts and exceptions */ \
66 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
67 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
68 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
69 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
70 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
71 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
72 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
73 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
74 /* Local memory, TODO */ \
75 XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
76 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
77 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
78 XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
79 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
80 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
81 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
82 /* Memory protection and translation */ \
83 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
84 XTENSA_OPTION_REGION_PROTECTION) | \
85 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
86 XTENSA_OPTION_REGION_TRANSLATION) | \
87 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
88 /* Other, TODO */ \
89 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
90 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG))
92 #ifndef XCHAL_WINDOW_OF4_VECOFS
93 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000
94 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040
95 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080
96 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
97 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100
98 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140
99 #endif
101 #define EXCEPTION_VECTORS { \
102 [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
103 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
104 XCHAL_WINDOW_VECTORS_VADDR, \
105 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
106 XCHAL_WINDOW_VECTORS_VADDR, \
107 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
108 XCHAL_WINDOW_VECTORS_VADDR, \
109 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
110 XCHAL_WINDOW_VECTORS_VADDR, \
111 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
112 XCHAL_WINDOW_VECTORS_VADDR, \
113 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
114 XCHAL_WINDOW_VECTORS_VADDR, \
115 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
116 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
117 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
118 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
121 #define INTERRUPT_VECTORS { \
122 0, \
123 0, \
124 XCHAL_INTLEVEL2_VECTOR_VADDR, \
125 XCHAL_INTLEVEL3_VECTOR_VADDR, \
126 XCHAL_INTLEVEL4_VECTOR_VADDR, \
127 XCHAL_INTLEVEL5_VECTOR_VADDR, \
128 XCHAL_INTLEVEL6_VECTOR_VADDR, \
129 XCHAL_INTLEVEL7_VECTOR_VADDR, \
132 #define LEVEL_MASKS { \
133 [1] = XCHAL_INTLEVEL1_MASK, \
134 [2] = XCHAL_INTLEVEL2_MASK, \
135 [3] = XCHAL_INTLEVEL3_MASK, \
136 [4] = XCHAL_INTLEVEL4_MASK, \
137 [5] = XCHAL_INTLEVEL5_MASK, \
138 [6] = XCHAL_INTLEVEL6_MASK, \
139 [7] = XCHAL_INTLEVEL7_MASK, \
142 #define INTTYPE_MASKS { \
143 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
144 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
145 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
148 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
149 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
150 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
151 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
152 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
153 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
154 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
155 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
158 #define INTERRUPT(i) { \
159 .level = XCHAL_INT ## i ## _LEVEL, \
160 .inttype = XCHAL_INT ## i ## _TYPE, \
163 #define INTERRUPTS { \
164 [0] = INTERRUPT(0), \
165 [1] = INTERRUPT(1), \
166 [2] = INTERRUPT(2), \
167 [3] = INTERRUPT(3), \
168 [4] = INTERRUPT(4), \
169 [5] = INTERRUPT(5), \
170 [6] = INTERRUPT(6), \
171 [7] = INTERRUPT(7), \
172 [8] = INTERRUPT(8), \
173 [9] = INTERRUPT(9), \
174 [10] = INTERRUPT(10), \
175 [11] = INTERRUPT(11), \
176 [12] = INTERRUPT(12), \
177 [13] = INTERRUPT(13), \
178 [14] = INTERRUPT(14), \
179 [15] = INTERRUPT(15), \
180 [16] = INTERRUPT(16), \
181 [17] = INTERRUPT(17), \
182 [18] = INTERRUPT(18), \
183 [19] = INTERRUPT(19), \
184 [20] = INTERRUPT(20), \
185 [21] = INTERRUPT(21), \
186 [22] = INTERRUPT(22), \
187 [23] = INTERRUPT(23), \
188 [24] = INTERRUPT(24), \
189 [25] = INTERRUPT(25), \
190 [26] = INTERRUPT(26), \
191 [27] = INTERRUPT(27), \
192 [28] = INTERRUPT(28), \
193 [29] = INTERRUPT(29), \
194 [30] = INTERRUPT(30), \
195 [31] = INTERRUPT(31), \
198 #define TIMERINTS { \
199 [0] = XCHAL_TIMER0_INTERRUPT, \
200 [1] = XCHAL_TIMER1_INTERRUPT, \
201 [2] = XCHAL_TIMER2_INTERRUPT, \
204 #define EXTINTS { \
205 [0] = XCHAL_EXTINT0_NUM, \
206 [1] = XCHAL_EXTINT1_NUM, \
207 [2] = XCHAL_EXTINT2_NUM, \
208 [3] = XCHAL_EXTINT3_NUM, \
209 [4] = XCHAL_EXTINT4_NUM, \
210 [5] = XCHAL_EXTINT5_NUM, \
211 [6] = XCHAL_EXTINT6_NUM, \
212 [7] = XCHAL_EXTINT7_NUM, \
213 [8] = XCHAL_EXTINT8_NUM, \
214 [9] = XCHAL_EXTINT9_NUM, \
215 [10] = XCHAL_EXTINT10_NUM, \
216 [11] = XCHAL_EXTINT11_NUM, \
217 [12] = XCHAL_EXTINT12_NUM, \
218 [13] = XCHAL_EXTINT13_NUM, \
219 [14] = XCHAL_EXTINT14_NUM, \
220 [15] = XCHAL_EXTINT15_NUM, \
221 [16] = XCHAL_EXTINT16_NUM, \
222 [17] = XCHAL_EXTINT17_NUM, \
223 [18] = XCHAL_EXTINT18_NUM, \
224 [19] = XCHAL_EXTINT19_NUM, \
225 [20] = XCHAL_EXTINT20_NUM, \
226 [21] = XCHAL_EXTINT21_NUM, \
227 [22] = XCHAL_EXTINT22_NUM, \
228 [23] = XCHAL_EXTINT23_NUM, \
229 [24] = XCHAL_EXTINT24_NUM, \
230 [25] = XCHAL_EXTINT25_NUM, \
231 [26] = XCHAL_EXTINT26_NUM, \
232 [27] = XCHAL_EXTINT27_NUM, \
233 [28] = XCHAL_EXTINT28_NUM, \
234 [29] = XCHAL_EXTINT29_NUM, \
235 [30] = XCHAL_EXTINT30_NUM, \
236 [31] = XCHAL_EXTINT31_NUM, \
239 #define EXCEPTIONS_SECTION \
240 .excm_level = XCHAL_EXCM_LEVEL, \
241 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
242 .exception_vector = EXCEPTION_VECTORS
244 #define INTERRUPTS_SECTION \
245 .ninterrupt = XCHAL_NUM_INTERRUPTS, \
246 .nlevel = XCHAL_NUM_INTLEVELS, \
247 .interrupt_vector = INTERRUPT_VECTORS, \
248 .level_mask = LEVEL_MASKS, \
249 .inttype_mask = INTTYPE_MASKS, \
250 .interrupt = INTERRUPTS, \
251 .nccompare = XCHAL_NUM_TIMERS, \
252 .timerint = TIMERINTS, \
253 .nextint = XCHAL_NUM_EXTINTERRUPTS, \
254 .extint = EXTINTS
256 #if XCHAL_HAVE_PTP_MMU
258 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
259 .nways = ways, \
260 .way_size = { \
261 (refill_way_size), (refill_way_size), \
262 (refill_way_size), (refill_way_size), \
263 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
264 }, \
265 .varway56 = (way56), \
266 .nrefillentries = (refill_way_size) * 4, \
269 #define ITLB(varway56) \
270 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
272 #define DTLB(varway56) \
273 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
275 #define TLB_SECTION \
276 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
277 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
279 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
281 #define TLB_TEMPLATE { \
282 .nways = 1, \
283 .way_size = { \
284 8, \
288 #define TLB_SECTION \
289 .itlb = TLB_TEMPLATE, \
290 .dtlb = TLB_TEMPLATE
292 #endif
294 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
295 #define REGISTER_CORE(core) \
296 static void __attribute__((constructor)) register_core(void) \
298 static XtensaConfigList node = { \
299 .config = &core, \
300 }; \
301 xtensa_register_core(&node); \
303 #else
304 #define REGISTER_CORE(core)
305 #endif
307 #define DEBUG_SECTION \
308 .debug_level = XCHAL_DEBUGLEVEL, \
309 .nibreak = XCHAL_NUM_IBREAK, \
310 .ndbreak = XCHAL_NUM_DBREAK
312 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
313 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
314 #endif
315 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
316 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
317 #endif
318 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
319 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
320 #endif
321 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
322 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
323 #endif
324 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
325 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
326 #endif
327 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
328 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
329 #endif
332 #if XCHAL_NUM_INTERRUPTS <= 0
333 #define XCHAL_INT0_LEVEL 0
334 #define XCHAL_INT0_TYPE 0
335 #endif
336 #if XCHAL_NUM_INTERRUPTS <= 1
337 #define XCHAL_INT1_LEVEL 0
338 #define XCHAL_INT1_TYPE 0
339 #endif
340 #if XCHAL_NUM_INTERRUPTS <= 2
341 #define XCHAL_INT2_LEVEL 0
342 #define XCHAL_INT2_TYPE 0
343 #endif
344 #if XCHAL_NUM_INTERRUPTS <= 3
345 #define XCHAL_INT3_LEVEL 0
346 #define XCHAL_INT3_TYPE 0
347 #endif
348 #if XCHAL_NUM_INTERRUPTS <= 4
349 #define XCHAL_INT4_LEVEL 0
350 #define XCHAL_INT4_TYPE 0
351 #endif
352 #if XCHAL_NUM_INTERRUPTS <= 5
353 #define XCHAL_INT5_LEVEL 0
354 #define XCHAL_INT5_TYPE 0
355 #endif
356 #if XCHAL_NUM_INTERRUPTS <= 6
357 #define XCHAL_INT6_LEVEL 0
358 #define XCHAL_INT6_TYPE 0
359 #endif
360 #if XCHAL_NUM_INTERRUPTS <= 7
361 #define XCHAL_INT7_LEVEL 0
362 #define XCHAL_INT7_TYPE 0
363 #endif
364 #if XCHAL_NUM_INTERRUPTS <= 8
365 #define XCHAL_INT8_LEVEL 0
366 #define XCHAL_INT8_TYPE 0
367 #endif
368 #if XCHAL_NUM_INTERRUPTS <= 9
369 #define XCHAL_INT9_LEVEL 0
370 #define XCHAL_INT9_TYPE 0
371 #endif
372 #if XCHAL_NUM_INTERRUPTS <= 10
373 #define XCHAL_INT10_LEVEL 0
374 #define XCHAL_INT10_TYPE 0
375 #endif
376 #if XCHAL_NUM_INTERRUPTS <= 11
377 #define XCHAL_INT11_LEVEL 0
378 #define XCHAL_INT11_TYPE 0
379 #endif
380 #if XCHAL_NUM_INTERRUPTS <= 12
381 #define XCHAL_INT12_LEVEL 0
382 #define XCHAL_INT12_TYPE 0
383 #endif
384 #if XCHAL_NUM_INTERRUPTS <= 13
385 #define XCHAL_INT13_LEVEL 0
386 #define XCHAL_INT13_TYPE 0
387 #endif
388 #if XCHAL_NUM_INTERRUPTS <= 14
389 #define XCHAL_INT14_LEVEL 0
390 #define XCHAL_INT14_TYPE 0
391 #endif
392 #if XCHAL_NUM_INTERRUPTS <= 15
393 #define XCHAL_INT15_LEVEL 0
394 #define XCHAL_INT15_TYPE 0
395 #endif
396 #if XCHAL_NUM_INTERRUPTS <= 16
397 #define XCHAL_INT16_LEVEL 0
398 #define XCHAL_INT16_TYPE 0
399 #endif
400 #if XCHAL_NUM_INTERRUPTS <= 17
401 #define XCHAL_INT17_LEVEL 0
402 #define XCHAL_INT17_TYPE 0
403 #endif
404 #if XCHAL_NUM_INTERRUPTS <= 18
405 #define XCHAL_INT18_LEVEL 0
406 #define XCHAL_INT18_TYPE 0
407 #endif
408 #if XCHAL_NUM_INTERRUPTS <= 19
409 #define XCHAL_INT19_LEVEL 0
410 #define XCHAL_INT19_TYPE 0
411 #endif
412 #if XCHAL_NUM_INTERRUPTS <= 20
413 #define XCHAL_INT20_LEVEL 0
414 #define XCHAL_INT20_TYPE 0
415 #endif
416 #if XCHAL_NUM_INTERRUPTS <= 21
417 #define XCHAL_INT21_LEVEL 0
418 #define XCHAL_INT21_TYPE 0
419 #endif
420 #if XCHAL_NUM_INTERRUPTS <= 22
421 #define XCHAL_INT22_LEVEL 0
422 #define XCHAL_INT22_TYPE 0
423 #endif
424 #if XCHAL_NUM_INTERRUPTS <= 23
425 #define XCHAL_INT23_LEVEL 0
426 #define XCHAL_INT23_TYPE 0
427 #endif
428 #if XCHAL_NUM_INTERRUPTS <= 24
429 #define XCHAL_INT24_LEVEL 0
430 #define XCHAL_INT24_TYPE 0
431 #endif
432 #if XCHAL_NUM_INTERRUPTS <= 25
433 #define XCHAL_INT25_LEVEL 0
434 #define XCHAL_INT25_TYPE 0
435 #endif
436 #if XCHAL_NUM_INTERRUPTS <= 26
437 #define XCHAL_INT26_LEVEL 0
438 #define XCHAL_INT26_TYPE 0
439 #endif
440 #if XCHAL_NUM_INTERRUPTS <= 27
441 #define XCHAL_INT27_LEVEL 0
442 #define XCHAL_INT27_TYPE 0
443 #endif
444 #if XCHAL_NUM_INTERRUPTS <= 28
445 #define XCHAL_INT28_LEVEL 0
446 #define XCHAL_INT28_TYPE 0
447 #endif
448 #if XCHAL_NUM_INTERRUPTS <= 29
449 #define XCHAL_INT29_LEVEL 0
450 #define XCHAL_INT29_TYPE 0
451 #endif
452 #if XCHAL_NUM_INTERRUPTS <= 30
453 #define XCHAL_INT30_LEVEL 0
454 #define XCHAL_INT30_TYPE 0
455 #endif
456 #if XCHAL_NUM_INTERRUPTS <= 31
457 #define XCHAL_INT31_LEVEL 0
458 #define XCHAL_INT31_TYPE 0
459 #endif
462 #if XCHAL_NUM_EXTINTERRUPTS <= 0
463 #define XCHAL_EXTINT0_NUM 0
464 #endif
465 #if XCHAL_NUM_EXTINTERRUPTS <= 1
466 #define XCHAL_EXTINT1_NUM 0
467 #endif
468 #if XCHAL_NUM_EXTINTERRUPTS <= 2
469 #define XCHAL_EXTINT2_NUM 0
470 #endif
471 #if XCHAL_NUM_EXTINTERRUPTS <= 3
472 #define XCHAL_EXTINT3_NUM 0
473 #endif
474 #if XCHAL_NUM_EXTINTERRUPTS <= 4
475 #define XCHAL_EXTINT4_NUM 0
476 #endif
477 #if XCHAL_NUM_EXTINTERRUPTS <= 5
478 #define XCHAL_EXTINT5_NUM 0
479 #endif
480 #if XCHAL_NUM_EXTINTERRUPTS <= 6
481 #define XCHAL_EXTINT6_NUM 0
482 #endif
483 #if XCHAL_NUM_EXTINTERRUPTS <= 7
484 #define XCHAL_EXTINT7_NUM 0
485 #endif
486 #if XCHAL_NUM_EXTINTERRUPTS <= 8
487 #define XCHAL_EXTINT8_NUM 0
488 #endif
489 #if XCHAL_NUM_EXTINTERRUPTS <= 9
490 #define XCHAL_EXTINT9_NUM 0
491 #endif
492 #if XCHAL_NUM_EXTINTERRUPTS <= 10
493 #define XCHAL_EXTINT10_NUM 0
494 #endif
495 #if XCHAL_NUM_EXTINTERRUPTS <= 11
496 #define XCHAL_EXTINT11_NUM 0
497 #endif
498 #if XCHAL_NUM_EXTINTERRUPTS <= 12
499 #define XCHAL_EXTINT12_NUM 0
500 #endif
501 #if XCHAL_NUM_EXTINTERRUPTS <= 13
502 #define XCHAL_EXTINT13_NUM 0
503 #endif
504 #if XCHAL_NUM_EXTINTERRUPTS <= 14
505 #define XCHAL_EXTINT14_NUM 0
506 #endif
507 #if XCHAL_NUM_EXTINTERRUPTS <= 15
508 #define XCHAL_EXTINT15_NUM 0
509 #endif
510 #if XCHAL_NUM_EXTINTERRUPTS <= 16
511 #define XCHAL_EXTINT16_NUM 0
512 #endif
513 #if XCHAL_NUM_EXTINTERRUPTS <= 17
514 #define XCHAL_EXTINT17_NUM 0
515 #endif
516 #if XCHAL_NUM_EXTINTERRUPTS <= 18
517 #define XCHAL_EXTINT18_NUM 0
518 #endif
519 #if XCHAL_NUM_EXTINTERRUPTS <= 19
520 #define XCHAL_EXTINT19_NUM 0
521 #endif
522 #if XCHAL_NUM_EXTINTERRUPTS <= 20
523 #define XCHAL_EXTINT20_NUM 0
524 #endif
525 #if XCHAL_NUM_EXTINTERRUPTS <= 21
526 #define XCHAL_EXTINT21_NUM 0
527 #endif
528 #if XCHAL_NUM_EXTINTERRUPTS <= 22
529 #define XCHAL_EXTINT22_NUM 0
530 #endif
531 #if XCHAL_NUM_EXTINTERRUPTS <= 23
532 #define XCHAL_EXTINT23_NUM 0
533 #endif
534 #if XCHAL_NUM_EXTINTERRUPTS <= 24
535 #define XCHAL_EXTINT24_NUM 0
536 #endif
537 #if XCHAL_NUM_EXTINTERRUPTS <= 25
538 #define XCHAL_EXTINT25_NUM 0
539 #endif
540 #if XCHAL_NUM_EXTINTERRUPTS <= 26
541 #define XCHAL_EXTINT26_NUM 0
542 #endif
543 #if XCHAL_NUM_EXTINTERRUPTS <= 27
544 #define XCHAL_EXTINT27_NUM 0
545 #endif
546 #if XCHAL_NUM_EXTINTERRUPTS <= 28
547 #define XCHAL_EXTINT28_NUM 0
548 #endif
549 #if XCHAL_NUM_EXTINTERRUPTS <= 29
550 #define XCHAL_EXTINT29_NUM 0
551 #endif
552 #if XCHAL_NUM_EXTINTERRUPTS <= 30
553 #define XCHAL_EXTINT30_NUM 0
554 #endif
555 #if XCHAL_NUM_EXTINTERRUPTS <= 31
556 #define XCHAL_EXTINT31_NUM 0
557 #endif
560 #define XTHAL_TIMER_UNCONFIGURED 0