target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/pc.h"
   4 #include "hw/isa.h"
   5
   6 #include "cpu.h"
   7 #include "sysemu/kvm.h"
   8
   9 static const VMStateDescription vmstate_segment = {
  10     .name = "segment",
  11     .version_id = 1,
  12     .minimum_version_id = 1,
  13     .minimum_version_id_old = 1,
  14     .fields      = (VMStateField []) {
  15         VMSTATE_UINT32(selector, SegmentCache),
  16         VMSTATE_UINTTL(base, SegmentCache),
  17         VMSTATE_UINT32(limit, SegmentCache),
  18         VMSTATE_UINT32(flags, SegmentCache),
  19         VMSTATE_END_OF_LIST()
  20     }
  21 };
  22
  23 #define VMSTATE_SEGMENT(_field, _state) {                            \
  24     .name       = (stringify(_field)),                               \
  25     .size       = sizeof(SegmentCache),                              \
  26     .vmsd       = &vmstate_segment,                                  \
  27     .flags      = VMS_STRUCT,                                        \
  28     .offset     = offsetof(_state, _field)                           \
  29             + type_check(SegmentCache,typeof_field(_state, _field))  \
  30 }
  31
  32 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  33     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  34
  35 static const VMStateDescription vmstate_xmm_reg = {
  36     .name = "xmm_reg",
  37     .version_id = 1,
  38     .minimum_version_id = 1,
  39     .minimum_version_id_old = 1,
  40     .fields      = (VMStateField []) {
  41         VMSTATE_UINT64(XMM_Q(0), XMMReg),
  42         VMSTATE_UINT64(XMM_Q(1), XMMReg),
  43         VMSTATE_END_OF_LIST()
  44     }
  45 };
  46
  47 #define VMSTATE_XMM_REGS(_field, _state, _n)                         \
  48     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
  49
  50 /* YMMH format is the same as XMM */
  51 static const VMStateDescription vmstate_ymmh_reg = {
  52     .name = "ymmh_reg",
  53     .version_id = 1,
  54     .minimum_version_id = 1,
  55     .minimum_version_id_old = 1,
  56     .fields      = (VMStateField []) {
  57         VMSTATE_UINT64(XMM_Q(0), XMMReg),
  58         VMSTATE_UINT64(XMM_Q(1), XMMReg),
  59         VMSTATE_END_OF_LIST()
  60     }
  61 };
  62
  63 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)                         \
  64     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
  65
  66 static const VMStateDescription vmstate_mtrr_var = {
  67     .name = "mtrr_var",
  68     .version_id = 1,
  69     .minimum_version_id = 1,
  70     .minimum_version_id_old = 1,
  71     .fields      = (VMStateField []) {
  72         VMSTATE_UINT64(base, MTRRVar),
  73         VMSTATE_UINT64(mask, MTRRVar),
  74         VMSTATE_END_OF_LIST()
  75     }
  76 };
  77
  78 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
  79     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
  80
  81 static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
  82 {
  83     fprintf(stderr, "call put_fpreg() with invalid arguments\n");
  84     exit(0);
  85 }
  86
  87 /* XXX: add that in a FPU generic layer */
  88 union x86_longdouble {
  89     uint64_t mant;
  90     uint16_t exp;
  91 };
  92
  93 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
  94 #define EXPBIAS1 1023
  95 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
  96 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
  97
  98 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
  99 {
 100     int e;
 101     /* mantissa */
 102     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 103     /* exponent + sign */
 104     e = EXPD1(temp) - EXPBIAS1 + 16383;
 105     e |= SIGND1(temp) >> 16;
 106     p->exp = e;
 107 }
 108
 109 static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
 110 {
 111     FPReg *fp_reg = opaque;
 112     uint64_t mant;
 113     uint16_t exp;
 114
 115     qemu_get_be64s(f, &mant);
 116     qemu_get_be16s(f, &exp);
 117     fp_reg->d = cpu_set_fp80(mant, exp);
 118     return 0;
 119 }
 120
 121 static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
 122 {
 123     FPReg *fp_reg = opaque;
 124     uint64_t mant;
 125     uint16_t exp;
 126     /* we save the real CPU data (in case of MMX usage only 'mant'
 127        contains the MMX register */
 128     cpu_get_fp80(&mant, &exp, fp_reg->d);
 129     qemu_put_be64s(f, &mant);
 130     qemu_put_be16s(f, &exp);
 131 }
 132
 133 static const VMStateInfo vmstate_fpreg = {
 134     .name = "fpreg",
 135     .get  = get_fpreg,
 136     .put  = put_fpreg,
 137 };
 138
 139 static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
 140 {
 141     union x86_longdouble *p = opaque;
 142     uint64_t mant;
 143
 144     qemu_get_be64s(f, &mant);
 145     p->mant = mant;
 146     p->exp = 0xffff;
 147     return 0;
 148 }
 149
 150 static const VMStateInfo vmstate_fpreg_1_mmx = {
 151     .name = "fpreg_1_mmx",
 152     .get  = get_fpreg_1_mmx,
 153     .put  = put_fpreg_error,
 154 };
 155
 156 static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
 157 {
 158     union x86_longdouble *p = opaque;
 159     uint64_t mant;
 160
 161     qemu_get_be64s(f, &mant);
 162     fp64_to_fp80(p, mant);
 163     return 0;
 164 }
 165
 166 static const VMStateInfo vmstate_fpreg_1_no_mmx = {
 167     .name = "fpreg_1_no_mmx",
 168     .get  = get_fpreg_1_no_mmx,
 169     .put  = put_fpreg_error,
 170 };
 171
 172 static bool fpregs_is_0(void *opaque, int version_id)
 173 {
 174     CPUX86State *env = opaque;
 175
 176     return (env->fpregs_format_vmstate == 0);
 177 }
 178
 179 static bool fpregs_is_1_mmx(void *opaque, int version_id)
 180 {
 181     CPUX86State *env = opaque;
 182     int guess_mmx;
 183
 184     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 185                  (env->fpus_vmstate & 0x3800) == 0);
 186     return (guess_mmx && (env->fpregs_format_vmstate == 1));
 187 }
 188
 189 static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
 190 {
 191     CPUX86State *env = opaque;
 192     int guess_mmx;
 193
 194     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 195                  (env->fpus_vmstate & 0x3800) == 0);
 196     return (!guess_mmx && (env->fpregs_format_vmstate == 1));
 197 }
 198
 199 #define VMSTATE_FP_REGS(_field, _state, _n)                               \
 200     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
 201     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
 202     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
 203
 204 static bool version_is_5(void *opaque, int version_id)
 205 {
 206     return version_id == 5;
 207 }
 208
 209 #ifdef TARGET_X86_64
 210 static bool less_than_7(void *opaque, int version_id)
 211 {
 212     return version_id < 7;
 213 }
 214
 215 static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 216 {
 217     uint64_t *v = pv;
 218     *v = qemu_get_be32(f);
 219     return 0;
 220 }
 221
 222 static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 223 {
 224     uint64_t *v = pv;
 225     qemu_put_be32(f, *v);
 226 }
 227
 228 static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
 229     .name = "uint64_as_uint32",
 230     .get  = get_uint64_as_uint32,
 231     .put  = put_uint64_as_uint32,
 232 };
 233
 234 #define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
 235     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
 236 #endif
 237
 238 static void cpu_pre_save(void *opaque)
 239 {
 240     CPUX86State *env = opaque;
 241     int i;
 242
 243     /* FPU */
 244     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 245     env->fptag_vmstate = 0;
 246     for(i = 0; i < 8; i++) {
 247         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 248     }
 249
 250     env->fpregs_format_vmstate = 0;
 251 }
 252
 253 static int cpu_post_load(void *opaque, int version_id)
 254 {
 255     CPUX86State *env = opaque;
 256     int i;
 257
 258     /* XXX: restore FPU round state */
 259     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 260     env->fpus = env->fpus_vmstate & ~0x3800;
 261     env->fptag_vmstate ^= 0xff;
 262     for(i = 0; i < 8; i++) {
 263         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 264     }
 265
 266     cpu_breakpoint_remove_all(env, BP_CPU);
 267     cpu_watchpoint_remove_all(env, BP_CPU);
 268     for (i = 0; i < DR7_MAX_BP; i++) {
 269         hw_breakpoint_insert(env, i);
 270     }
 271     tlb_flush(env, 1);
 272
 273     return 0;
 274 }
 275
 276 static bool async_pf_msr_needed(void *opaque)
 277 {
 278     CPUX86State *cpu = opaque;
 279
 280     return cpu->async_pf_en_msr != 0;
 281 }
 282
 283 static bool pv_eoi_msr_needed(void *opaque)
 284 {
 285     CPUX86State *cpu = opaque;
 286
 287     return cpu->pv_eoi_en_msr != 0;
 288 }
 289
 290 static const VMStateDescription vmstate_async_pf_msr = {
 291     .name = "cpu/async_pf_msr",
 292     .version_id = 1,
 293     .minimum_version_id = 1,
 294     .minimum_version_id_old = 1,
 295     .fields      = (VMStateField []) {
 296         VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
 297         VMSTATE_END_OF_LIST()
 298     }
 299 };
 300
 301 static const VMStateDescription vmstate_pv_eoi_msr = {
 302     .name = "cpu/async_pv_eoi_msr",
 303     .version_id = 1,
 304     .minimum_version_id = 1,
 305     .minimum_version_id_old = 1,
 306     .fields      = (VMStateField []) {
 307         VMSTATE_UINT64(pv_eoi_en_msr, CPUX86State),
 308         VMSTATE_END_OF_LIST()
 309     }
 310 };
 311
 312 static bool fpop_ip_dp_needed(void *opaque)
 313 {
 314     CPUX86State *env = opaque;
 315
 316     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 317 }
 318
 319 static const VMStateDescription vmstate_fpop_ip_dp = {
 320     .name = "cpu/fpop_ip_dp",
 321     .version_id = 1,
 322     .minimum_version_id = 1,
 323     .minimum_version_id_old = 1,
 324     .fields      = (VMStateField []) {
 325         VMSTATE_UINT16(fpop, CPUX86State),
 326         VMSTATE_UINT64(fpip, CPUX86State),
 327         VMSTATE_UINT64(fpdp, CPUX86State),
 328         VMSTATE_END_OF_LIST()
 329     }
 330 };
 331
 332 static bool tsc_adjust_needed(void *opaque)
 333 {
 334     CPUX86State *env = opaque;
 335
 336     return env->tsc_adjust != 0;
 337 }
 338
 339 static const VMStateDescription vmstate_msr_tsc_adjust = {
 340     .name = "cpu/msr_tsc_adjust",
 341     .version_id = 1,
 342     .minimum_version_id = 1,
 343     .minimum_version_id_old = 1,
 344     .fields      = (VMStateField[]) {
 345         VMSTATE_UINT64(tsc_adjust, CPUX86State),
 346         VMSTATE_END_OF_LIST()
 347     }
 348 };
 349
 350 static bool tscdeadline_needed(void *opaque)
 351 {
 352     CPUX86State *env = opaque;
 353
 354     return env->tsc_deadline != 0;
 355 }
 356
 357 static const VMStateDescription vmstate_msr_tscdeadline = {
 358     .name = "cpu/msr_tscdeadline",
 359     .version_id = 1,
 360     .minimum_version_id = 1,
 361     .minimum_version_id_old = 1,
 362     .fields      = (VMStateField []) {
 363         VMSTATE_UINT64(tsc_deadline, CPUX86State),
 364         VMSTATE_END_OF_LIST()
 365     }
 366 };
 367
 368 static bool misc_enable_needed(void *opaque)
 369 {
 370     CPUX86State *env = opaque;
 371
 372     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 373 }
 374
 375 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 376     .name = "cpu/msr_ia32_misc_enable",
 377     .version_id = 1,
 378     .minimum_version_id = 1,
 379     .minimum_version_id_old = 1,
 380     .fields      = (VMStateField []) {
 381         VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State),
 382         VMSTATE_END_OF_LIST()
 383     }
 384 };
 385
 386 static const VMStateDescription vmstate_cpu = {
 387     .name = "cpu",
 388     .version_id = CPU_SAVE_VERSION,
 389     .minimum_version_id = 3,
 390     .minimum_version_id_old = 3,
 391     .pre_save = cpu_pre_save,
 392     .post_load = cpu_post_load,
 393     .fields      = (VMStateField []) {
 394         VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
 395         VMSTATE_UINTTL(eip, CPUX86State),
 396         VMSTATE_UINTTL(eflags, CPUX86State),
 397         VMSTATE_UINT32(hflags, CPUX86State),
 398         /* FPU */
 399         VMSTATE_UINT16(fpuc, CPUX86State),
 400         VMSTATE_UINT16(fpus_vmstate, CPUX86State),
 401         VMSTATE_UINT16(fptag_vmstate, CPUX86State),
 402         VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State),
 403         VMSTATE_FP_REGS(fpregs, CPUX86State, 8),
 404
 405         VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6),
 406         VMSTATE_SEGMENT(ldt, CPUX86State),
 407         VMSTATE_SEGMENT(tr, CPUX86State),
 408         VMSTATE_SEGMENT(gdt, CPUX86State),
 409         VMSTATE_SEGMENT(idt, CPUX86State),
 410
 411         VMSTATE_UINT32(sysenter_cs, CPUX86State),
 412 #ifdef TARGET_X86_64
 413         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
 414         VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7),
 415         VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7),
 416         VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7),
 417         VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7),
 418 #else
 419         VMSTATE_UINTTL(sysenter_esp, CPUX86State),
 420         VMSTATE_UINTTL(sysenter_eip, CPUX86State),
 421 #endif
 422
 423         VMSTATE_UINTTL(cr[0], CPUX86State),
 424         VMSTATE_UINTTL(cr[2], CPUX86State),
 425         VMSTATE_UINTTL(cr[3], CPUX86State),
 426         VMSTATE_UINTTL(cr[4], CPUX86State),
 427         VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8),
 428         /* MMU */
 429         VMSTATE_INT32(a20_mask, CPUX86State),
 430         /* XMM */
 431         VMSTATE_UINT32(mxcsr, CPUX86State),
 432         VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS),
 433
 434 #ifdef TARGET_X86_64
 435         VMSTATE_UINT64(efer, CPUX86State),
 436         VMSTATE_UINT64(star, CPUX86State),
 437         VMSTATE_UINT64(lstar, CPUX86State),
 438         VMSTATE_UINT64(cstar, CPUX86State),
 439         VMSTATE_UINT64(fmask, CPUX86State),
 440         VMSTATE_UINT64(kernelgsbase, CPUX86State),
 441 #endif
 442         VMSTATE_UINT32_V(smbase, CPUX86State, 4),
 443
 444         VMSTATE_UINT64_V(pat, CPUX86State, 5),
 445         VMSTATE_UINT32_V(hflags2, CPUX86State, 5),
 446
 447         VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5),
 448         VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5),
 449         VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5),
 450         VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5),
 451         VMSTATE_UINT64_V(intercept, CPUX86State, 5),
 452         VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5),
 453         VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5),
 454         VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5),
 455         VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5),
 456         VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5),
 457         VMSTATE_UINT8_V(v_tpr, CPUX86State, 5),
 458         /* MTRRs */
 459         VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8),
 460         VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8),
 461         VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8),
 462         /* KVM-related states */
 463         VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9),
 464         VMSTATE_UINT32_V(mp_state, CPUX86State, 9),
 465         VMSTATE_UINT64_V(tsc, CPUX86State, 9),
 466         VMSTATE_INT32_V(exception_injected, CPUX86State, 11),
 467         VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11),
 468         VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11),
 469         VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11),
 470         VMSTATE_UINT8_V(has_error_code, CPUX86State, 11),
 471         VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11),
 472         /* MCE */
 473         VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10),
 474         VMSTATE_UINT64_V(mcg_status, CPUX86State, 10),
 475         VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10),
 476         VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4, 10),
 477         /* rdtscp */
 478         VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11),
 479         /* KVM pvclock msr */
 480         VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11),
 481         VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11),
 482         /* XSAVE related fields */
 483         VMSTATE_UINT64_V(xcr0, CPUX86State, 12),
 484         VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12),
 485         VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12),
 486         VMSTATE_END_OF_LIST()
 487         /* The above list is not sorted /wrt version numbers, watch out! */
 488     },
 489     .subsections = (VMStateSubsection []) {
 490         {
 491             .vmsd = &vmstate_async_pf_msr,
 492             .needed = async_pf_msr_needed,
 493         } , {
 494             .vmsd = &vmstate_pv_eoi_msr,
 495             .needed = pv_eoi_msr_needed,
 496         } , {
 497             .vmsd = &vmstate_fpop_ip_dp,
 498             .needed = fpop_ip_dp_needed,
 499         }, {
 500             .vmsd = &vmstate_msr_tsc_adjust,
 501             .needed = tsc_adjust_needed,
 502         }, {
 503             .vmsd = &vmstate_msr_tscdeadline,
 504             .needed = tscdeadline_needed,
 505         }, {
 506             .vmsd = &vmstate_msr_ia32_misc_enable,
 507             .needed = misc_enable_needed,
 508         } , {
 509             /* empty */
 510         }
 511     }
 512 };
 513
 514 void cpu_save(QEMUFile *f, void *opaque)
 515 {
 516     vmstate_save_state(f, &vmstate_cpu, opaque);
 517 }
 518
 519 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 520 {
 521     return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
 522 }