target-xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef CPU_XTENSA_H
  29 #define CPU_XTENSA_H
  30
  31 #define TARGET_LONG_BITS 32
  32 #define ELF_MACHINE EM_XTENSA
  33
  34 #define CPUArchState struct CPUXtensaState
  35
  36 #include "config.h"
  37 #include "qemu-common.h"
  38 #include "cpu-defs.h"
  39 #include "fpu/softfloat.h"
  40
  41 #define TARGET_HAS_ICE 1
  42
  43 #define NB_MMU_MODES 4
  44
  45 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  46 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  47 #define TARGET_PAGE_BITS 12
  48
  49 enum {
  50     /* Additional instructions */
  51     XTENSA_OPTION_CODE_DENSITY,
  52     XTENSA_OPTION_LOOP,
  53     XTENSA_OPTION_EXTENDED_L32R,
  54     XTENSA_OPTION_16_BIT_IMUL,
  55     XTENSA_OPTION_32_BIT_IMUL,
  56     XTENSA_OPTION_32_BIT_IMUL_HIGH,
  57     XTENSA_OPTION_32_BIT_IDIV,
  58     XTENSA_OPTION_MAC16,
  59     XTENSA_OPTION_MISC_OP_NSA,
  60     XTENSA_OPTION_MISC_OP_MINMAX,
  61     XTENSA_OPTION_MISC_OP_SEXT,
  62     XTENSA_OPTION_MISC_OP_CLAMPS,
  63     XTENSA_OPTION_COPROCESSOR,
  64     XTENSA_OPTION_BOOLEAN,
  65     XTENSA_OPTION_FP_COPROCESSOR,
  66     XTENSA_OPTION_MP_SYNCHRO,
  67     XTENSA_OPTION_CONDITIONAL_STORE,
  68
  69     /* Interrupts and exceptions */
  70     XTENSA_OPTION_EXCEPTION,
  71     XTENSA_OPTION_RELOCATABLE_VECTOR,
  72     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  73     XTENSA_OPTION_INTERRUPT,
  74     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  75     XTENSA_OPTION_TIMER_INTERRUPT,
  76
  77     /* Local memory */
  78     XTENSA_OPTION_ICACHE,
  79     XTENSA_OPTION_ICACHE_TEST,
  80     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  81     XTENSA_OPTION_DCACHE,
  82     XTENSA_OPTION_DCACHE_TEST,
  83     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  84     XTENSA_OPTION_IRAM,
  85     XTENSA_OPTION_IROM,
  86     XTENSA_OPTION_DRAM,
  87     XTENSA_OPTION_DROM,
  88     XTENSA_OPTION_XLMI,
  89     XTENSA_OPTION_HW_ALIGNMENT,
  90     XTENSA_OPTION_MEMORY_ECC_PARITY,
  91
  92     /* Memory protection and translation */
  93     XTENSA_OPTION_REGION_PROTECTION,
  94     XTENSA_OPTION_REGION_TRANSLATION,
  95     XTENSA_OPTION_MMU,
  96
  97     /* Other */
  98     XTENSA_OPTION_WINDOWED_REGISTER,
  99     XTENSA_OPTION_PROCESSOR_INTERFACE,
 100     XTENSA_OPTION_MISC_SR,
 101     XTENSA_OPTION_THREAD_POINTER,
 102     XTENSA_OPTION_PROCESSOR_ID,
 103     XTENSA_OPTION_DEBUG,
 104     XTENSA_OPTION_TRACE_PORT,
 105 };
 106
 107 enum {
 108     THREADPTR = 231,
 109     FCR = 232,
 110     FSR = 233,
 111 };
 112
 113 enum {
 114     LBEG = 0,
 115     LEND = 1,
 116     LCOUNT = 2,
 117     SAR = 3,
 118     BR = 4,
 119     LITBASE = 5,
 120     SCOMPARE1 = 12,
 121     ACCLO = 16,
 122     ACCHI = 17,
 123     MR = 32,
 124     WINDOW_BASE = 72,
 125     WINDOW_START = 73,
 126     PTEVADDR = 83,
 127     RASID = 90,
 128     ITLBCFG = 91,
 129     DTLBCFG = 92,
 130     IBREAKENABLE = 96,
 131     IBREAKA = 128,
 132     DBREAKA = 144,
 133     DBREAKC = 160,
 134     EPC1 = 177,
 135     DEPC = 192,
 136     EPS2 = 194,
 137     EXCSAVE1 = 209,
 138     CPENABLE = 224,
 139     INTSET = 226,
 140     INTCLEAR = 227,
 141     INTENABLE = 228,
 142     PS = 230,
 143     VECBASE = 231,
 144     EXCCAUSE = 232,
 145     DEBUGCAUSE = 233,
 146     CCOUNT = 234,
 147     PRID = 235,
 148     ICOUNT = 236,
 149     ICOUNTLEVEL = 237,
 150     EXCVADDR = 238,
 151     CCOMPARE = 240,
 152 };
 153
 154 #define PS_INTLEVEL 0xf
 155 #define PS_INTLEVEL_SHIFT 0
 156
 157 #define PS_EXCM 0x10
 158 #define PS_UM 0x20
 159
 160 #define PS_RING 0xc0
 161 #define PS_RING_SHIFT 6
 162
 163 #define PS_OWB 0xf00
 164 #define PS_OWB_SHIFT 8
 165
 166 #define PS_CALLINC 0x30000
 167 #define PS_CALLINC_SHIFT 16
 168 #define PS_CALLINC_LEN 2
 169
 170 #define PS_WOE 0x40000
 171
 172 #define DEBUGCAUSE_IC 0x1
 173 #define DEBUGCAUSE_IB 0x2
 174 #define DEBUGCAUSE_DB 0x4
 175 #define DEBUGCAUSE_BI 0x8
 176 #define DEBUGCAUSE_BN 0x10
 177 #define DEBUGCAUSE_DI 0x20
 178 #define DEBUGCAUSE_DBNUM 0xf00
 179 #define DEBUGCAUSE_DBNUM_SHIFT 8
 180
 181 #define DBREAKC_SB 0x80000000
 182 #define DBREAKC_LB 0x40000000
 183 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
 184 #define DBREAKC_MASK 0x3f
 185
 186 #define MAX_NAREG 64
 187 #define MAX_NINTERRUPT 32
 188 #define MAX_NLEVEL 6
 189 #define MAX_NNMI 1
 190 #define MAX_NCCOMPARE 3
 191 #define MAX_TLB_WAY_SIZE 8
 192 #define MAX_NDBREAK 2
 193
 194 #define REGION_PAGE_MASK 0xe0000000
 195
 196 enum {
 197     /* Static vectors */
 198     EXC_RESET,
 199     EXC_MEMORY_ERROR,
 200
 201     /* Dynamic vectors */
 202     EXC_WINDOW_OVERFLOW4,
 203     EXC_WINDOW_UNDERFLOW4,
 204     EXC_WINDOW_OVERFLOW8,
 205     EXC_WINDOW_UNDERFLOW8,
 206     EXC_WINDOW_OVERFLOW12,
 207     EXC_WINDOW_UNDERFLOW12,
 208     EXC_IRQ,
 209     EXC_KERNEL,
 210     EXC_USER,
 211     EXC_DOUBLE,
 212     EXC_DEBUG,
 213     EXC_MAX
 214 };
 215
 216 enum {
 217     ILLEGAL_INSTRUCTION_CAUSE = 0,
 218     SYSCALL_CAUSE,
 219     INSTRUCTION_FETCH_ERROR_CAUSE,
 220     LOAD_STORE_ERROR_CAUSE,
 221     LEVEL1_INTERRUPT_CAUSE,
 222     ALLOCA_CAUSE,
 223     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 224     PRIVILEGED_CAUSE = 8,
 225     LOAD_STORE_ALIGNMENT_CAUSE,
 226
 227     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 228     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 229     INSTR_PIF_ADDR_ERROR_CAUSE,
 230     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 231
 232     INST_TLB_MISS_CAUSE,
 233     INST_TLB_MULTI_HIT_CAUSE,
 234     INST_FETCH_PRIVILEGE_CAUSE,
 235     INST_FETCH_PROHIBITED_CAUSE = 20,
 236     LOAD_STORE_TLB_MISS_CAUSE = 24,
 237     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 238     LOAD_STORE_PRIVILEGE_CAUSE,
 239     LOAD_PROHIBITED_CAUSE = 28,
 240     STORE_PROHIBITED_CAUSE,
 241
 242     COPROCESSOR0_DISABLED = 32,
 243 };
 244
 245 typedef enum {
 246     INTTYPE_LEVEL,
 247     INTTYPE_EDGE,
 248     INTTYPE_NMI,
 249     INTTYPE_SOFTWARE,
 250     INTTYPE_TIMER,
 251     INTTYPE_DEBUG,
 252     INTTYPE_WRITE_ERR,
 253     INTTYPE_MAX
 254 } interrupt_type;
 255
 256 typedef struct xtensa_tlb_entry {
 257     uint32_t vaddr;
 258     uint32_t paddr;
 259     uint8_t asid;
 260     uint8_t attr;
 261     bool variable;
 262 } xtensa_tlb_entry;
 263
 264 typedef struct xtensa_tlb {
 265     unsigned nways;
 266     const unsigned way_size[10];
 267     bool varway56;
 268     unsigned nrefillentries;
 269 } xtensa_tlb;
 270
 271 typedef struct XtensaGdbReg {
 272     int targno;
 273     int type;
 274     int group;
 275 } XtensaGdbReg;
 276
 277 typedef struct XtensaGdbRegmap {
 278     int num_regs;
 279     int num_core_regs;
 280     /* PC + a + ar + sr + ur */
 281     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
 282 } XtensaGdbRegmap;
 283
 284 typedef struct XtensaConfig {
 285     const char *name;
 286     uint64_t options;
 287     XtensaGdbRegmap gdb_regmap;
 288     unsigned nareg;
 289     int excm_level;
 290     int ndepc;
 291     uint32_t vecbase;
 292     uint32_t exception_vector[EXC_MAX];
 293     unsigned ninterrupt;
 294     unsigned nlevel;
 295     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 296     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 297     uint32_t inttype_mask[INTTYPE_MAX];
 298     struct {
 299         uint32_t level;
 300         interrupt_type inttype;
 301     } interrupt[MAX_NINTERRUPT];
 302     unsigned nccompare;
 303     uint32_t timerint[MAX_NCCOMPARE];
 304     unsigned nextint;
 305     unsigned extint[MAX_NINTERRUPT];
 306
 307     unsigned debug_level;
 308     unsigned nibreak;
 309     unsigned ndbreak;
 310
 311     uint32_t clock_freq_khz;
 312
 313     xtensa_tlb itlb;
 314     xtensa_tlb dtlb;
 315 } XtensaConfig;
 316
 317 typedef struct XtensaConfigList {
 318     const XtensaConfig *config;
 319     struct XtensaConfigList *next;
 320 } XtensaConfigList;
 321
 322 typedef struct CPUXtensaState {
 323     const XtensaConfig *config;
 324     uint32_t regs[16];
 325     uint32_t pc;
 326     uint32_t sregs[256];
 327     uint32_t uregs[256];
 328     uint32_t phys_regs[MAX_NAREG];
 329     float32 fregs[16];
 330     float_status fp_status;
 331
 332     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 333     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
 334     unsigned autorefill_idx;
 335
 336     int pending_irq_level; /* level of last raised IRQ */
 337     void **irq_inputs;
 338     QEMUTimer *ccompare_timer;
 339     uint32_t wake_ccount;
 340     int64_t halt_clock;
 341
 342     int exception_taken;
 343
 344     /* Watchpoints for DBREAK registers */
 345     CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
 346
 347     CPU_COMMON
 348 } CPUXtensaState;
 349
 350 #include "cpu-qom.h"
 351
 352 #define cpu_exec cpu_xtensa_exec
 353 #define cpu_gen_code cpu_xtensa_gen_code
 354 #define cpu_signal_handler cpu_xtensa_signal_handler
 355 #define cpu_list xtensa_cpu_list
 356
 357 #ifdef TARGET_WORDS_BIGENDIAN
 358 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
 359 #else
 360 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
 361 #endif
 362
 363 XtensaCPU *cpu_xtensa_init(const char *cpu_model);
 364
 365 static inline CPUXtensaState *cpu_init(const char *cpu_model)
 366 {
 367     XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
 368     if (cpu == NULL) {
 369         return NULL;
 370     }
 371     return &cpu->env;
 372 }
 373
 374 void xtensa_translate_init(void);
 375 int cpu_xtensa_exec(CPUXtensaState *s);
 376 void xtensa_register_core(XtensaConfigList *node);
 377 void do_interrupt(CPUXtensaState *s);
 378 void check_interrupts(CPUXtensaState *s);
 379 void xtensa_irq_init(CPUXtensaState *env);
 380 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
 381 void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
 382 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
 383 void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
 384 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 385 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 386 void xtensa_sync_window_from_phys(CPUXtensaState *env);
 387 void xtensa_sync_phys_from_window(CPUXtensaState *env);
 388 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
 389 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 390         uint32_t *vpn, uint32_t wi, uint32_t *ei);
 391 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 392         uint32_t *pwi, uint32_t *pei, uint8_t *pring);
 393 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 394         xtensa_tlb_entry *entry, bool dtlb,
 395         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 396 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 397         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 398 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 399         uint32_t vaddr, int is_write, int mmu_idx,
 400         uint32_t *paddr, uint32_t *page_size, unsigned *access);
 401 void reset_mmu(CPUXtensaState *env);
 402 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
 403 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
 404
 405
 406 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 407
 408 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
 409         uint64_t opt)
 410 {
 411     return (config->options & opt) != 0;
 412 }
 413
 414 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 415 {
 416     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 417 }
 418
 419 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
 420 {
 421     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 422     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 423         level = env->config->excm_level;
 424     }
 425     return level;
 426 }
 427
 428 static inline int xtensa_get_ring(const CPUXtensaState *env)
 429 {
 430     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 431         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 432     } else {
 433         return 0;
 434     }
 435 }
 436
 437 static inline int xtensa_get_cring(const CPUXtensaState *env)
 438 {
 439     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 440             (env->sregs[PS] & PS_EXCM) == 0) {
 441         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 442     } else {
 443         return 0;
 444     }
 445 }
 446
 447 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
 448         bool dtlb, unsigned wi, unsigned ei)
 449 {
 450     return dtlb ?
 451         env->dtlb[wi] + ei :
 452         env->itlb[wi] + ei;
 453 }
 454
 455 /* MMU modes definitions */
 456 #define MMU_MODE0_SUFFIX _ring0
 457 #define MMU_MODE1_SUFFIX _ring1
 458 #define MMU_MODE2_SUFFIX _ring2
 459 #define MMU_MODE3_SUFFIX _ring3
 460
 461 static inline int cpu_mmu_index(CPUXtensaState *env)
 462 {
 463     return xtensa_get_cring(env);
 464 }
 465
 466 #define XTENSA_TBFLAG_RING_MASK 0x3
 467 #define XTENSA_TBFLAG_EXCM 0x4
 468 #define XTENSA_TBFLAG_LITBASE 0x8
 469 #define XTENSA_TBFLAG_DEBUG 0x10
 470 #define XTENSA_TBFLAG_ICOUNT 0x20
 471 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
 472 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
 473
 474 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 475         target_ulong *cs_base, int *flags)
 476 {
 477     *pc = env->pc;
 478     *cs_base = 0;
 479     *flags = 0;
 480     *flags |= xtensa_get_ring(env);
 481     if (env->sregs[PS] & PS_EXCM) {
 482         *flags |= XTENSA_TBFLAG_EXCM;
 483     }
 484     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 485             (env->sregs[LITBASE] & 1)) {
 486         *flags |= XTENSA_TBFLAG_LITBASE;
 487     }
 488     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
 489         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 490             *flags |= XTENSA_TBFLAG_DEBUG;
 491         }
 492         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
 493             *flags |= XTENSA_TBFLAG_ICOUNT;
 494         }
 495     }
 496     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
 497         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
 498     }
 499 }
 500
 501 #include "cpu-all.h"
 502 #include "exec-all.h"
 503
 504 static inline int cpu_has_work(CPUXtensaState *env)
 505 {
 506     return env->pending_irq_level;
 507 }
 508
 509 static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock *tb)
 510 {
 511     env->pc = tb->pc;
 512 }
 513
 514 #endif