hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "mc146818rtc.h"
  28
  29 #ifdef TARGET_I386
  30 #include "apic.h"
  31 #endif
  32
  33 //#define DEBUG_CMOS
  34 //#define DEBUG_COALESCED
  35
  36 #ifdef DEBUG_CMOS
  37 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  38 #else
  39 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  40 #endif
  41
  42 #ifdef DEBUG_COALESCED
  43 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  44 #else
  45 # define DPRINTF_C(format, ...)      do { } while (0)
  46 #endif
  47
  48 #define NSEC_PER_SEC    1000000000LL
  49 #define SEC_PER_MIN     60
  50 #define MIN_PER_HOUR    60
  51 #define SEC_PER_HOUR    3600
  52 #define HOUR_PER_DAY    24
  53 #define SEC_PER_DAY     86400
  54
  55 #define RTC_REINJECT_ON_ACK_COUNT 20
  56 #define RTC_CLOCK_RATE            32768
  57 #define UIP_HOLD_LENGTH           (8 * NSEC_PER_SEC / 32768)
  58
  59 typedef struct RTCState {
  60     ISADevice dev;
  61     MemoryRegion io;
  62     uint8_t cmos_data[128];
  63     uint8_t cmos_index;
  64     int32_t base_year;
  65     uint64_t base_rtc;
  66     uint64_t last_update;
  67     int64_t offset;
  68     qemu_irq irq;
  69     qemu_irq sqw_irq;
  70     int it_shift;
  71     /* periodic timer */
  72     QEMUTimer *periodic_timer;
  73     int64_t next_periodic_time;
  74     /* update-ended timer */
  75     QEMUTimer *update_timer;
  76     uint64_t next_alarm_time;
  77     uint16_t irq_reinject_on_ack_count;
  78     uint32_t irq_coalesced;
  79     uint32_t period;
  80     QEMUTimer *coalesced_timer;
  81     Notifier clock_reset_notifier;
  82     LostTickPolicy lost_tick_policy;
  83     Notifier suspend_notifier;
  84 } RTCState;
  85
  86 static void rtc_set_time(RTCState *s);
  87 static void rtc_update_time(RTCState *s);
  88 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  89 static inline int rtc_from_bcd(RTCState *s, int a);
  90 static uint64_t get_next_alarm(RTCState *s);
  91
  92 static inline bool rtc_running(RTCState *s)
  93 {
  94     return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
  95             (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
  96 }
  97
  98 static uint64_t get_guest_rtc_ns(RTCState *s)
  99 {
 100     uint64_t guest_rtc;
 101     uint64_t guest_clock = qemu_get_clock_ns(rtc_clock);
 102
 103     guest_rtc = s->base_rtc * NSEC_PER_SEC
 104                  + guest_clock - s->last_update + s->offset;
 105     return guest_rtc;
 106 }
 107
 108 #ifdef TARGET_I386
 109 static void rtc_coalesced_timer_update(RTCState *s)
 110 {
 111     if (s->irq_coalesced == 0) {
 112         qemu_del_timer(s->coalesced_timer);
 113     } else {
 114         /* divide each RTC interval to 2 - 8 smaller intervals */
 115         int c = MIN(s->irq_coalesced, 7) + 1;
 116         int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
 117             muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
 118         qemu_mod_timer(s->coalesced_timer, next_clock);
 119     }
 120 }
 121
 122 static void rtc_coalesced_timer(void *opaque)
 123 {
 124     RTCState *s = opaque;
 125
 126     if (s->irq_coalesced != 0) {
 127         apic_reset_irq_delivered();
 128         s->cmos_data[RTC_REG_C] |= 0xc0;
 129         DPRINTF_C("cmos: injecting from timer\n");
 130         qemu_irq_raise(s->irq);
 131         if (apic_get_irq_delivered()) {
 132             s->irq_coalesced--;
 133             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 134                       s->irq_coalesced);
 135         }
 136     }
 137
 138     rtc_coalesced_timer_update(s);
 139 }
 140 #endif
 141
 142 /* handle periodic timer */
 143 static void periodic_timer_update(RTCState *s, int64_t current_time)
 144 {
 145     int period_code, period;
 146     int64_t cur_clock, next_irq_clock;
 147
 148     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 149     if (period_code != 0
 150         && ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
 151             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 152         if (period_code <= 2)
 153             period_code += 7;
 154         /* period in 32 Khz cycles */
 155         period = 1 << (period_code - 1);
 156 #ifdef TARGET_I386
 157         if (period != s->period) {
 158             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 159             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 160         }
 161         s->period = period;
 162 #endif
 163         /* compute 32 khz clock */
 164         cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
 165         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 166         s->next_periodic_time =
 167             muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
 168         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 169     } else {
 170 #ifdef TARGET_I386
 171         s->irq_coalesced = 0;
 172 #endif
 173         qemu_del_timer(s->periodic_timer);
 174     }
 175 }
 176
 177 static void rtc_periodic_timer(void *opaque)
 178 {
 179     RTCState *s = opaque;
 180
 181     periodic_timer_update(s, s->next_periodic_time);
 182     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 183     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 184         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 185 #ifdef TARGET_I386
 186         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 187             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 188                 s->irq_reinject_on_ack_count = 0;
 189             apic_reset_irq_delivered();
 190             qemu_irq_raise(s->irq);
 191             if (!apic_get_irq_delivered()) {
 192                 s->irq_coalesced++;
 193                 rtc_coalesced_timer_update(s);
 194                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 195                           s->irq_coalesced);
 196             }
 197         } else
 198 #endif
 199         qemu_irq_raise(s->irq);
 200     }
 201     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 202         /* Not square wave at all but we don't want 2048Hz interrupts!
 203            Must be seen as a pulse.  */
 204         qemu_irq_raise(s->sqw_irq);
 205     }
 206 }
 207
 208 /* handle update-ended timer */
 209 static void check_update_timer(RTCState *s)
 210 {
 211     uint64_t next_update_time;
 212     uint64_t guest_nsec;
 213     int next_alarm_sec;
 214
 215     /* From the data sheet: "Holding the dividers in reset prevents
 216      * interrupts from operating, while setting the SET bit allows"
 217      * them to occur.  However, it will prevent an alarm interrupt
 218      * from occurring, because the time of day is not updated.
 219      */
 220     if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
 221         qemu_del_timer(s->update_timer);
 222         return;
 223     }
 224     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 225         (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 226         qemu_del_timer(s->update_timer);
 227         return;
 228     }
 229     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 230         (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
 231         qemu_del_timer(s->update_timer);
 232         return;
 233     }
 234
 235     guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 236     /* if UF is clear, reprogram to next second */
 237     next_update_time = qemu_get_clock_ns(rtc_clock)
 238         + NSEC_PER_SEC - guest_nsec;
 239
 240     /* Compute time of next alarm.  One second is already accounted
 241      * for in next_update_time.
 242      */
 243     next_alarm_sec = get_next_alarm(s);
 244     s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
 245
 246     if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
 247         /* UF is set, but AF is clear.  Program the timer to target
 248          * the alarm time.  */
 249         next_update_time = s->next_alarm_time;
 250     }
 251     if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
 252         qemu_mod_timer(s->update_timer, next_update_time);
 253     }
 254 }
 255
 256 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
 257 {
 258     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 259         hour %= 12;
 260         if (s->cmos_data[RTC_HOURS] & 0x80) {
 261             hour += 12;
 262         }
 263     }
 264     return hour;
 265 }
 266
 267 static uint64_t get_next_alarm(RTCState *s)
 268 {
 269     int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
 270     int32_t hour, min, sec;
 271
 272     rtc_update_time(s);
 273
 274     alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
 275     alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
 276     alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
 277     alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
 278
 279     cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 280     cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 281     cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
 282     cur_hour = convert_hour(s, cur_hour);
 283
 284     if (alarm_hour == -1) {
 285         alarm_hour = cur_hour;
 286         if (alarm_min == -1) {
 287             alarm_min = cur_min;
 288             if (alarm_sec == -1) {
 289                 alarm_sec = cur_sec + 1;
 290             } else if (cur_sec > alarm_sec) {
 291                 alarm_min++;
 292             }
 293         } else if (cur_min == alarm_min) {
 294             if (alarm_sec == -1) {
 295                 alarm_sec = cur_sec + 1;
 296             } else {
 297                 if (cur_sec > alarm_sec) {
 298                     alarm_hour++;
 299                 }
 300             }
 301             if (alarm_sec == SEC_PER_MIN) {
 302                 /* wrap to next hour, minutes is not in don't care mode */
 303                 alarm_sec = 0;
 304                 alarm_hour++;
 305             }
 306         } else if (cur_min > alarm_min) {
 307             alarm_hour++;
 308         }
 309     } else if (cur_hour == alarm_hour) {
 310         if (alarm_min == -1) {
 311             alarm_min = cur_min;
 312             if (alarm_sec == -1) {
 313                 alarm_sec = cur_sec + 1;
 314             } else if (cur_sec > alarm_sec) {
 315                 alarm_min++;
 316             }
 317
 318             if (alarm_sec == SEC_PER_MIN) {
 319                 alarm_sec = 0;
 320                 alarm_min++;
 321             }
 322             /* wrap to next day, hour is not in don't care mode */
 323             alarm_min %= MIN_PER_HOUR;
 324         } else if (cur_min == alarm_min) {
 325             if (alarm_sec == -1) {
 326                 alarm_sec = cur_sec + 1;
 327             }
 328             /* wrap to next day, hours+minutes not in don't care mode */
 329             alarm_sec %= SEC_PER_MIN;
 330         }
 331     }
 332
 333     /* values that are still don't care fire at the next min/sec */
 334     if (alarm_min == -1) {
 335         alarm_min = 0;
 336     }
 337     if (alarm_sec == -1) {
 338         alarm_sec = 0;
 339     }
 340
 341     /* keep values in range */
 342     if (alarm_sec == SEC_PER_MIN) {
 343         alarm_sec = 0;
 344         alarm_min++;
 345     }
 346     if (alarm_min == MIN_PER_HOUR) {
 347         alarm_min = 0;
 348         alarm_hour++;
 349     }
 350     alarm_hour %= HOUR_PER_DAY;
 351
 352     hour = alarm_hour - cur_hour;
 353     min = hour * MIN_PER_HOUR + alarm_min - cur_min;
 354     sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
 355     return sec <= 0 ? sec + SEC_PER_DAY : sec;
 356 }
 357
 358 static void rtc_update_timer(void *opaque)
 359 {
 360     RTCState *s = opaque;
 361     int32_t irqs = REG_C_UF;
 362     int32_t new_irqs;
 363
 364     assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
 365
 366     /* UIP might have been latched, update time and clear it.  */
 367     rtc_update_time(s);
 368     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 369
 370     if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
 371         irqs |= REG_C_AF;
 372         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 373             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 374         }
 375     }
 376
 377     new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
 378     s->cmos_data[RTC_REG_C] |= irqs;
 379     if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
 380         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 381         qemu_irq_raise(s->irq);
 382     }
 383     check_update_timer(s);
 384 }
 385
 386 static void cmos_ioport_write(void *opaque, hwaddr addr,
 387                               uint64_t data, unsigned size)
 388 {
 389     RTCState *s = opaque;
 390
 391     if ((addr & 1) == 0) {
 392         s->cmos_index = data & 0x7f;
 393     } else {
 394         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 395                      s->cmos_index, data);
 396         switch(s->cmos_index) {
 397         case RTC_SECONDS_ALARM:
 398         case RTC_MINUTES_ALARM:
 399         case RTC_HOURS_ALARM:
 400             s->cmos_data[s->cmos_index] = data;
 401             check_update_timer(s);
 402             break;
 403         case RTC_IBM_PS2_CENTURY_BYTE:
 404             s->cmos_index = RTC_CENTURY;
 405             /* fall through */
 406         case RTC_CENTURY:
 407         case RTC_SECONDS:
 408         case RTC_MINUTES:
 409         case RTC_HOURS:
 410         case RTC_DAY_OF_WEEK:
 411         case RTC_DAY_OF_MONTH:
 412         case RTC_MONTH:
 413         case RTC_YEAR:
 414             s->cmos_data[s->cmos_index] = data;
 415             /* if in set mode, do not update the time */
 416             if (rtc_running(s)) {
 417                 rtc_set_time(s);
 418                 check_update_timer(s);
 419             }
 420             break;
 421         case RTC_REG_A:
 422             if ((data & 0x60) == 0x60) {
 423                 if (rtc_running(s)) {
 424                     rtc_update_time(s);
 425                 }
 426                 /* What happens to UIP when divider reset is enabled is
 427                  * unclear from the datasheet.  Shouldn't matter much
 428                  * though.
 429                  */
 430                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 431             } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
 432                     (data & 0x70)  <= 0x20) {
 433                 /* when the divider reset is removed, the first update cycle
 434                  * begins one-half second later*/
 435                 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 436                     s->offset = 500000000;
 437                     rtc_set_time(s);
 438                 }
 439                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 440             }
 441             /* UIP bit is read only */
 442             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 443                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 444             periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
 445             check_update_timer(s);
 446             break;
 447         case RTC_REG_B:
 448             if (data & REG_B_SET) {
 449                 /* update cmos to when the rtc was stopping */
 450                 if (rtc_running(s)) {
 451                     rtc_update_time(s);
 452                 }
 453                 /* set mode: reset UIP mode */
 454                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 455                 data &= ~REG_B_UIE;
 456             } else {
 457                 /* if disabling set mode, update the time */
 458                 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 459                     (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
 460                     s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 461                     rtc_set_time(s);
 462                 }
 463             }
 464             /* if an interrupt flag is already set when the interrupt
 465              * becomes enabled, raise an interrupt immediately.  */
 466             if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
 467                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 468                 qemu_irq_raise(s->irq);
 469             } else {
 470                 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
 471                 qemu_irq_lower(s->irq);
 472             }
 473             s->cmos_data[RTC_REG_B] = data;
 474             periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
 475             check_update_timer(s);
 476             break;
 477         case RTC_REG_C:
 478         case RTC_REG_D:
 479             /* cannot write to them */
 480             break;
 481         default:
 482             s->cmos_data[s->cmos_index] = data;
 483             break;
 484         }
 485     }
 486 }
 487
 488 static inline int rtc_to_bcd(RTCState *s, int a)
 489 {
 490     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 491         return a;
 492     } else {
 493         return ((a / 10) << 4) | (a % 10);
 494     }
 495 }
 496
 497 static inline int rtc_from_bcd(RTCState *s, int a)
 498 {
 499     if ((a & 0xc0) == 0xc0) {
 500         return -1;
 501     }
 502     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 503         return a;
 504     } else {
 505         return ((a >> 4) * 10) + (a & 0x0f);
 506     }
 507 }
 508
 509 static void rtc_get_time(RTCState *s, struct tm *tm)
 510 {
 511     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 512     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 513     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 514     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 515         tm->tm_hour %= 12;
 516         if (s->cmos_data[RTC_HOURS] & 0x80) {
 517             tm->tm_hour += 12;
 518         }
 519     }
 520     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 521     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 522     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 523     tm->tm_year =
 524         rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
 525         rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
 526 }
 527
 528 static void rtc_set_time(RTCState *s)
 529 {
 530     struct tm tm;
 531
 532     rtc_get_time(s, &tm);
 533     s->base_rtc = mktimegm(&tm);
 534     s->last_update = qemu_get_clock_ns(rtc_clock);
 535
 536     rtc_change_mon_event(&tm);
 537 }
 538
 539 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
 540 {
 541     int year;
 542
 543     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 544     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 545     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 546         /* 24 hour format */
 547         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 548     } else {
 549         /* 12 hour format */
 550         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 551         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 552         if (tm->tm_hour >= 12)
 553             s->cmos_data[RTC_HOURS] |= 0x80;
 554     }
 555     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 556     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 557     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 558     year = tm->tm_year + 1900 - s->base_year;
 559     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
 560     s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
 561 }
 562
 563 static void rtc_update_time(RTCState *s)
 564 {
 565     struct tm ret;
 566     time_t guest_sec;
 567     int64_t guest_nsec;
 568
 569     guest_nsec = get_guest_rtc_ns(s);
 570     guest_sec = guest_nsec / NSEC_PER_SEC;
 571     gmtime_r(&guest_sec, &ret);
 572     rtc_set_cmos(s, &ret);
 573 }
 574
 575 static int update_in_progress(RTCState *s)
 576 {
 577     int64_t guest_nsec;
 578
 579     if (!rtc_running(s)) {
 580         return 0;
 581     }
 582     if (qemu_timer_pending(s->update_timer)) {
 583         int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer);
 584         /* Latch UIP until the timer expires.  */
 585         if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
 586             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 587             return 1;
 588         }
 589     }
 590
 591     guest_nsec = get_guest_rtc_ns(s);
 592     /* UIP bit will be set at last 244us of every second. */
 593     if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
 594         return 1;
 595     }
 596     return 0;
 597 }
 598
 599 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
 600                                  unsigned size)
 601 {
 602     RTCState *s = opaque;
 603     int ret;
 604     if ((addr & 1) == 0) {
 605         return 0xff;
 606     } else {
 607         switch(s->cmos_index) {
 608         case RTC_IBM_PS2_CENTURY_BYTE:
 609             s->cmos_index = RTC_CENTURY;
 610             /* fall through */
 611         case RTC_CENTURY:
 612         case RTC_SECONDS:
 613         case RTC_MINUTES:
 614         case RTC_HOURS:
 615         case RTC_DAY_OF_WEEK:
 616         case RTC_DAY_OF_MONTH:
 617         case RTC_MONTH:
 618         case RTC_YEAR:
 619             /* if not in set mode, calibrate cmos before
 620              * reading*/
 621             if (rtc_running(s)) {
 622                 rtc_update_time(s);
 623             }
 624             ret = s->cmos_data[s->cmos_index];
 625             break;
 626         case RTC_REG_A:
 627             if (update_in_progress(s)) {
 628                 s->cmos_data[s->cmos_index] |= REG_A_UIP;
 629             } else {
 630                 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
 631             }
 632             ret = s->cmos_data[s->cmos_index];
 633             break;
 634         case RTC_REG_C:
 635             ret = s->cmos_data[s->cmos_index];
 636             qemu_irq_lower(s->irq);
 637             s->cmos_data[RTC_REG_C] = 0x00;
 638             if (ret & (REG_C_UF | REG_C_AF)) {
 639                 check_update_timer(s);
 640             }
 641 #ifdef TARGET_I386
 642             if(s->irq_coalesced &&
 643                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 644                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 645                 s->irq_reinject_on_ack_count++;
 646                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 647                 apic_reset_irq_delivered();
 648                 DPRINTF_C("cmos: injecting on ack\n");
 649                 qemu_irq_raise(s->irq);
 650                 if (apic_get_irq_delivered()) {
 651                     s->irq_coalesced--;
 652                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 653                               s->irq_coalesced);
 654                 }
 655             }
 656 #endif
 657             break;
 658         default:
 659             ret = s->cmos_data[s->cmos_index];
 660             break;
 661         }
 662         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 663                      s->cmos_index, ret);
 664         return ret;
 665     }
 666 }
 667
 668 void rtc_set_memory(ISADevice *dev, int addr, int val)
 669 {
 670     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 671     if (addr >= 0 && addr <= 127)
 672         s->cmos_data[addr] = val;
 673 }
 674
 675 static void rtc_set_date_from_host(ISADevice *dev)
 676 {
 677     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 678     struct tm tm;
 679
 680     qemu_get_timedate(&tm, 0);
 681
 682     s->base_rtc = mktimegm(&tm);
 683     s->last_update = qemu_get_clock_ns(rtc_clock);
 684     s->offset = 0;
 685
 686     /* set the CMOS date */
 687     rtc_set_cmos(s, &tm);
 688 }
 689
 690 static int rtc_post_load(void *opaque, int version_id)
 691 {
 692     RTCState *s = opaque;
 693
 694     if (version_id <= 2) {
 695         rtc_set_time(s);
 696         s->offset = 0;
 697         check_update_timer(s);
 698     }
 699
 700 #ifdef TARGET_I386
 701     if (version_id >= 2) {
 702         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 703             rtc_coalesced_timer_update(s);
 704         }
 705     }
 706 #endif
 707     return 0;
 708 }
 709
 710 static const VMStateDescription vmstate_rtc = {
 711     .name = "mc146818rtc",
 712     .version_id = 3,
 713     .minimum_version_id = 1,
 714     .minimum_version_id_old = 1,
 715     .post_load = rtc_post_load,
 716     .fields      = (VMStateField []) {
 717         VMSTATE_BUFFER(cmos_data, RTCState),
 718         VMSTATE_UINT8(cmos_index, RTCState),
 719         VMSTATE_UNUSED(7*4),
 720         VMSTATE_TIMER(periodic_timer, RTCState),
 721         VMSTATE_INT64(next_periodic_time, RTCState),
 722         VMSTATE_UNUSED(3*8),
 723         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 724         VMSTATE_UINT32_V(period, RTCState, 2),
 725         VMSTATE_UINT64_V(base_rtc, RTCState, 3),
 726         VMSTATE_UINT64_V(last_update, RTCState, 3),
 727         VMSTATE_INT64_V(offset, RTCState, 3),
 728         VMSTATE_TIMER_V(update_timer, RTCState, 3),
 729         VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
 730         VMSTATE_END_OF_LIST()
 731     }
 732 };
 733
 734 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 735 {
 736     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 737     int64_t now = *(int64_t *)data;
 738
 739     rtc_set_date_from_host(&s->dev);
 740     periodic_timer_update(s, now);
 741     check_update_timer(s);
 742 #ifdef TARGET_I386
 743     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 744         rtc_coalesced_timer_update(s);
 745     }
 746 #endif
 747 }
 748
 749 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 750    BIOS will read it and start S3 resume at POST Entry */
 751 static void rtc_notify_suspend(Notifier *notifier, void *data)
 752 {
 753     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 754     rtc_set_memory(&s->dev, 0xF, 0xFE);
 755 }
 756
 757 static void rtc_reset(void *opaque)
 758 {
 759     RTCState *s = opaque;
 760
 761     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 762     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 763     check_update_timer(s);
 764
 765     qemu_irq_lower(s->irq);
 766
 767 #ifdef TARGET_I386
 768     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 769         s->irq_coalesced = 0;
 770     }
 771 #endif
 772 }
 773
 774 static const MemoryRegionOps cmos_ops = {
 775     .read = cmos_ioport_read,
 776     .write = cmos_ioport_write,
 777     .impl = {
 778         .min_access_size = 1,
 779         .max_access_size = 1,
 780     },
 781     .endianness = DEVICE_LITTLE_ENDIAN,
 782 };
 783
 784 static void rtc_get_date(Object *obj, Visitor *v, void *opaque,
 785                          const char *name, Error **errp)
 786 {
 787     ISADevice *isa = ISA_DEVICE(obj);
 788     RTCState *s = DO_UPCAST(RTCState, dev, isa);
 789     struct tm current_tm;
 790
 791     rtc_update_time(s);
 792     rtc_get_time(s, &current_tm);
 793     visit_start_struct(v, NULL, "struct tm", name, 0, errp);
 794     visit_type_int32(v, &current_tm.tm_year, "tm_year", errp);
 795     visit_type_int32(v, &current_tm.tm_mon, "tm_mon", errp);
 796     visit_type_int32(v, &current_tm.tm_mday, "tm_mday", errp);
 797     visit_type_int32(v, &current_tm.tm_hour, "tm_hour", errp);
 798     visit_type_int32(v, &current_tm.tm_min, "tm_min", errp);
 799     visit_type_int32(v, &current_tm.tm_sec, "tm_sec", errp);
 800     visit_end_struct(v, errp);
 801 }
 802
 803 static int rtc_initfn(ISADevice *dev)
 804 {
 805     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 806     int base = 0x70;
 807
 808     s->cmos_data[RTC_REG_A] = 0x26;
 809     s->cmos_data[RTC_REG_B] = 0x02;
 810     s->cmos_data[RTC_REG_C] = 0x00;
 811     s->cmos_data[RTC_REG_D] = 0x80;
 812
 813     /* This is for historical reasons.  The default base year qdev property
 814      * was set to 2000 for most machine types before the century byte was
 815      * implemented.
 816      *
 817      * This if statement means that the century byte will be always 0
 818      * (at least until 2079...) for base_year = 1980, but will be set
 819      * correctly for base_year = 2000.
 820      */
 821     if (s->base_year == 2000) {
 822         s->base_year = 0;
 823     }
 824
 825     rtc_set_date_from_host(dev);
 826
 827 #ifdef TARGET_I386
 828     switch (s->lost_tick_policy) {
 829     case LOST_TICK_SLEW:
 830         s->coalesced_timer =
 831             qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
 832         break;
 833     case LOST_TICK_DISCARD:
 834         break;
 835     default:
 836         return -EINVAL;
 837     }
 838 #endif
 839
 840     s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
 841     s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s);
 842     check_update_timer(s);
 843
 844     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 845     qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
 846
 847     s->suspend_notifier.notify = rtc_notify_suspend;
 848     qemu_register_suspend_notifier(&s->suspend_notifier);
 849
 850     memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
 851     isa_register_ioport(dev, &s->io, base);
 852
 853     qdev_set_legacy_instance_id(&dev->qdev, base, 3);
 854     qemu_register_reset(rtc_reset, s);
 855
 856     object_property_add(OBJECT(s), "date", "struct tm",
 857                         rtc_get_date, NULL, NULL, s, NULL);
 858
 859     return 0;
 860 }
 861
 862 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 863 {
 864     ISADevice *dev;
 865     RTCState *s;
 866
 867     dev = isa_create(bus, "mc146818rtc");
 868     s = DO_UPCAST(RTCState, dev, dev);
 869     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 870     qdev_init_nofail(&dev->qdev);
 871     if (intercept_irq) {
 872         s->irq = intercept_irq;
 873     } else {
 874         isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
 875     }
 876     return dev;
 877 }
 878
 879 static Property mc146818rtc_properties[] = {
 880     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 881     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 882                                lost_tick_policy, LOST_TICK_DISCARD),
 883     DEFINE_PROP_END_OF_LIST(),
 884 };
 885
 886 static void rtc_class_initfn(ObjectClass *klass, void *data)
 887 {
 888     DeviceClass *dc = DEVICE_CLASS(klass);
 889     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 890     ic->init = rtc_initfn;
 891     dc->no_user = 1;
 892     dc->vmsd = &vmstate_rtc;
 893     dc->props = mc146818rtc_properties;
 894 }
 895
 896 static TypeInfo mc146818rtc_info = {
 897     .name          = "mc146818rtc",
 898     .parent        = TYPE_ISA_DEVICE,
 899     .instance_size = sizeof(RTCState),
 900     .class_init    = rtc_class_initfn,
 901 };
 902
 903 static void mc146818rtc_register_types(void)
 904 {
 905     type_register_static(&mc146818rtc_info);
 906 }
 907
 908 type_init(mc146818rtc_register_types)