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gdbstub: Fix qOffsets packet detection
[qemu/qmp-unstable.git] / hw / ppc / spapr_pci.c
blob05f4faca6e07ebab25d96244ebf6246eb661962e
1 /*
2 * QEMU sPAPR PCI host originated from Uninorth PCI host
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "hw/hw.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/ppc/spapr.h"
31 #include "hw/pci-host/spapr.h"
32 #include "exec/address-spaces.h"
33 #include <libfdt.h>
34 #include "trace.h"
35 #include "qemu/error-report.h"
36
37 #include "hw/pci/pci_bus.h"
38
39 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
40 #define RTAS_QUERY_FN 0
41 #define RTAS_CHANGE_FN 1
42 #define RTAS_RESET_FN 2
43 #define RTAS_CHANGE_MSI_FN 3
44 #define RTAS_CHANGE_MSIX_FN 4
45
46 /* Interrupt types to return on RTAS_CHANGE_* */
47 #define RTAS_TYPE_MSI 1
48 #define RTAS_TYPE_MSIX 2
49
50 static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
51 {
52 sPAPRPHBState *sphb;
53
54 QLIST_FOREACH(sphb, &spapr->phbs, list) {
55 if (sphb->buid != buid) {
56 continue;
57 }
58 return sphb;
59 }
60
61 return NULL;
62 }
63
64 static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
65 uint32_t config_addr)
66 {
67 sPAPRPHBState *sphb = find_phb(spapr, buid);
68 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
69 int bus_num = (config_addr >> 16) & 0xFF;
70 int devfn = (config_addr >> 8) & 0xFF;
71
72 if (!phb) {
73 return NULL;
74 }
75
76 return pci_find_device(phb->bus, bus_num, devfn);
77 }
78
79 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
80 {
81 /* This handles the encoding of extended config space addresses */
82 return ((arg >> 20) & 0xf00) | (arg & 0xff);
83 }
84
85 static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
86 uint32_t addr, uint32_t size,
87 target_ulong rets)
88 {
89 PCIDevice *pci_dev;
90 uint32_t val;
91
92 if ((size != 1) && (size != 2) && (size != 4)) {
93 /* access must be 1, 2 or 4 bytes */
94 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
95 return;
96 }
97
98 pci_dev = find_dev(spapr, buid, addr);
99 addr = rtas_pci_cfgaddr(addr);
100
101 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
102 /* Access must be to a valid device, within bounds and
103 * naturally aligned */
104 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
105 return;
106 }
107
108 val = pci_host_config_read_common(pci_dev, addr,
109 pci_config_size(pci_dev), size);
110
111 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
112 rtas_st(rets, 1, val);
113 }
114
115 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
116 uint32_t token, uint32_t nargs,
117 target_ulong args,
118 uint32_t nret, target_ulong rets)
119 {
120 uint64_t buid;
121 uint32_t size, addr;
122
123 if ((nargs != 4) || (nret != 2)) {
124 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
125 return;
126 }
127
128 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
129 size = rtas_ld(args, 3);
130 addr = rtas_ld(args, 0);
131
132 finish_read_pci_config(spapr, buid, addr, size, rets);
133 }
134
135 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
136 uint32_t token, uint32_t nargs,
137 target_ulong args,
138 uint32_t nret, target_ulong rets)
139 {
140 uint32_t size, addr;
141
142 if ((nargs != 2) || (nret != 2)) {
143 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
144 return;
145 }
146
147 size = rtas_ld(args, 1);
148 addr = rtas_ld(args, 0);
149
150 finish_read_pci_config(spapr, 0, addr, size, rets);
151 }
152
153 static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
154 uint32_t addr, uint32_t size,
155 uint32_t val, target_ulong rets)
156 {
157 PCIDevice *pci_dev;
158
159 if ((size != 1) && (size != 2) && (size != 4)) {
160 /* access must be 1, 2 or 4 bytes */
161 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
162 return;
163 }
164
165 pci_dev = find_dev(spapr, buid, addr);
166 addr = rtas_pci_cfgaddr(addr);
167
168 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
169 /* Access must be to a valid device, within bounds and
170 * naturally aligned */
171 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
172 return;
173 }
174
175 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
176 val, size);
177
178 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
179 }
180
181 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
182 uint32_t token, uint32_t nargs,
183 target_ulong args,
184 uint32_t nret, target_ulong rets)
185 {
186 uint64_t buid;
187 uint32_t val, size, addr;
188
189 if ((nargs != 5) || (nret != 1)) {
190 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
191 return;
192 }
193
194 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
195 val = rtas_ld(args, 4);
196 size = rtas_ld(args, 3);
197 addr = rtas_ld(args, 0);
198
199 finish_write_pci_config(spapr, buid, addr, size, val, rets);
200 }
201
202 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
203 uint32_t token, uint32_t nargs,
204 target_ulong args,
205 uint32_t nret, target_ulong rets)
206 {
207 uint32_t val, size, addr;
208
209 if ((nargs != 3) || (nret != 1)) {
210 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
211 return;
212 }
213
214
215 val = rtas_ld(args, 2);
216 size = rtas_ld(args, 1);
217 addr = rtas_ld(args, 0);
218
219 finish_write_pci_config(spapr, 0, addr, size, val, rets);
220 }
221
222 /*
223 * Set MSI/MSIX message data.
224 * This is required for msi_notify()/msix_notify() which
225 * will write at the addresses via spapr_msi_write().
226 *
227 * If hwaddr == 0, all entries will have .data == first_irq i.e.
228 * table will be reset.
229 */
230 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
231 unsigned first_irq, unsigned req_num)
232 {
233 unsigned i;
234 MSIMessage msg = { .address = addr, .data = first_irq };
235
236 if (!msix) {
237 msi_set_message(pdev, msg);
238 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
239 return;
240 }
241
242 for (i = 0; i < req_num; ++i) {
243 msix_set_message(pdev, i, msg);
244 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
245 if (addr) {
246 ++msg.data;
247 }
248 }
249 }
250
251 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
252 uint32_t token, uint32_t nargs,
253 target_ulong args, uint32_t nret,
254 target_ulong rets)
255 {
256 uint32_t config_addr = rtas_ld(args, 0);
257 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
258 unsigned int func = rtas_ld(args, 3);
259 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
260 unsigned int seq_num = rtas_ld(args, 5);
261 unsigned int ret_intr_type;
262 unsigned int irq, max_irqs = 0, num = 0;
263 sPAPRPHBState *phb = NULL;
264 PCIDevice *pdev = NULL;
265 spapr_pci_msi *msi;
266 int *config_addr_key;
267
268 switch (func) {
269 case RTAS_CHANGE_MSI_FN:
270 case RTAS_CHANGE_FN:
271 ret_intr_type = RTAS_TYPE_MSI;
272 break;
273 case RTAS_CHANGE_MSIX_FN:
274 ret_intr_type = RTAS_TYPE_MSIX;
275 break;
276 default:
277 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
278 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
279 return;
280 }
281
282 /* Fins sPAPRPHBState */
283 phb = find_phb(spapr, buid);
284 if (phb) {
285 pdev = find_dev(spapr, buid, config_addr);
286 }
287 if (!phb || !pdev) {
288 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
289 return;
290 }
291
292 /* Releasing MSIs */
293 if (!req_num) {
294 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
295 if (!msi) {
296 trace_spapr_pci_msi("Releasing wrong config", config_addr);
297 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
298 return;
299 }
300
301 xics_free(spapr->icp, msi->first_irq, msi->num);
302 if (msi_present(pdev)) {
303 spapr_msi_setmsg(pdev, 0, false, 0, num);
304 }
305 if (msix_present(pdev)) {
306 spapr_msi_setmsg(pdev, 0, true, 0, num);
307 }
308 g_hash_table_remove(phb->msi, &config_addr);
309
310 trace_spapr_pci_msi("Released MSIs", config_addr);
311 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
312 rtas_st(rets, 1, 0);
313 return;
314 }
315
316 /* Enabling MSI */
317
318 /* Check if the device supports as many IRQs as requested */
319 if (ret_intr_type == RTAS_TYPE_MSI) {
320 max_irqs = msi_nr_vectors_allocated(pdev);
321 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
322 max_irqs = pdev->msix_entries_nr;
323 }
324 if (!max_irqs) {
325 error_report("Requested interrupt type %d is not enabled for device %x",
326 ret_intr_type, config_addr);
327 rtas_st(rets, 0, -1); /* Hardware error */
328 return;
329 }
330 /* Correct the number if the guest asked for too many */
331 if (req_num > max_irqs) {
332 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
333 req_num = max_irqs;
334 irq = 0; /* to avoid misleading trace */
335 goto out;
336 }
337
338 /* Allocate MSIs */
339 irq = xics_alloc_block(spapr->icp, 0, req_num, false,
340 ret_intr_type == RTAS_TYPE_MSI);
341 if (!irq) {
342 error_report("Cannot allocate MSIs for device %x", config_addr);
343 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
344 return;
345 }
346
347 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
348 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
349 irq, req_num);
350
351 /* Add MSI device to cache */
352 msi = g_new(spapr_pci_msi, 1);
353 msi->first_irq = irq;
354 msi->num = req_num;
355 config_addr_key = g_new(int, 1);
356 *config_addr_key = config_addr;
357 g_hash_table_insert(phb->msi, config_addr_key, msi);
358
359 out:
360 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
361 rtas_st(rets, 1, req_num);
362 rtas_st(rets, 2, ++seq_num);
363 rtas_st(rets, 3, ret_intr_type);
364
365 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
366 }
367
368 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
369 sPAPREnvironment *spapr,
370 uint32_t token,
371 uint32_t nargs,
372 target_ulong args,
373 uint32_t nret,
374 target_ulong rets)
375 {
376 uint32_t config_addr = rtas_ld(args, 0);
377 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
378 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
379 sPAPRPHBState *phb = NULL;
380 PCIDevice *pdev = NULL;
381 spapr_pci_msi *msi;
382
383 /* Find sPAPRPHBState */
384 phb = find_phb(spapr, buid);
385 if (phb) {
386 pdev = find_dev(spapr, buid, config_addr);
387 }
388 if (!phb || !pdev) {
389 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
390 return;
391 }
392
393 /* Find device descriptor and start IRQ */
394 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
395 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
396 trace_spapr_pci_msi("Failed to return vector", config_addr);
397 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
398 return;
399 }
400 intr_src_num = msi->first_irq + ioa_intr_num;
401 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
402 intr_src_num);
403
404 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
405 rtas_st(rets, 1, intr_src_num);
406 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
407 }
408
409 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
410 sPAPREnvironment *spapr,
411 uint32_t token, uint32_t nargs,
412 target_ulong args, uint32_t nret,
413 target_ulong rets)
414 {
415 sPAPRPHBState *sphb;
416 sPAPRPHBClass *spc;
417 uint32_t addr, option;
418 uint64_t buid;
419 int ret;
420
421 if ((nargs != 4) || (nret != 1)) {
422 goto param_error_exit;
423 }
424
425 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
426 addr = rtas_ld(args, 0);
427 option = rtas_ld(args, 3);
428
429 sphb = find_phb(spapr, buid);
430 if (!sphb) {
431 goto param_error_exit;
432 }
433
434 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
435 if (!spc->eeh_set_option) {
436 goto param_error_exit;
437 }
438
439 ret = spc->eeh_set_option(sphb, addr, option);
440 rtas_st(rets, 0, ret);
441 return;
442
443 param_error_exit:
444 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
445 }
446
447 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
448 sPAPREnvironment *spapr,
449 uint32_t token, uint32_t nargs,
450 target_ulong args, uint32_t nret,
451 target_ulong rets)
452 {
453 sPAPRPHBState *sphb;
454 sPAPRPHBClass *spc;
455 PCIDevice *pdev;
456 uint32_t addr, option;
457 uint64_t buid;
458
459 if ((nargs != 4) || (nret != 2)) {
460 goto param_error_exit;
461 }
462
463 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
464 sphb = find_phb(spapr, buid);
465 if (!sphb) {
466 goto param_error_exit;
467 }
468
469 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
470 if (!spc->eeh_set_option) {
471 goto param_error_exit;
472 }
473
474 /*
475 * We always have PE address of form "00BB0001". "BB"
476 * represents the bus number of PE's primary bus.
477 */
478 option = rtas_ld(args, 3);
479 switch (option) {
480 case RTAS_GET_PE_ADDR:
481 addr = rtas_ld(args, 0);
482 pdev = find_dev(spapr, buid, addr);
483 if (!pdev) {
484 goto param_error_exit;
485 }
486
487 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
488 break;
489 case RTAS_GET_PE_MODE:
490 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
491 break;
492 default:
493 goto param_error_exit;
494 }
495
496 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
497 return;
498
499 param_error_exit:
500 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
501 }
502
503 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
504 sPAPREnvironment *spapr,
505 uint32_t token, uint32_t nargs,
506 target_ulong args, uint32_t nret,
507 target_ulong rets)
508 {
509 sPAPRPHBState *sphb;
510 sPAPRPHBClass *spc;
511 uint64_t buid;
512 int state, ret;
513
514 if ((nargs != 3) || (nret != 4 && nret != 5)) {
515 goto param_error_exit;
516 }
517
518 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
519 sphb = find_phb(spapr, buid);
520 if (!sphb) {
521 goto param_error_exit;
522 }
523
524 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
525 if (!spc->eeh_get_state) {
526 goto param_error_exit;
527 }
528
529 ret = spc->eeh_get_state(sphb, &state);
530 rtas_st(rets, 0, ret);
531 if (ret != RTAS_OUT_SUCCESS) {
532 return;
533 }
534
535 rtas_st(rets, 1, state);
536 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
537 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
538 if (nret >= 5) {
539 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
540 }
541 return;
542
543 param_error_exit:
544 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
545 }
546
547 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
548 sPAPREnvironment *spapr,
549 uint32_t token, uint32_t nargs,
550 target_ulong args, uint32_t nret,
551 target_ulong rets)
552 {
553 sPAPRPHBState *sphb;
554 sPAPRPHBClass *spc;
555 uint32_t option;
556 uint64_t buid;
557 int ret;
558
559 if ((nargs != 4) || (nret != 1)) {
560 goto param_error_exit;
561 }
562
563 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
564 option = rtas_ld(args, 3);
565 sphb = find_phb(spapr, buid);
566 if (!sphb) {
567 goto param_error_exit;
568 }
569
570 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
571 if (!spc->eeh_reset) {
572 goto param_error_exit;
573 }
574
575 ret = spc->eeh_reset(sphb, option);
576 rtas_st(rets, 0, ret);
577 return;
578
579 param_error_exit:
580 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
581 }
582
583 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
584 sPAPREnvironment *spapr,
585 uint32_t token, uint32_t nargs,
586 target_ulong args, uint32_t nret,
587 target_ulong rets)
588 {
589 sPAPRPHBState *sphb;
590 sPAPRPHBClass *spc;
591 uint64_t buid;
592 int ret;
593
594 if ((nargs != 3) || (nret != 1)) {
595 goto param_error_exit;
596 }
597
598 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
599 sphb = find_phb(spapr, buid);
600 if (!sphb) {
601 goto param_error_exit;
602 }
603
604 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
605 if (!spc->eeh_configure) {
606 goto param_error_exit;
607 }
608
609 ret = spc->eeh_configure(sphb);
610 rtas_st(rets, 0, ret);
611 return;
612
613 param_error_exit:
614 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
615 }
616
617 /* To support it later */
618 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
619 sPAPREnvironment *spapr,
620 uint32_t token, uint32_t nargs,
621 target_ulong args, uint32_t nret,
622 target_ulong rets)
623 {
624 sPAPRPHBState *sphb;
625 sPAPRPHBClass *spc;
626 int option;
627 uint64_t buid;
628
629 if ((nargs != 8) || (nret != 1)) {
630 goto param_error_exit;
631 }
632
633 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
634 sphb = find_phb(spapr, buid);
635 if (!sphb) {
636 goto param_error_exit;
637 }
638
639 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
640 if (!spc->eeh_set_option) {
641 goto param_error_exit;
642 }
643
644 option = rtas_ld(args, 7);
645 switch (option) {
646 case RTAS_SLOT_TEMP_ERR_LOG:
647 case RTAS_SLOT_PERM_ERR_LOG:
648 break;
649 default:
650 goto param_error_exit;
651 }
652
653 /* We don't have error log yet */
654 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
655 return;
656
657 param_error_exit:
658 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
659 }
660
661 static int pci_spapr_swizzle(int slot, int pin)
662 {
663 return (slot + pin) % PCI_NUM_PINS;
664 }
665
666 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
667 {
668 /*
669 * Here we need to convert pci_dev + irq_num to some unique value
670 * which is less than number of IRQs on the specific bus (4). We
671 * use standard PCI swizzling, that is (slot number + pin number)
672 * % 4.
673 */
674 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
675 }
676
677 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
678 {
679 /*
680 * Here we use the number returned by pci_spapr_map_irq to find a
681 * corresponding qemu_irq.
682 */
683 sPAPRPHBState *phb = opaque;
684
685 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
686 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
687 }
688
689 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
690 {
691 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
692 PCIINTxRoute route;
693
694 route.mode = PCI_INTX_ENABLED;
695 route.irq = sphb->lsi_table[pin].irq;
696
697 return route;
698 }
699
700 /*
701 * MSI/MSIX memory region implementation.
702 * The handler handles both MSI and MSIX.
703 * For MSI-X, the vector number is encoded as a part of the address,
704 * data is set to 0.
705 * For MSI, the vector number is encoded in least bits in data.
706 */
707 static void spapr_msi_write(void *opaque, hwaddr addr,
708 uint64_t data, unsigned size)
709 {
710 uint32_t irq = data;
711
712 trace_spapr_pci_msi_write(addr, data, irq);
713
714 qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));
715 }
716
717 static const MemoryRegionOps spapr_msi_ops = {
718 /* There is no .read as the read result is undefined by PCI spec */
719 .read = NULL,
720 .write = spapr_msi_write,
721 .endianness = DEVICE_LITTLE_ENDIAN
722 };
723
724 /*
725 * PHB PCI device
726 */
727 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
728 {
729 sPAPRPHBState *phb = opaque;
730
731 return &phb->iommu_as;
732 }
733
734 static void spapr_phb_realize(DeviceState *dev, Error **errp)
735 {
736 SysBusDevice *s = SYS_BUS_DEVICE(dev);
737 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
738 PCIHostState *phb = PCI_HOST_BRIDGE(s);
739 sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s);
740 char *namebuf;
741 int i;
742 PCIBus *bus;
743 uint64_t msi_window_size = 4096;
744
745 if (sphb->index != -1) {
746 hwaddr windows_base;
747
748 if ((sphb->buid != -1) || (sphb->dma_liobn != -1)
749 || (sphb->mem_win_addr != -1)
750 || (sphb->io_win_addr != -1)) {
751 error_setg(errp, "Either \"index\" or other parameters must"
752 " be specified for PAPR PHB, not both");
753 return;
754 }
755
756 if (sphb->index > SPAPR_PCI_MAX_INDEX) {
757 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
758 SPAPR_PCI_MAX_INDEX);
759 return;
760 }
761
762 sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index;
763 sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN + sphb->index;
764
765 windows_base = SPAPR_PCI_WINDOW_BASE
766 + sphb->index * SPAPR_PCI_WINDOW_SPACING;
767 sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF;
768 sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF;
769 }
770
771 if (sphb->buid == -1) {
772 error_setg(errp, "BUID not specified for PHB");
773 return;
774 }
775
776 if (sphb->dma_liobn == -1) {
777 error_setg(errp, "LIOBN not specified for PHB");
778 return;
779 }
780
781 if (sphb->mem_win_addr == -1) {
782 error_setg(errp, "Memory window address not specified for PHB");
783 return;
784 }
785
786 if (sphb->io_win_addr == -1) {
787 error_setg(errp, "IO window address not specified for PHB");
788 return;
789 }
790
791 if (find_phb(spapr, sphb->buid)) {
792 error_setg(errp, "PCI host bridges must have unique BUIDs");
793 return;
794 }
795
796 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
797
798 namebuf = alloca(strlen(sphb->dtbusname) + 32);
799
800 /* Initialize memory regions */
801 sprintf(namebuf, "%s.mmio", sphb->dtbusname);
802 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
803
804 sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname);
805 memory_region_init_alias(&sphb->memwindow, OBJECT(sphb),
806 namebuf, &sphb->memspace,
807 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
808 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
809 &sphb->memwindow);
810
811 /* Initialize IO regions */
812 sprintf(namebuf, "%s.io", sphb->dtbusname);
813 memory_region_init(&sphb->iospace, OBJECT(sphb),
814 namebuf, SPAPR_PCI_IO_WIN_SIZE);
815
816 sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
817 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
818 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
819 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
820 &sphb->iowindow);
821
822 bus = pci_register_bus(dev, NULL,
823 pci_spapr_set_irq, pci_spapr_map_irq, sphb,
824 &sphb->memspace, &sphb->iospace,
825 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
826 phb->bus = bus;
827
828 /*
829 * Initialize PHB address space.
830 * By default there will be at least one subregion for default
831 * 32bit DMA window.
832 * Later the guest might want to create another DMA window
833 * which will become another memory subregion.
834 */
835 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname);
836
837 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
838 namebuf, UINT64_MAX);
839 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
840 sphb->dtbusname);
841
842 /*
843 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
844 * we need to allocate some memory to catch those writes coming
845 * from msi_notify()/msix_notify().
846 * As MSIMessage:addr is going to be the same and MSIMessage:data
847 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
848 * be used.
849 *
850 * For KVM we want to ensure that this memory is a full page so that
851 * our memory slot is of page size granularity.
852 */
853 #ifdef CONFIG_KVM
854 if (kvm_enabled()) {
855 msi_window_size = getpagesize();
856 }
857 #endif
858
859 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr,
860 "msi", msi_window_size);
861 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
862 &sphb->msiwindow);
863
864 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
865
866 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
867
868 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
869
870 /* Initialize the LSI table */
871 for (i = 0; i < PCI_NUM_PINS; i++) {
872 uint32_t irq;
873
874 irq = xics_alloc_block(spapr->icp, 0, 1, true, false);
875 if (!irq) {
876 error_setg(errp, "spapr_allocate_lsi failed");
877 return;
878 }
879
880 sphb->lsi_table[i].irq = irq;
881 }
882
883 if (!info->finish_realize) {
884 error_setg(errp, "finish_realize not defined");
885 return;
886 }
887
888 info->finish_realize(sphb, errp);
889
890 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
891 }
892
893 static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp)
894 {
895 sPAPRTCETable *tcet;
896
897 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn,
898 0,
899 SPAPR_TCE_PAGE_SHIFT,
900 0x40000000 >> SPAPR_TCE_PAGE_SHIFT, false);
901 if (!tcet) {
902 error_setg(errp, "Unable to create TCE table for %s",
903 sphb->dtbusname);
904 return ;
905 }
906
907 /* Register default 32bit DMA window */
908 memory_region_add_subregion(&sphb->iommu_root, 0,
909 spapr_tce_get_iommu(tcet));
910 }
911
912 static int spapr_phb_children_reset(Object *child, void *opaque)
913 {
914 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
915
916 if (dev) {
917 device_reset(dev);
918 }
919
920 return 0;
921 }
922
923 static void spapr_phb_reset(DeviceState *qdev)
924 {
925 /* Reset the IOMMU state */
926 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
927 }
928
929 static Property spapr_phb_properties[] = {
930 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1),
931 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1),
932 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1),
933 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1),
934 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size,
935 SPAPR_PCI_MMIO_WIN_SIZE),
936 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1),
937 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size,
938 SPAPR_PCI_IO_WIN_SIZE),
939 DEFINE_PROP_END_OF_LIST(),
940 };
941
942 static const VMStateDescription vmstate_spapr_pci_lsi = {
943 .name = "spapr_pci/lsi",
944 .version_id = 1,
945 .minimum_version_id = 1,
946 .fields = (VMStateField[]) {
947 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi),
948
949 VMSTATE_END_OF_LIST()
950 },
951 };
952
953 static const VMStateDescription vmstate_spapr_pci_msi = {
954 .name = "spapr_pci/msi",
955 .version_id = 1,
956 .minimum_version_id = 1,
957 .fields = (VMStateField []) {
958 VMSTATE_UINT32(key, spapr_pci_msi_mig),
959 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
960 VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
961 VMSTATE_END_OF_LIST()
962 },
963 };
964
965 static void spapr_pci_fill_msi_devs(gpointer key, gpointer value,
966 gpointer opaque)
967 {
968 sPAPRPHBState *sphb = opaque;
969
970 sphb->msi_devs[sphb->msi_devs_num].key = *(uint32_t *)key;
971 sphb->msi_devs[sphb->msi_devs_num].value = *(spapr_pci_msi *)value;
972 sphb->msi_devs_num++;
973 }
974
975 static void spapr_pci_pre_save(void *opaque)
976 {
977 sPAPRPHBState *sphb = opaque;
978 int msi_devs_num;
979
980 if (sphb->msi_devs) {
981 g_free(sphb->msi_devs);
982 sphb->msi_devs = NULL;
983 }
984 sphb->msi_devs_num = 0;
985 msi_devs_num = g_hash_table_size(sphb->msi);
986 if (!msi_devs_num) {
987 return;
988 }
989 sphb->msi_devs = g_malloc(msi_devs_num * sizeof(spapr_pci_msi_mig));
990
991 g_hash_table_foreach(sphb->msi, spapr_pci_fill_msi_devs, sphb);
992 assert(sphb->msi_devs_num == msi_devs_num);
993 }
994
995 static int spapr_pci_post_load(void *opaque, int version_id)
996 {
997 sPAPRPHBState *sphb = opaque;
998 gpointer key, value;
999 int i;
1000
1001 for (i = 0; i < sphb->msi_devs_num; ++i) {
1002 key = g_memdup(&sphb->msi_devs[i].key,
1003 sizeof(sphb->msi_devs[i].key));
1004 value = g_memdup(&sphb->msi_devs[i].value,
1005 sizeof(sphb->msi_devs[i].value));
1006 g_hash_table_insert(sphb->msi, key, value);
1007 }
1008 if (sphb->msi_devs) {
1009 g_free(sphb->msi_devs);
1010 sphb->msi_devs = NULL;
1011 }
1012 sphb->msi_devs_num = 0;
1013
1014 return 0;
1015 }
1016
1017 static const VMStateDescription vmstate_spapr_pci = {
1018 .name = "spapr_pci",
1019 .version_id = 2,
1020 .minimum_version_id = 2,
1021 .pre_save = spapr_pci_pre_save,
1022 .post_load = spapr_pci_post_load,
1023 .fields = (VMStateField[]) {
1024 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState),
1025 VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState),
1026 VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState),
1027 VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState),
1028 VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState),
1029 VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState),
1030 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
1031 vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
1032 VMSTATE_INT32(msi_devs_num, sPAPRPHBState),
1033 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0,
1034 vmstate_spapr_pci_msi, spapr_pci_msi_mig),
1035 VMSTATE_END_OF_LIST()
1036 },
1037 };
1038
1039 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
1040 PCIBus *rootbus)
1041 {
1042 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
1043
1044 return sphb->dtbusname;
1045 }
1046
1047 static void spapr_phb_class_init(ObjectClass *klass, void *data)
1048 {
1049 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1050 DeviceClass *dc = DEVICE_CLASS(klass);
1051 sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass);
1052
1053 hc->root_bus_path = spapr_phb_root_bus_path;
1054 dc->realize = spapr_phb_realize;
1055 dc->props = spapr_phb_properties;
1056 dc->reset = spapr_phb_reset;
1057 dc->vmsd = &vmstate_spapr_pci;
1058 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1059 dc->cannot_instantiate_with_device_add_yet = false;
1060 spc->finish_realize = spapr_phb_finish_realize;
1061 }
1062
1063 static const TypeInfo spapr_phb_info = {
1064 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
1065 .parent = TYPE_PCI_HOST_BRIDGE,
1066 .instance_size = sizeof(sPAPRPHBState),
1067 .class_init = spapr_phb_class_init,
1068 .class_size = sizeof(sPAPRPHBClass),
1069 };
1070
1071 PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index)
1072 {
1073 DeviceState *dev;
1074
1075 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
1076 qdev_prop_set_uint32(dev, "index", index);
1077 qdev_init_nofail(dev);
1078
1079 return PCI_HOST_BRIDGE(dev);
1080 }
1081
1082 /* Macros to operate with address in OF binding to PCI */
1083 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
1084 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
1085 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
1086 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
1087 #define b_ss(x) b_x((x), 24, 2) /* the space code */
1088 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
1089 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
1090 #define b_fff(x) b_x((x), 8, 3) /* function number */
1091 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
1092
1093 typedef struct sPAPRTCEDT {
1094 void *fdt;
1095 int node_off;
1096 } sPAPRTCEDT;
1097
1098 static int spapr_phb_children_dt(Object *child, void *opaque)
1099 {
1100 sPAPRTCEDT *p = opaque;
1101 sPAPRTCETable *tcet;
1102
1103 tcet = (sPAPRTCETable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE);
1104 if (!tcet) {
1105 return 0;
1106 }
1107
1108 spapr_dma_dt(p->fdt, p->node_off, "ibm,dma-window",
1109 tcet->liobn, tcet->bus_offset,
1110 tcet->nb_table << tcet->page_shift);
1111 /* Stop after the first window */
1112
1113 return 1;
1114 }
1115
1116 int spapr_populate_pci_dt(sPAPRPHBState *phb,
1117 uint32_t xics_phandle,
1118 void *fdt)
1119 {
1120 int bus_off, i, j;
1121 char nodename[256];
1122 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
1123 const uint64_t mmiosize = memory_region_size(&phb->memwindow);
1124 const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET;
1125 const uint64_t w32size = MIN(w32max, mmiosize);
1126 const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0;
1127 struct {
1128 uint32_t hi;
1129 uint64_t child;
1130 uint64_t parent;
1131 uint64_t size;
1132 } QEMU_PACKED ranges[] = {
1133 {
1134 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
1135 cpu_to_be64(phb->io_win_addr),
1136 cpu_to_be64(memory_region_size(&phb->iospace)),
1137 },
1138 {
1139 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
1140 cpu_to_be64(phb->mem_win_addr),
1141 cpu_to_be64(w32size),
1142 },
1143 {
1144 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32),
1145 cpu_to_be64(phb->mem_win_addr + w32size),
1146 cpu_to_be64(w64size)
1147 },
1148 };
1149 const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]);
1150 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
1151 uint32_t interrupt_map_mask[] = {
1152 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
1153 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
1154
1155 /* Start populating the FDT */
1156 sprintf(nodename, "pci@%" PRIx64, phb->buid);
1157 bus_off = fdt_add_subnode(fdt, 0, nodename);
1158 if (bus_off < 0) {
1159 return bus_off;
1160 }
1161
1162 #define _FDT(exp) \
1163 do { \
1164 int ret = (exp); \
1165 if (ret < 0) { \
1166 return ret; \
1167 } \
1168 } while (0)
1169
1170 /* Write PHB properties */
1171 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
1172 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
1173 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
1174 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
1175 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
1176 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
1177 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
1178 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
1179 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
1180 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
1181 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS));
1182
1183 /* Build the interrupt-map, this must matches what is done
1184 * in pci_spapr_map_irq
1185 */
1186 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
1187 &interrupt_map_mask, sizeof(interrupt_map_mask)));
1188 for (i = 0; i < PCI_SLOT_MAX; i++) {
1189 for (j = 0; j < PCI_NUM_PINS; j++) {
1190 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
1191 int lsi_num = pci_spapr_swizzle(i, j);
1192
1193 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
1194 irqmap[1] = 0;
1195 irqmap[2] = 0;
1196 irqmap[3] = cpu_to_be32(j+1);
1197 irqmap[4] = cpu_to_be32(xics_phandle);
1198 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
1199 irqmap[6] = cpu_to_be32(0x8);
1200 }
1201 }
1202 /* Write interrupt map */
1203 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
1204 sizeof(interrupt_map)));
1205
1206 object_child_foreach(OBJECT(phb), spapr_phb_children_dt,
1207 &((sPAPRTCEDT){ .fdt = fdt, .node_off = bus_off }));
1208
1209 return 0;
1210 }
1211
1212 void spapr_pci_rtas_init(void)
1213 {
1214 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
1215 rtas_read_pci_config);
1216 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
1217 rtas_write_pci_config);
1218 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
1219 rtas_ibm_read_pci_config);
1220 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
1221 rtas_ibm_write_pci_config);
1222 if (msi_supported) {
1223 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
1224 "ibm,query-interrupt-source-number",
1225 rtas_ibm_query_interrupt_source_number);
1226 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
1227 rtas_ibm_change_msi);
1228 }
1229
1230 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
1231 "ibm,set-eeh-option",
1232 rtas_ibm_set_eeh_option);
1233 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
1234 "ibm,get-config-addr-info2",
1235 rtas_ibm_get_config_addr_info2);
1236 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
1237 "ibm,read-slot-reset-state2",
1238 rtas_ibm_read_slot_reset_state2);
1239 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
1240 "ibm,set-slot-reset",
1241 rtas_ibm_set_slot_reset);
1242 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
1243 "ibm,configure-pe",
1244 rtas_ibm_configure_pe);
1245 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
1246 "ibm,slot-error-detail",
1247 rtas_ibm_slot_error_detail);
1248 }
1249
1250 static void spapr_pci_register_types(void)
1251 {
1252 type_register_static(&spapr_phb_info);
1253 }
1254
1255 type_init(spapr_pci_register_types)
1256
1257 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
1258 {
1259 bool be = *(bool *)opaque;
1260
1261 if (object_dynamic_cast(OBJECT(dev), "VGA")
1262 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
1263 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
1264 &error_abort);
1265 }
1266 return 0;
1267 }
1268
1269 void spapr_pci_switch_vga(bool big_endian)
1270 {
1271 sPAPRPHBState *sphb;
1272
1273 /*
1274 * For backward compatibility with existing guests, we switch
1275 * the endianness of the VGA controller when changing the guest
1276 * interrupt mode
1277 */
1278 QLIST_FOREACH(sphb, &spapr->phbs, list) {
1279 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
1280 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
1281 &big_endian);
1282 }
1283 }
QEMU Monitor Protocol