cputlb.c

   1 /*
   2  *  Common CPU TLB handling
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "config.h"
  21 #include "cpu.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/memory.h"
  24 #include "exec/address-spaces.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 #include "exec/cputlb.h"
  28
  29 #include "exec/memory-internal.h"
  30 #include "exec/ram_addr.h"
  31 #include "tcg/tcg.h"
  32
  33 //#define DEBUG_TLB
  34 //#define DEBUG_TLB_CHECK
  35
  36 /* statistics */
  37 int tlb_flush_count;
  38
  39 /* NOTE:
  40  * If flush_global is true (the usual case), flush all tlb entries.
  41  * If flush_global is false, flush (at least) all tlb entries not
  42  * marked global.
  43  *
  44  * Since QEMU doesn't currently implement a global/not-global flag
  45  * for tlb entries, at the moment tlb_flush() will also flush all
  46  * tlb entries in the flush_global == false case. This is OK because
  47  * CPU architectures generally permit an implementation to drop
  48  * entries from the TLB at any time, so flushing more entries than
  49  * required is only an efficiency issue, not a correctness issue.
  50  */
  51 void tlb_flush(CPUState *cpu, int flush_global)
  52 {
  53     CPUArchState *env = cpu->env_ptr;
  54
  55 #if defined(DEBUG_TLB)
  56     printf("tlb_flush:\n");
  57 #endif
  58     /* must reset current TB so that interrupts cannot modify the
  59        links while we are modifying them */
  60     cpu->current_tb = NULL;
  61
  62     memset(env->tlb_table, -1, sizeof(env->tlb_table));
  63     memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
  64     memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
  65
  66     env->vtlb_index = 0;
  67     env->tlb_flush_addr = -1;
  68     env->tlb_flush_mask = 0;
  69     tlb_flush_count++;
  70 }
  71
  72 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
  73 {
  74     if (addr == (tlb_entry->addr_read &
  75                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
  76         addr == (tlb_entry->addr_write &
  77                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
  78         addr == (tlb_entry->addr_code &
  79                  (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
  80         memset(tlb_entry, -1, sizeof(*tlb_entry));
  81     }
  82 }
  83
  84 void tlb_flush_page(CPUState *cpu, target_ulong addr)
  85 {
  86     CPUArchState *env = cpu->env_ptr;
  87     int i;
  88     int mmu_idx;
  89
  90 #if defined(DEBUG_TLB)
  91     printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
  92 #endif
  93     /* Check if we need to flush due to large pages.  */
  94     if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
  95 #if defined(DEBUG_TLB)
  96         printf("tlb_flush_page: forced full flush ("
  97                TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
  98                env->tlb_flush_addr, env->tlb_flush_mask);
  99 #endif
 100         tlb_flush(cpu, 1);
 101         return;
 102     }
 103     /* must reset current TB so that interrupts cannot modify the
 104        links while we are modifying them */
 105     cpu->current_tb = NULL;
 106
 107     addr &= TARGET_PAGE_MASK;
 108     i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 109     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 110         tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
 111     }
 112
 113     /* check whether there are entries that need to be flushed in the vtlb */
 114     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 115         int k;
 116         for (k = 0; k < CPU_VTLB_SIZE; k++) {
 117             tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
 118         }
 119     }
 120
 121     tb_flush_jmp_cache(cpu, addr);
 122 }
 123
 124 /* update the TLBs so that writes to code in the virtual page 'addr'
 125    can be detected */
 126 void tlb_protect_code(ram_addr_t ram_addr)
 127 {
 128     cpu_physical_memory_reset_dirty(ram_addr, TARGET_PAGE_SIZE,
 129                                     DIRTY_MEMORY_CODE);
 130 }
 131
 132 /* update the TLB so that writes in physical page 'phys_addr' are no longer
 133    tested for self modifying code */
 134 void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
 135                              target_ulong vaddr)
 136 {
 137     cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
 138 }
 139
 140 static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
 141 {
 142     return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
 143 }
 144
 145 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
 146                            uintptr_t length)
 147 {
 148     uintptr_t addr;
 149
 150     if (tlb_is_dirty_ram(tlb_entry)) {
 151         addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
 152         if ((addr - start) < length) {
 153             tlb_entry->addr_write |= TLB_NOTDIRTY;
 154         }
 155     }
 156 }
 157
 158 static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
 159 {
 160     ram_addr_t ram_addr;
 161
 162     if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
 163         fprintf(stderr, "Bad ram pointer %p\n", ptr);
 164         abort();
 165     }
 166     return ram_addr;
 167 }
 168
 169 void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
 170 {
 171     CPUState *cpu;
 172     CPUArchState *env;
 173
 174     CPU_FOREACH(cpu) {
 175         int mmu_idx;
 176
 177         env = cpu->env_ptr;
 178         for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 179             unsigned int i;
 180
 181             for (i = 0; i < CPU_TLB_SIZE; i++) {
 182                 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
 183                                       start1, length);
 184             }
 185
 186             for (i = 0; i < CPU_VTLB_SIZE; i++) {
 187                 tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
 188                                       start1, length);
 189             }
 190         }
 191     }
 192 }
 193
 194 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
 195 {
 196     if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
 197         tlb_entry->addr_write = vaddr;
 198     }
 199 }
 200
 201 /* update the TLB corresponding to virtual page vaddr
 202    so that it is no longer dirty */
 203 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
 204 {
 205     int i;
 206     int mmu_idx;
 207
 208     vaddr &= TARGET_PAGE_MASK;
 209     i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 210     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 211         tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
 212     }
 213
 214     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 215         int k;
 216         for (k = 0; k < CPU_VTLB_SIZE; k++) {
 217             tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr);
 218         }
 219     }
 220 }
 221
 222 /* Our TLB does not support large pages, so remember the area covered by
 223    large pages and trigger a full TLB flush if these are invalidated.  */
 224 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
 225                                target_ulong size)
 226 {
 227     target_ulong mask = ~(size - 1);
 228
 229     if (env->tlb_flush_addr == (target_ulong)-1) {
 230         env->tlb_flush_addr = vaddr & mask;
 231         env->tlb_flush_mask = mask;
 232         return;
 233     }
 234     /* Extend the existing region to include the new page.
 235        This is a compromise between unnecessary flushes and the cost
 236        of maintaining a full variable size TLB.  */
 237     mask &= env->tlb_flush_mask;
 238     while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
 239         mask <<= 1;
 240     }
 241     env->tlb_flush_addr &= mask;
 242     env->tlb_flush_mask = mask;
 243 }
 244
 245 /* Add a new TLB entry. At most one entry for a given virtual address
 246  * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
 247  * supplied size is only used by tlb_flush_page.
 248  *
 249  * Called from TCG-generated code, which is under an RCU read-side
 250  * critical section.
 251  */
 252 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 253                   hwaddr paddr, int prot,
 254                   int mmu_idx, target_ulong size)
 255 {
 256     CPUArchState *env = cpu->env_ptr;
 257     MemoryRegionSection *section;
 258     unsigned int index;
 259     target_ulong address;
 260     target_ulong code_address;
 261     uintptr_t addend;
 262     CPUTLBEntry *te;
 263     hwaddr iotlb, xlat, sz;
 264     unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
 265
 266     assert(size >= TARGET_PAGE_SIZE);
 267     if (size != TARGET_PAGE_SIZE) {
 268         tlb_add_large_page(env, vaddr, size);
 269     }
 270
 271     sz = size;
 272     section = address_space_translate_for_iotlb(cpu, paddr, &xlat, &sz);
 273     assert(sz >= TARGET_PAGE_SIZE);
 274
 275 #if defined(DEBUG_TLB)
 276     qemu_log_mask(CPU_LOG_MMU,
 277            "tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
 278            " prot=%x idx=%d\n",
 279            vaddr, paddr, prot, mmu_idx);
 280 #endif
 281
 282     address = vaddr;
 283     if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
 284         /* IO memory case */
 285         address |= TLB_MMIO;
 286         addend = 0;
 287     } else {
 288         /* TLB_MMIO for rom/romd handled below */
 289         addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
 290     }
 291
 292     code_address = address;
 293     iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
 294                                             prot, &address);
 295
 296     index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 297     te = &env->tlb_table[mmu_idx][index];
 298
 299     /* do not discard the translation in te, evict it into a victim tlb */
 300     env->tlb_v_table[mmu_idx][vidx] = *te;
 301     env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
 302
 303     /* refill the tlb */
 304     env->iotlb[mmu_idx][index] = iotlb - vaddr;
 305     te->addend = addend - vaddr;
 306     if (prot & PAGE_READ) {
 307         te->addr_read = address;
 308     } else {
 309         te->addr_read = -1;
 310     }
 311
 312     if (prot & PAGE_EXEC) {
 313         te->addr_code = code_address;
 314     } else {
 315         te->addr_code = -1;
 316     }
 317     if (prot & PAGE_WRITE) {
 318         if ((memory_region_is_ram(section->mr) && section->readonly)
 319             || memory_region_is_romd(section->mr)) {
 320             /* Write access calls the I/O callback.  */
 321             te->addr_write = address | TLB_MMIO;
 322         } else if (memory_region_is_ram(section->mr)
 323                    && cpu_physical_memory_is_clean(section->mr->ram_addr
 324                                                    + xlat)) {
 325             te->addr_write = address | TLB_NOTDIRTY;
 326         } else {
 327             te->addr_write = address;
 328         }
 329     } else {
 330         te->addr_write = -1;
 331     }
 332 }
 333
 334 /* NOTE: this function can trigger an exception */
 335 /* NOTE2: the returned address is not exactly the physical address: it
 336  * is actually a ram_addr_t (in system mode; the user mode emulation
 337  * version of this function returns a guest virtual address).
 338  */
 339 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 340 {
 341     int mmu_idx, page_index, pd;
 342     void *p;
 343     MemoryRegion *mr;
 344     CPUState *cpu = ENV_GET_CPU(env1);
 345
 346     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 347     mmu_idx = cpu_mmu_index(env1);
 348     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 349                  (addr & TARGET_PAGE_MASK))) {
 350         cpu_ldub_code(env1, addr);
 351     }
 352     pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
 353     mr = iotlb_to_region(cpu, pd);
 354     if (memory_region_is_unassigned(mr)) {
 355         CPUClass *cc = CPU_GET_CLASS(cpu);
 356
 357         if (cc->do_unassigned_access) {
 358             cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
 359         } else {
 360             cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
 361                       TARGET_FMT_lx "\n", addr);
 362         }
 363     }
 364     p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
 365     return qemu_ram_addr_from_host_nofail(p);
 366 }
 367
 368 #define MMUSUFFIX _mmu
 369
 370 #define SHIFT 0
 371 #include "softmmu_template.h"
 372
 373 #define SHIFT 1
 374 #include "softmmu_template.h"
 375
 376 #define SHIFT 2
 377 #include "softmmu_template.h"
 378
 379 #define SHIFT 3
 380 #include "softmmu_template.h"
 381 #undef MMUSUFFIX
 382
 383 #define MMUSUFFIX _cmmu
 384 #undef GETPC_ADJ
 385 #define GETPC_ADJ 0
 386 #undef GETRA
 387 #define GETRA() ((uintptr_t)0)
 388 #define SOFTMMU_CODE_ACCESS
 389
 390 #define SHIFT 0
 391 #include "softmmu_template.h"
 392
 393 #define SHIFT 1
 394 #include "softmmu_template.h"
 395
 396 #define SHIFT 2
 397 #include "softmmu_template.h"
 398
 399 #define SHIFT 3
 400 #include "softmmu_template.h"