target-arm: convert check_ap to ap_to_rw_prot
[qemu/qmp-unstable.git] / target-sparc / mmu_helper.c
blob2a0c6f0d3de3affa3651046ace3accdd448e97a1
1 /*
2 * Sparc MMU helpers
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "cpu.h"
21 #include "trace.h"
22 #include "exec/address-spaces.h"
24 /* Sparc MMU emulation */
26 #if defined(CONFIG_USER_ONLY)
28 int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
29 int mmu_idx)
31 if (rw & 2) {
32 cs->exception_index = TT_TFAULT;
33 } else {
34 cs->exception_index = TT_DFAULT;
36 return 1;
39 #else
41 #ifndef TARGET_SPARC64
43 * Sparc V8 Reference MMU (SRMMU)
45 static const int access_table[8][8] = {
46 { 0, 0, 0, 0, 8, 0, 12, 12 },
47 { 0, 0, 0, 0, 8, 0, 0, 0 },
48 { 8, 8, 0, 0, 0, 8, 12, 12 },
49 { 8, 8, 0, 0, 0, 8, 0, 0 },
50 { 8, 0, 8, 0, 8, 8, 12, 12 },
51 { 8, 0, 8, 0, 8, 0, 8, 0 },
52 { 8, 8, 8, 0, 8, 8, 12, 12 },
53 { 8, 8, 8, 0, 8, 8, 8, 0 }
56 static const int perm_table[2][8] = {
58 PAGE_READ,
59 PAGE_READ | PAGE_WRITE,
60 PAGE_READ | PAGE_EXEC,
61 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
62 PAGE_EXEC,
63 PAGE_READ | PAGE_WRITE,
64 PAGE_READ | PAGE_EXEC,
65 PAGE_READ | PAGE_WRITE | PAGE_EXEC
68 PAGE_READ,
69 PAGE_READ | PAGE_WRITE,
70 PAGE_READ | PAGE_EXEC,
71 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
72 PAGE_EXEC,
73 PAGE_READ,
79 static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
80 int *prot, int *access_index,
81 target_ulong address, int rw, int mmu_idx,
82 target_ulong *page_size)
84 int access_perms = 0;
85 hwaddr pde_ptr;
86 uint32_t pde;
87 int error_code = 0, is_dirty, is_user;
88 unsigned long page_offset;
89 CPUState *cs = CPU(sparc_env_get_cpu(env));
91 is_user = mmu_idx == MMU_USER_IDX;
93 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
94 *page_size = TARGET_PAGE_SIZE;
95 /* Boot mode: instruction fetches are taken from PROM */
96 if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
97 *physical = env->prom_addr | (address & 0x7ffffULL);
98 *prot = PAGE_READ | PAGE_EXEC;
99 return 0;
101 *physical = address;
102 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
103 return 0;
106 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
107 *physical = 0xffffffffffff0000ULL;
109 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
110 /* Context base + context number */
111 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
112 pde = ldl_phys(cs->as, pde_ptr);
114 /* Ctx pde */
115 switch (pde & PTE_ENTRYTYPE_MASK) {
116 default:
117 case 0: /* Invalid */
118 return 1 << 2;
119 case 2: /* L0 PTE, maybe should not happen? */
120 case 3: /* Reserved */
121 return 4 << 2;
122 case 1: /* L0 PDE */
123 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
124 pde = ldl_phys(cs->as, pde_ptr);
126 switch (pde & PTE_ENTRYTYPE_MASK) {
127 default:
128 case 0: /* Invalid */
129 return (1 << 8) | (1 << 2);
130 case 3: /* Reserved */
131 return (1 << 8) | (4 << 2);
132 case 1: /* L1 PDE */
133 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
134 pde = ldl_phys(cs->as, pde_ptr);
136 switch (pde & PTE_ENTRYTYPE_MASK) {
137 default:
138 case 0: /* Invalid */
139 return (2 << 8) | (1 << 2);
140 case 3: /* Reserved */
141 return (2 << 8) | (4 << 2);
142 case 1: /* L2 PDE */
143 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
144 pde = ldl_phys(cs->as, pde_ptr);
146 switch (pde & PTE_ENTRYTYPE_MASK) {
147 default:
148 case 0: /* Invalid */
149 return (3 << 8) | (1 << 2);
150 case 1: /* PDE, should not happen */
151 case 3: /* Reserved */
152 return (3 << 8) | (4 << 2);
153 case 2: /* L3 PTE */
154 page_offset = 0;
156 *page_size = TARGET_PAGE_SIZE;
157 break;
158 case 2: /* L2 PTE */
159 page_offset = address & 0x3f000;
160 *page_size = 0x40000;
162 break;
163 case 2: /* L1 PTE */
164 page_offset = address & 0xfff000;
165 *page_size = 0x1000000;
169 /* check access */
170 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
171 error_code = access_table[*access_index][access_perms];
172 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) {
173 return error_code;
176 /* update page modified and dirty bits */
177 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
178 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
179 pde |= PG_ACCESSED_MASK;
180 if (is_dirty) {
181 pde |= PG_MODIFIED_MASK;
183 stl_phys_notdirty(cs->as, pde_ptr, pde);
186 /* the page can be put in the TLB */
187 *prot = perm_table[is_user][access_perms];
188 if (!(pde & PG_MODIFIED_MASK)) {
189 /* only set write access if already dirty... otherwise wait
190 for dirty access */
191 *prot &= ~PAGE_WRITE;
194 /* Even if large ptes, we map only one 4KB page in the cache to
195 avoid filling it too fast */
196 *physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
197 return error_code;
200 /* Perform address translation */
201 int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
202 int mmu_idx)
204 SPARCCPU *cpu = SPARC_CPU(cs);
205 CPUSPARCState *env = &cpu->env;
206 hwaddr paddr;
207 target_ulong vaddr;
208 target_ulong page_size;
209 int error_code = 0, prot, access_index;
211 address &= TARGET_PAGE_MASK;
212 error_code = get_physical_address(env, &paddr, &prot, &access_index,
213 address, rw, mmu_idx, &page_size);
214 vaddr = address;
215 if (error_code == 0) {
216 qemu_log_mask(CPU_LOG_MMU,
217 "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
218 TARGET_FMT_lx "\n", address, paddr, vaddr);
219 tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
220 return 0;
223 if (env->mmuregs[3]) { /* Fault status register */
224 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
226 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
227 env->mmuregs[4] = address; /* Fault address register */
229 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
230 /* No fault mode: if a mapping is available, just override
231 permissions. If no mapping is available, redirect accesses to
232 neverland. Fake/overridden mappings will be flushed when
233 switching to normal mode. */
234 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
235 tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
236 return 0;
237 } else {
238 if (rw & 2) {
239 cs->exception_index = TT_TFAULT;
240 } else {
241 cs->exception_index = TT_DFAULT;
243 return 1;
247 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
249 CPUState *cs = CPU(sparc_env_get_cpu(env));
250 hwaddr pde_ptr;
251 uint32_t pde;
253 /* Context base + context number */
254 pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
255 (env->mmuregs[2] << 2);
256 pde = ldl_phys(cs->as, pde_ptr);
258 switch (pde & PTE_ENTRYTYPE_MASK) {
259 default:
260 case 0: /* Invalid */
261 case 2: /* PTE, maybe should not happen? */
262 case 3: /* Reserved */
263 return 0;
264 case 1: /* L1 PDE */
265 if (mmulev == 3) {
266 return pde;
268 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
269 pde = ldl_phys(cs->as, pde_ptr);
271 switch (pde & PTE_ENTRYTYPE_MASK) {
272 default:
273 case 0: /* Invalid */
274 case 3: /* Reserved */
275 return 0;
276 case 2: /* L1 PTE */
277 return pde;
278 case 1: /* L2 PDE */
279 if (mmulev == 2) {
280 return pde;
282 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
283 pde = ldl_phys(cs->as, pde_ptr);
285 switch (pde & PTE_ENTRYTYPE_MASK) {
286 default:
287 case 0: /* Invalid */
288 case 3: /* Reserved */
289 return 0;
290 case 2: /* L2 PTE */
291 return pde;
292 case 1: /* L3 PDE */
293 if (mmulev == 1) {
294 return pde;
296 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
297 pde = ldl_phys(cs->as, pde_ptr);
299 switch (pde & PTE_ENTRYTYPE_MASK) {
300 default:
301 case 0: /* Invalid */
302 case 1: /* PDE, should not happen */
303 case 3: /* Reserved */
304 return 0;
305 case 2: /* L3 PTE */
306 return pde;
311 return 0;
314 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
316 CPUState *cs = CPU(sparc_env_get_cpu(env));
317 target_ulong va, va1, va2;
318 unsigned int n, m, o;
319 hwaddr pde_ptr, pa;
320 uint32_t pde;
322 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
323 pde = ldl_phys(cs->as, pde_ptr);
324 (*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
325 (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
326 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
327 pde = mmu_probe(env, va, 2);
328 if (pde) {
329 pa = cpu_get_phys_page_debug(cs, va);
330 (*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
331 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
332 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
333 pde = mmu_probe(env, va1, 1);
334 if (pde) {
335 pa = cpu_get_phys_page_debug(cs, va1);
336 (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
337 TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
338 va1, pa, pde);
339 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
340 pde = mmu_probe(env, va2, 0);
341 if (pde) {
342 pa = cpu_get_phys_page_debug(cs, va2);
343 (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
344 TARGET_FMT_plx " PTE: "
345 TARGET_FMT_lx "\n",
346 va2, pa, pde);
355 /* Gdb expects all registers windows to be flushed in ram. This function handles
356 * reads (and only reads) in stack frames as if windows were flushed. We assume
357 * that the sparc ABI is followed.
359 int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
360 uint8_t *buf, int len, bool is_write)
362 SPARCCPU *cpu = SPARC_CPU(cs);
363 CPUSPARCState *env = &cpu->env;
364 target_ulong addr = address;
365 int i;
366 int len1;
367 int cwp = env->cwp;
369 if (!is_write) {
370 for (i = 0; i < env->nwindows; i++) {
371 int off;
372 target_ulong fp = env->regbase[cwp * 16 + 22];
374 /* Assume fp == 0 means end of frame. */
375 if (fp == 0) {
376 break;
379 cwp = cpu_cwp_inc(env, cwp + 1);
381 /* Invalid window ? */
382 if (env->wim & (1 << cwp)) {
383 break;
386 /* According to the ABI, the stack is growing downward. */
387 if (addr + len < fp) {
388 break;
391 /* Not in this frame. */
392 if (addr > fp + 64) {
393 continue;
396 /* Handle access before this window. */
397 if (addr < fp) {
398 len1 = fp - addr;
399 if (cpu_memory_rw_debug(cs, addr, buf, len1, is_write) != 0) {
400 return -1;
402 addr += len1;
403 len -= len1;
404 buf += len1;
407 /* Access byte per byte to registers. Not very efficient but speed
408 * is not critical.
410 off = addr - fp;
411 len1 = 64 - off;
413 if (len1 > len) {
414 len1 = len;
417 for (; len1; len1--) {
418 int reg = cwp * 16 + 8 + (off >> 2);
419 union {
420 uint32_t v;
421 uint8_t c[4];
422 } u;
423 u.v = cpu_to_be32(env->regbase[reg]);
424 *buf++ = u.c[off & 3];
425 addr++;
426 len--;
427 off++;
430 if (len == 0) {
431 return 0;
435 return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
438 #else /* !TARGET_SPARC64 */
440 /* 41 bit physical address space */
441 static inline hwaddr ultrasparc_truncate_physical(uint64_t x)
443 return x & 0x1ffffffffffULL;
447 * UltraSparc IIi I/DMMUs
450 /* Returns true if TTE tag is valid and matches virtual address value
451 in context requires virtual address mask value calculated from TTE
452 entry size */
453 static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
454 uint64_t address, uint64_t context,
455 hwaddr *physical)
457 uint64_t mask;
459 switch (TTE_PGSIZE(tlb->tte)) {
460 default:
461 case 0x0: /* 8k */
462 mask = 0xffffffffffffe000ULL;
463 break;
464 case 0x1: /* 64k */
465 mask = 0xffffffffffff0000ULL;
466 break;
467 case 0x2: /* 512k */
468 mask = 0xfffffffffff80000ULL;
469 break;
470 case 0x3: /* 4M */
471 mask = 0xffffffffffc00000ULL;
472 break;
475 /* valid, context match, virtual address match? */
476 if (TTE_IS_VALID(tlb->tte) &&
477 (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context))
478 && compare_masked(address, tlb->tag, mask)) {
479 /* decode physical address */
480 *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
481 return 1;
484 return 0;
487 static int get_physical_address_data(CPUSPARCState *env,
488 hwaddr *physical, int *prot,
489 target_ulong address, int rw, int mmu_idx)
491 CPUState *cs = CPU(sparc_env_get_cpu(env));
492 unsigned int i;
493 uint64_t context;
494 uint64_t sfsr = 0;
496 int is_user = (mmu_idx == MMU_USER_IDX ||
497 mmu_idx == MMU_USER_SECONDARY_IDX);
499 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
500 *physical = ultrasparc_truncate_physical(address);
501 *prot = PAGE_READ | PAGE_WRITE;
502 return 0;
505 switch (mmu_idx) {
506 case MMU_USER_IDX:
507 case MMU_KERNEL_IDX:
508 context = env->dmmu.mmu_primary_context & 0x1fff;
509 sfsr |= SFSR_CT_PRIMARY;
510 break;
511 case MMU_USER_SECONDARY_IDX:
512 case MMU_KERNEL_SECONDARY_IDX:
513 context = env->dmmu.mmu_secondary_context & 0x1fff;
514 sfsr |= SFSR_CT_SECONDARY;
515 break;
516 case MMU_NUCLEUS_IDX:
517 sfsr |= SFSR_CT_NUCLEUS;
518 /* FALLTHRU */
519 default:
520 context = 0;
521 break;
524 if (rw == 1) {
525 sfsr |= SFSR_WRITE_BIT;
526 } else if (rw == 4) {
527 sfsr |= SFSR_NF_BIT;
530 for (i = 0; i < 64; i++) {
531 /* ctx match, vaddr match, valid? */
532 if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
533 int do_fault = 0;
535 /* access ok? */
536 /* multiple bits in SFSR.FT may be set on TT_DFAULT */
537 if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
538 do_fault = 1;
539 sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
540 trace_mmu_helper_dfault(address, context, mmu_idx, env->tl);
542 if (rw == 4) {
543 if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
544 do_fault = 1;
545 sfsr |= SFSR_FT_NF_E_BIT;
547 } else {
548 if (TTE_IS_NFO(env->dtlb[i].tte)) {
549 do_fault = 1;
550 sfsr |= SFSR_FT_NFO_BIT;
554 if (do_fault) {
555 /* faults above are reported with TT_DFAULT. */
556 cs->exception_index = TT_DFAULT;
557 } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
558 do_fault = 1;
559 cs->exception_index = TT_DPROT;
561 trace_mmu_helper_dprot(address, context, mmu_idx, env->tl);
564 if (!do_fault) {
565 *prot = PAGE_READ;
566 if (TTE_IS_W_OK(env->dtlb[i].tte)) {
567 *prot |= PAGE_WRITE;
570 TTE_SET_USED(env->dtlb[i].tte);
572 return 0;
575 if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
576 sfsr |= SFSR_OW_BIT; /* overflow (not read before
577 another fault) */
580 if (env->pstate & PS_PRIV) {
581 sfsr |= SFSR_PR_BIT;
584 /* FIXME: ASI field in SFSR must be set */
585 env->dmmu.sfsr = sfsr | SFSR_VALID_BIT;
587 env->dmmu.sfar = address; /* Fault address register */
589 env->dmmu.tag_access = (address & ~0x1fffULL) | context;
591 return 1;
595 trace_mmu_helper_dmiss(address, context);
598 * On MMU misses:
599 * - UltraSPARC IIi: SFSR and SFAR unmodified
600 * - JPS1: SFAR updated and some fields of SFSR updated
602 env->dmmu.tag_access = (address & ~0x1fffULL) | context;
603 cs->exception_index = TT_DMISS;
604 return 1;
607 static int get_physical_address_code(CPUSPARCState *env,
608 hwaddr *physical, int *prot,
609 target_ulong address, int mmu_idx)
611 CPUState *cs = CPU(sparc_env_get_cpu(env));
612 unsigned int i;
613 uint64_t context;
615 int is_user = (mmu_idx == MMU_USER_IDX ||
616 mmu_idx == MMU_USER_SECONDARY_IDX);
618 if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
619 /* IMMU disabled */
620 *physical = ultrasparc_truncate_physical(address);
621 *prot = PAGE_EXEC;
622 return 0;
625 if (env->tl == 0) {
626 /* PRIMARY context */
627 context = env->dmmu.mmu_primary_context & 0x1fff;
628 } else {
629 /* NUCLEUS context */
630 context = 0;
633 for (i = 0; i < 64; i++) {
634 /* ctx match, vaddr match, valid? */
635 if (ultrasparc_tag_match(&env->itlb[i],
636 address, context, physical)) {
637 /* access ok? */
638 if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
639 /* Fault status register */
640 if (env->immu.sfsr & SFSR_VALID_BIT) {
641 env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
642 another fault) */
643 } else {
644 env->immu.sfsr = 0;
646 if (env->pstate & PS_PRIV) {
647 env->immu.sfsr |= SFSR_PR_BIT;
649 if (env->tl > 0) {
650 env->immu.sfsr |= SFSR_CT_NUCLEUS;
653 /* FIXME: ASI field in SFSR must be set */
654 env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
655 cs->exception_index = TT_TFAULT;
657 env->immu.tag_access = (address & ~0x1fffULL) | context;
659 trace_mmu_helper_tfault(address, context);
661 return 1;
663 *prot = PAGE_EXEC;
664 TTE_SET_USED(env->itlb[i].tte);
665 return 0;
669 trace_mmu_helper_tmiss(address, context);
671 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
672 env->immu.tag_access = (address & ~0x1fffULL) | context;
673 cs->exception_index = TT_TMISS;
674 return 1;
677 static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
678 int *prot, int *access_index,
679 target_ulong address, int rw, int mmu_idx,
680 target_ulong *page_size)
682 /* ??? We treat everything as a small page, then explicitly flush
683 everything when an entry is evicted. */
684 *page_size = TARGET_PAGE_SIZE;
686 /* safety net to catch wrong softmmu index use from dynamic code */
687 if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
688 if (rw == 2) {
689 trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx,
690 env->dmmu.mmu_primary_context,
691 env->dmmu.mmu_secondary_context,
692 address);
693 } else {
694 trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx,
695 env->dmmu.mmu_primary_context,
696 env->dmmu.mmu_secondary_context,
697 address);
701 if (rw == 2) {
702 return get_physical_address_code(env, physical, prot, address,
703 mmu_idx);
704 } else {
705 return get_physical_address_data(env, physical, prot, address, rw,
706 mmu_idx);
710 /* Perform address translation */
711 int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
712 int mmu_idx)
714 SPARCCPU *cpu = SPARC_CPU(cs);
715 CPUSPARCState *env = &cpu->env;
716 target_ulong vaddr;
717 hwaddr paddr;
718 target_ulong page_size;
719 int error_code = 0, prot, access_index;
721 address &= TARGET_PAGE_MASK;
722 error_code = get_physical_address(env, &paddr, &prot, &access_index,
723 address, rw, mmu_idx, &page_size);
724 if (error_code == 0) {
725 vaddr = address;
727 trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
728 env->dmmu.mmu_primary_context,
729 env->dmmu.mmu_secondary_context);
731 tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
732 return 0;
734 /* XXX */
735 return 1;
738 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
740 unsigned int i;
741 const char *mask;
743 (*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %"
744 PRId64 "\n",
745 env->dmmu.mmu_primary_context,
746 env->dmmu.mmu_secondary_context);
747 if ((env->lsu & DMMU_E) == 0) {
748 (*cpu_fprintf)(f, "DMMU disabled\n");
749 } else {
750 (*cpu_fprintf)(f, "DMMU dump\n");
751 for (i = 0; i < 64; i++) {
752 switch (TTE_PGSIZE(env->dtlb[i].tte)) {
753 default:
754 case 0x0:
755 mask = " 8k";
756 break;
757 case 0x1:
758 mask = " 64k";
759 break;
760 case 0x2:
761 mask = "512k";
762 break;
763 case 0x3:
764 mask = " 4M";
765 break;
767 if (TTE_IS_VALID(env->dtlb[i].tte)) {
768 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
769 ", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
771 env->dtlb[i].tag & (uint64_t)~0x1fffULL,
772 TTE_PA(env->dtlb[i].tte),
773 mask,
774 TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
775 TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
776 TTE_IS_LOCKED(env->dtlb[i].tte) ?
777 "locked" : "unlocked",
778 env->dtlb[i].tag & (uint64_t)0x1fffULL,
779 TTE_IS_GLOBAL(env->dtlb[i].tte) ?
780 "global" : "local");
784 if ((env->lsu & IMMU_E) == 0) {
785 (*cpu_fprintf)(f, "IMMU disabled\n");
786 } else {
787 (*cpu_fprintf)(f, "IMMU dump\n");
788 for (i = 0; i < 64; i++) {
789 switch (TTE_PGSIZE(env->itlb[i].tte)) {
790 default:
791 case 0x0:
792 mask = " 8k";
793 break;
794 case 0x1:
795 mask = " 64k";
796 break;
797 case 0x2:
798 mask = "512k";
799 break;
800 case 0x3:
801 mask = " 4M";
802 break;
804 if (TTE_IS_VALID(env->itlb[i].tte)) {
805 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
806 ", %s, %s, %s, ctx %" PRId64 " %s\n",
808 env->itlb[i].tag & (uint64_t)~0x1fffULL,
809 TTE_PA(env->itlb[i].tte),
810 mask,
811 TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
812 TTE_IS_LOCKED(env->itlb[i].tte) ?
813 "locked" : "unlocked",
814 env->itlb[i].tag & (uint64_t)0x1fffULL,
815 TTE_IS_GLOBAL(env->itlb[i].tte) ?
816 "global" : "local");
822 #endif /* TARGET_SPARC64 */
824 static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
825 target_ulong addr, int rw, int mmu_idx)
827 target_ulong page_size;
828 int prot, access_index;
830 return get_physical_address(env, phys, &prot, &access_index, addr, rw,
831 mmu_idx, &page_size);
834 #if defined(TARGET_SPARC64)
835 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
836 int mmu_idx)
838 hwaddr phys_addr;
840 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
841 return -1;
843 return phys_addr;
845 #endif
847 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
849 SPARCCPU *cpu = SPARC_CPU(cs);
850 CPUSPARCState *env = &cpu->env;
851 hwaddr phys_addr;
852 int mmu_idx = cpu_mmu_index(env);
853 MemoryRegionSection section;
855 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
856 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
857 return -1;
860 section = memory_region_find(get_system_memory(), phys_addr, 1);
861 memory_region_unref(section.mr);
862 if (!int128_nz(section.size)) {
863 return -1;
865 return phys_addr;
867 #endif