?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
milkymist: convert to memory API
[qemu/qmp-unstable.git] / hw / ppc405_boards.c
blob1eb807c4c1b9b5838b2434da4aac38c2a8e82781
1 /*
2 * QEMU PowerPC 405 evaluation boards emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "nvram.h"
28 #include "flash.h"
29 #include "sysemu.h"
30 #include "block.h"
31 #include "boards.h"
32 #include "qemu-log.h"
33 #include "loader.h"
34 #include "blockdev.h"
35 #include "exec-memory.h"
36
37 #define BIOS_FILENAME "ppc405_rom.bin"
38 #define BIOS_SIZE (2048 * 1024)
39
40 #define KERNEL_LOAD_ADDR 0x00000000
41 #define INITRD_LOAD_ADDR 0x01800000
42
43 #define USE_FLASH_BIOS
44
45 #define DEBUG_BOARD_INIT
46
47 /*****************************************************************************/
48 /* PPC405EP reference board (IBM) */
49 /* Standalone board with:
50 * - PowerPC 405EP CPU
51 * - SDRAM (0x00000000)
52 * - Flash (0xFFF80000)
53 * - SRAM (0xFFF00000)
54 * - NVRAM (0xF0000000)
55 * - FPGA (0xF0300000)
56 */
57 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
58 struct ref405ep_fpga_t {
59 uint8_t reg0;
60 uint8_t reg1;
61 };
62
63 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
64 {
65 ref405ep_fpga_t *fpga;
66 uint32_t ret;
67
68 fpga = opaque;
69 switch (addr) {
70 case 0x0:
71 ret = fpga->reg0;
72 break;
73 case 0x1:
74 ret = fpga->reg1;
75 break;
76 default:
77 ret = 0;
78 break;
79 }
80
81 return ret;
82 }
83
84 static void ref405ep_fpga_writeb (void *opaque,
85 target_phys_addr_t addr, uint32_t value)
86 {
87 ref405ep_fpga_t *fpga;
88
89 fpga = opaque;
90 switch (addr) {
91 case 0x0:
92 /* Read only */
93 break;
94 case 0x1:
95 fpga->reg1 = value;
96 break;
97 default:
98 break;
99 }
100 }
101
102 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
103 {
104 uint32_t ret;
105
106 ret = ref405ep_fpga_readb(opaque, addr) << 8;
107 ret |= ref405ep_fpga_readb(opaque, addr + 1);
108
109 return ret;
110 }
111
112 static void ref405ep_fpga_writew (void *opaque,
113 target_phys_addr_t addr, uint32_t value)
114 {
115 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
116 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
117 }
118
119 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
120 {
121 uint32_t ret;
122
123 ret = ref405ep_fpga_readb(opaque, addr) << 24;
124 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
125 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
126 ret |= ref405ep_fpga_readb(opaque, addr + 3);
127
128 return ret;
129 }
130
131 static void ref405ep_fpga_writel (void *opaque,
132 target_phys_addr_t addr, uint32_t value)
133 {
134 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
135 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
136 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
137 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
138 }
139
140 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
141 &ref405ep_fpga_readb,
142 &ref405ep_fpga_readw,
143 &ref405ep_fpga_readl,
144 };
145
146 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
147 &ref405ep_fpga_writeb,
148 &ref405ep_fpga_writew,
149 &ref405ep_fpga_writel,
150 };
151
152 static void ref405ep_fpga_reset (void *opaque)
153 {
154 ref405ep_fpga_t *fpga;
155
156 fpga = opaque;
157 fpga->reg0 = 0x00;
158 fpga->reg1 = 0x0F;
159 }
160
161 static void ref405ep_fpga_init (uint32_t base)
162 {
163 ref405ep_fpga_t *fpga;
164 int fpga_memory;
165
166 fpga = g_malloc0(sizeof(ref405ep_fpga_t));
167 fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
168 ref405ep_fpga_write, fpga,
169 DEVICE_NATIVE_ENDIAN);
170 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
171 qemu_register_reset(&ref405ep_fpga_reset, fpga);
172 }
173
174 static void ref405ep_init (ram_addr_t ram_size,
175 const char *boot_device,
176 const char *kernel_filename,
177 const char *kernel_cmdline,
178 const char *initrd_filename,
179 const char *cpu_model)
180 {
181 char *filename;
182 ppc4xx_bd_info_t bd;
183 CPUPPCState *env;
184 qemu_irq *pic;
185 ram_addr_t sram_offset, bdloc;
186 MemoryRegion *address_space_mem = get_system_memory();
187 MemoryRegion *bios = g_new(MemoryRegion, 1);
188 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
189 target_phys_addr_t ram_bases[2], ram_sizes[2];
190 target_ulong sram_size;
191 long bios_size;
192 //int phy_addr = 0;
193 //static int phy_addr = 1;
194 target_ulong kernel_base, initrd_base;
195 long kernel_size, initrd_size;
196 int linux_boot;
197 int fl_idx, fl_sectors, len;
198 DriveInfo *dinfo;
199
200 /* XXX: fix this */
201 memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
202 ram_bases[0] = 0;
203 ram_sizes[0] = 0x08000000;
204 memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
205 ram_bases[1] = 0x00000000;
206 ram_sizes[1] = 0x00000000;
207 ram_size = 128 * 1024 * 1024;
208 #ifdef DEBUG_BOARD_INIT
209 printf("%s: register cpu\n", __func__);
210 #endif
211 env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
212 kernel_filename == NULL ? 0 : 1);
213 /* allocate SRAM */
214 sram_size = 512 * 1024;
215 sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
216 #ifdef DEBUG_BOARD_INIT
217 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
218 #endif
219 cpu_register_physical_memory(0xFFF00000, sram_size,
220 sram_offset | IO_MEM_RAM);
221 /* allocate and load BIOS */
222 #ifdef DEBUG_BOARD_INIT
223 printf("%s: register BIOS\n", __func__);
224 #endif
225 fl_idx = 0;
226 #ifdef USE_FLASH_BIOS
227 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
228 if (dinfo) {
229 bios_size = bdrv_getlength(dinfo->bdrv);
230 memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
231 NULL, "ef405ep.bios", bios_size);
232 fl_sectors = (bios_size + 65535) >> 16;
233 #ifdef DEBUG_BOARD_INIT
234 printf("Register parallel flash %d size %lx"
235 " at addr %lx '%s' %d\n",
236 fl_idx, bios_size, -bios_size,
237 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
238 #endif
239 pflash_cfi02_register((uint32_t)(-bios_size), bios,
240 dinfo->bdrv, 65536, fl_sectors, 1,
241 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
242 fl_idx++;
243 } else
244 #endif
245 {
246 #ifdef DEBUG_BOARD_INIT
247 printf("Load BIOS from file\n");
248 #endif
249 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
250 if (bios_name == NULL)
251 bios_name = BIOS_FILENAME;
252 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
253 if (filename) {
254 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
255 g_free(filename);
256 } else {
257 bios_size = -1;
258 }
259 if (bios_size < 0 || bios_size > BIOS_SIZE) {
260 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
261 bios_name);
262 exit(1);
263 }
264 bios_size = (bios_size + 0xfff) & ~0xfff;
265 memory_region_set_readonly(bios, true);
266 memory_region_add_subregion(address_space_mem, (uint32_t)(-bios_size),
267 bios);
268 }
269 /* Register FPGA */
270 #ifdef DEBUG_BOARD_INIT
271 printf("%s: register FPGA\n", __func__);
272 #endif
273 ref405ep_fpga_init(0xF0300000);
274 /* Register NVRAM */
275 #ifdef DEBUG_BOARD_INIT
276 printf("%s: register NVRAM\n", __func__);
277 #endif
278 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
279 /* Load kernel */
280 linux_boot = (kernel_filename != NULL);
281 if (linux_boot) {
282 #ifdef DEBUG_BOARD_INIT
283 printf("%s: load kernel\n", __func__);
284 #endif
285 memset(&bd, 0, sizeof(bd));
286 bd.bi_memstart = 0x00000000;
287 bd.bi_memsize = ram_size;
288 bd.bi_flashstart = -bios_size;
289 bd.bi_flashsize = -bios_size;
290 bd.bi_flashoffset = 0;
291 bd.bi_sramstart = 0xFFF00000;
292 bd.bi_sramsize = sram_size;
293 bd.bi_bootflags = 0;
294 bd.bi_intfreq = 133333333;
295 bd.bi_busfreq = 33333333;
296 bd.bi_baudrate = 115200;
297 bd.bi_s_version[0] = 'Q';
298 bd.bi_s_version[1] = 'M';
299 bd.bi_s_version[2] = 'U';
300 bd.bi_s_version[3] = '\0';
301 bd.bi_r_version[0] = 'Q';
302 bd.bi_r_version[1] = 'E';
303 bd.bi_r_version[2] = 'M';
304 bd.bi_r_version[3] = 'U';
305 bd.bi_r_version[4] = '\0';
306 bd.bi_procfreq = 133333333;
307 bd.bi_plb_busfreq = 33333333;
308 bd.bi_pci_busfreq = 33333333;
309 bd.bi_opbfreq = 33333333;
310 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
311 env->gpr[3] = bdloc;
312 kernel_base = KERNEL_LOAD_ADDR;
313 /* now we can load the kernel */
314 kernel_size = load_image_targphys(kernel_filename, kernel_base,
315 ram_size - kernel_base);
316 if (kernel_size < 0) {
317 fprintf(stderr, "qemu: could not load kernel '%s'\n",
318 kernel_filename);
319 exit(1);
320 }
321 printf("Load kernel size %ld at " TARGET_FMT_lx,
322 kernel_size, kernel_base);
323 /* load initrd */
324 if (initrd_filename) {
325 initrd_base = INITRD_LOAD_ADDR;
326 initrd_size = load_image_targphys(initrd_filename, initrd_base,
327 ram_size - initrd_base);
328 if (initrd_size < 0) {
329 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
330 initrd_filename);
331 exit(1);
332 }
333 } else {
334 initrd_base = 0;
335 initrd_size = 0;
336 }
337 env->gpr[4] = initrd_base;
338 env->gpr[5] = initrd_size;
339 if (kernel_cmdline != NULL) {
340 len = strlen(kernel_cmdline);
341 bdloc -= ((len + 255) & ~255);
342 cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
343 env->gpr[6] = bdloc;
344 env->gpr[7] = bdloc + len;
345 } else {
346 env->gpr[6] = 0;
347 env->gpr[7] = 0;
348 }
349 env->nip = KERNEL_LOAD_ADDR;
350 } else {
351 kernel_base = 0;
352 kernel_size = 0;
353 initrd_base = 0;
354 initrd_size = 0;
355 bdloc = 0;
356 }
357 #ifdef DEBUG_BOARD_INIT
358 printf("%s: Done\n", __func__);
359 #endif
360 printf("bdloc %016lx\n", (unsigned long)bdloc);
361 }
362
363 static QEMUMachine ref405ep_machine = {
364 .name = "ref405ep",
365 .desc = "ref405ep",
366 .init = ref405ep_init,
367 };
368
369 /*****************************************************************************/
370 /* AMCC Taihu evaluation board */
371 /* - PowerPC 405EP processor
372 * - SDRAM 128 MB at 0x00000000
373 * - Boot flash 2 MB at 0xFFE00000
374 * - Application flash 32 MB at 0xFC000000
375 * - 2 serial ports
376 * - 2 ethernet PHY
377 * - 1 USB 1.1 device 0x50000000
378 * - 1 LCD display 0x50100000
379 * - 1 CPLD 0x50100000
380 * - 1 I2C EEPROM
381 * - 1 I2C thermal sensor
382 * - a set of LEDs
383 * - bit-bang SPI port using GPIOs
384 * - 1 EBC interface connector 0 0x50200000
385 * - 1 cardbus controller + expansion slot.
386 * - 1 PCI expansion slot.
387 */
388 typedef struct taihu_cpld_t taihu_cpld_t;
389 struct taihu_cpld_t {
390 uint8_t reg0;
391 uint8_t reg1;
392 };
393
394 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
395 {
396 taihu_cpld_t *cpld;
397 uint32_t ret;
398
399 cpld = opaque;
400 switch (addr) {
401 case 0x0:
402 ret = cpld->reg0;
403 break;
404 case 0x1:
405 ret = cpld->reg1;
406 break;
407 default:
408 ret = 0;
409 break;
410 }
411
412 return ret;
413 }
414
415 static void taihu_cpld_writeb (void *opaque,
416 target_phys_addr_t addr, uint32_t value)
417 {
418 taihu_cpld_t *cpld;
419
420 cpld = opaque;
421 switch (addr) {
422 case 0x0:
423 /* Read only */
424 break;
425 case 0x1:
426 cpld->reg1 = value;
427 break;
428 default:
429 break;
430 }
431 }
432
433 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
434 {
435 uint32_t ret;
436
437 ret = taihu_cpld_readb(opaque, addr) << 8;
438 ret |= taihu_cpld_readb(opaque, addr + 1);
439
440 return ret;
441 }
442
443 static void taihu_cpld_writew (void *opaque,
444 target_phys_addr_t addr, uint32_t value)
445 {
446 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
447 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
448 }
449
450 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
451 {
452 uint32_t ret;
453
454 ret = taihu_cpld_readb(opaque, addr) << 24;
455 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
456 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
457 ret |= taihu_cpld_readb(opaque, addr + 3);
458
459 return ret;
460 }
461
462 static void taihu_cpld_writel (void *opaque,
463 target_phys_addr_t addr, uint32_t value)
464 {
465 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
466 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
467 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
468 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
469 }
470
471 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
472 &taihu_cpld_readb,
473 &taihu_cpld_readw,
474 &taihu_cpld_readl,
475 };
476
477 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
478 &taihu_cpld_writeb,
479 &taihu_cpld_writew,
480 &taihu_cpld_writel,
481 };
482
483 static void taihu_cpld_reset (void *opaque)
484 {
485 taihu_cpld_t *cpld;
486
487 cpld = opaque;
488 cpld->reg0 = 0x01;
489 cpld->reg1 = 0x80;
490 }
491
492 static void taihu_cpld_init (uint32_t base)
493 {
494 taihu_cpld_t *cpld;
495 int cpld_memory;
496
497 cpld = g_malloc0(sizeof(taihu_cpld_t));
498 cpld_memory = cpu_register_io_memory(taihu_cpld_read,
499 taihu_cpld_write, cpld,
500 DEVICE_NATIVE_ENDIAN);
501 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
502 qemu_register_reset(&taihu_cpld_reset, cpld);
503 }
504
505 static void taihu_405ep_init(ram_addr_t ram_size,
506 const char *boot_device,
507 const char *kernel_filename,
508 const char *kernel_cmdline,
509 const char *initrd_filename,
510 const char *cpu_model)
511 {
512 char *filename;
513 qemu_irq *pic;
514 MemoryRegion *address_space_mem = get_system_memory();
515 MemoryRegion *bios = g_new(MemoryRegion, 1);
516 MemoryRegion *flash = g_new(MemoryRegion, 1);
517 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
518 target_phys_addr_t ram_bases[2], ram_sizes[2];
519 long bios_size;
520 target_ulong kernel_base, initrd_base;
521 long kernel_size, initrd_size;
522 int linux_boot;
523 int fl_idx, fl_sectors;
524 DriveInfo *dinfo;
525
526 /* RAM is soldered to the board so the size cannot be changed */
527 memory_region_init_ram(&ram_memories[0], NULL,
528 "taihu_405ep.ram-0", 0x04000000);
529 ram_bases[0] = 0;
530 ram_sizes[0] = 0x04000000;
531 memory_region_init_ram(&ram_memories[1], NULL,
532 "taihu_405ep.ram-1", 0x04000000);
533 ram_bases[1] = 0x04000000;
534 ram_sizes[1] = 0x04000000;
535 ram_size = 0x08000000;
536 #ifdef DEBUG_BOARD_INIT
537 printf("%s: register cpu\n", __func__);
538 #endif
539 ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
540 kernel_filename == NULL ? 0 : 1);
541 /* allocate and load BIOS */
542 #ifdef DEBUG_BOARD_INIT
543 printf("%s: register BIOS\n", __func__);
544 #endif
545 fl_idx = 0;
546 #if defined(USE_FLASH_BIOS)
547 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
548 if (dinfo) {
549 bios_size = bdrv_getlength(dinfo->bdrv);
550 /* XXX: should check that size is 2MB */
551 // bios_size = 2 * 1024 * 1024;
552 fl_sectors = (bios_size + 65535) >> 16;
553 memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
554 NULL, "taihu_405ep.bios", bios_size);
555 #ifdef DEBUG_BOARD_INIT
556 printf("Register parallel flash %d size %lx"
557 " at addr %lx '%s' %d\n",
558 fl_idx, bios_size, -bios_size,
559 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
560 #endif
561 pflash_cfi02_register((uint32_t)(-bios_size), bios,
562 dinfo->bdrv, 65536, fl_sectors, 1,
563 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
564 fl_idx++;
565 } else
566 #endif
567 {
568 #ifdef DEBUG_BOARD_INIT
569 printf("Load BIOS from file\n");
570 #endif
571 if (bios_name == NULL)
572 bios_name = BIOS_FILENAME;
573 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
574 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
575 if (filename) {
576 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
577 g_free(filename);
578 } else {
579 bios_size = -1;
580 }
581 if (bios_size < 0 || bios_size > BIOS_SIZE) {
582 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
583 bios_name);
584 exit(1);
585 }
586 bios_size = (bios_size + 0xfff) & ~0xfff;
587 memory_region_set_readonly(bios, true);
588 memory_region_add_subregion(address_space_mem,
589 (uint32_t)(-bios_size), bios);
590 }
591 /* Register Linux flash */
592 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
593 if (dinfo) {
594 bios_size = bdrv_getlength(dinfo->bdrv);
595 /* XXX: should check that size is 32MB */
596 bios_size = 32 * 1024 * 1024;
597 fl_sectors = (bios_size + 65535) >> 16;
598 #ifdef DEBUG_BOARD_INIT
599 printf("Register parallel flash %d size %lx"
600 " at addr " TARGET_FMT_lx " '%s'\n",
601 fl_idx, bios_size, (target_ulong)0xfc000000,
602 bdrv_get_device_name(dinfo->bdrv));
603 #endif
604 memory_region_init_rom_device(flash, &pflash_cfi02_ops_be,
605 NULL, "taihu_405ep.flash", bios_size);
606 pflash_cfi02_register(0xfc000000, flash,
607 dinfo->bdrv, 65536, fl_sectors, 1,
608 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
609 fl_idx++;
610 }
611 /* Register CLPD & LCD display */
612 #ifdef DEBUG_BOARD_INIT
613 printf("%s: register CPLD\n", __func__);
614 #endif
615 taihu_cpld_init(0x50100000);
616 /* Load kernel */
617 linux_boot = (kernel_filename != NULL);
618 if (linux_boot) {
619 #ifdef DEBUG_BOARD_INIT
620 printf("%s: load kernel\n", __func__);
621 #endif
622 kernel_base = KERNEL_LOAD_ADDR;
623 /* now we can load the kernel */
624 kernel_size = load_image_targphys(kernel_filename, kernel_base,
625 ram_size - kernel_base);
626 if (kernel_size < 0) {
627 fprintf(stderr, "qemu: could not load kernel '%s'\n",
628 kernel_filename);
629 exit(1);
630 }
631 /* load initrd */
632 if (initrd_filename) {
633 initrd_base = INITRD_LOAD_ADDR;
634 initrd_size = load_image_targphys(initrd_filename, initrd_base,
635 ram_size - initrd_base);
636 if (initrd_size < 0) {
637 fprintf(stderr,
638 "qemu: could not load initial ram disk '%s'\n",
639 initrd_filename);
640 exit(1);
641 }
642 } else {
643 initrd_base = 0;
644 initrd_size = 0;
645 }
646 } else {
647 kernel_base = 0;
648 kernel_size = 0;
649 initrd_base = 0;
650 initrd_size = 0;
651 }
652 #ifdef DEBUG_BOARD_INIT
653 printf("%s: Done\n", __func__);
654 #endif
655 }
656
657 static QEMUMachine taihu_machine = {
658 .name = "taihu",
659 .desc = "taihu",
660 .init = taihu_405ep_init,
661 };
662
663 static void ppc405_machine_init(void)
664 {
665 qemu_register_machine(&ref405ep_machine);
666 qemu_register_machine(&taihu_machine);
667 }
668
669 machine_init(ppc405_machine_init);
QEMU Monitor Protocol