target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_I386_H
  20 #define CPU_I386_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #define CPUState struct CPUX86State
  46
  47 #include "cpu-defs.h"
  48
  49 #include "softfloat.h"
  50
  51 #define R_EAX 0
  52 #define R_ECX 1
  53 #define R_EDX 2
  54 #define R_EBX 3
  55 #define R_ESP 4
  56 #define R_EBP 5
  57 #define R_ESI 6
  58 #define R_EDI 7
  59
  60 #define R_AL 0
  61 #define R_CL 1
  62 #define R_DL 2
  63 #define R_BL 3
  64 #define R_AH 4
  65 #define R_CH 5
  66 #define R_DH 6
  67 #define R_BH 7
  68
  69 #define R_ES 0
  70 #define R_CS 1
  71 #define R_SS 2
  72 #define R_DS 3
  73 #define R_FS 4
  74 #define R_GS 5
  75
  76 /* segment descriptor fields */
  77 #define DESC_G_MASK     (1 << 23)
  78 #define DESC_B_SHIFT    22
  79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  82 #define DESC_AVL_MASK   (1 << 20)
  83 #define DESC_P_MASK     (1 << 15)
  84 #define DESC_DPL_SHIFT  13
  85 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
  86 #define DESC_S_MASK     (1 << 12)
  87 #define DESC_TYPE_SHIFT 8
  88 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
  89 #define DESC_A_MASK     (1 << 8)
  90
  91 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  92 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  93 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  94
  95 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  96 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  97
  98 #define DESC_TSS_BUSY_MASK (1 << 9)
  99
 100 /* eflags masks */
 101 #define CC_C    0x0001
 102 #define CC_P    0x0004
 103 #define CC_A    0x0010
 104 #define CC_Z    0x0040
 105 #define CC_S    0x0080
 106 #define CC_O    0x0800
 107
 108 #define TF_SHIFT   8
 109 #define IOPL_SHIFT 12
 110 #define VM_SHIFT   17
 111
 112 #define TF_MASK                 0x00000100
 113 #define IF_MASK                 0x00000200
 114 #define DF_MASK                 0x00000400
 115 #define IOPL_MASK               0x00003000
 116 #define NT_MASK                 0x00004000
 117 #define RF_MASK                 0x00010000
 118 #define VM_MASK                 0x00020000
 119 #define AC_MASK                 0x00040000
 120 #define VIF_MASK                0x00080000
 121 #define VIP_MASK                0x00100000
 122 #define ID_MASK                 0x00200000
 123
 124 /* hidden flags - used internally by qemu to represent additional cpu
 125    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 126    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
 127    position to ease oring with eflags. */
 128 /* current cpl */
 129 #define HF_CPL_SHIFT         0
 130 /* true if soft mmu is being used */
 131 #define HF_SOFTMMU_SHIFT     2
 132 /* true if hardware interrupts must be disabled for next instruction */
 133 #define HF_INHIBIT_IRQ_SHIFT 3
 134 /* 16 or 32 segments */
 135 #define HF_CS32_SHIFT        4
 136 #define HF_SS32_SHIFT        5
 137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 138 #define HF_ADDSEG_SHIFT      6
 139 /* copy of CR0.PE (protected mode) */
 140 #define HF_PE_SHIFT          7
 141 #define HF_TF_SHIFT          8 /* must be same as eflags */
 142 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 143 #define HF_EM_SHIFT         10
 144 #define HF_TS_SHIFT         11
 145 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 146 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 147 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 148 #define HF_RF_SHIFT         16 /* must be same as eflags */
 149 #define HF_VM_SHIFT         17 /* must be same as eflags */
 150 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 151 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 152 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 153 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 154
 155 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 156 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 157 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 158 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 159 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 160 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 161 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 162 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 163 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 164 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 165 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 166 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 167 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 168 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 169 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
 170 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 171 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 172 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 173 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 174 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 175
 176 /* hflags2 */
 177
 178 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 179 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 180 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 181 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 182
 183 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 184 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 185 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 186 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 187
 188 #define CR0_PE_SHIFT 0
 189 #define CR0_MP_SHIFT 1
 190
 191 #define CR0_PE_MASK  (1 << 0)
 192 #define CR0_MP_MASK  (1 << 1)
 193 #define CR0_EM_MASK  (1 << 2)
 194 #define CR0_TS_MASK  (1 << 3)
 195 #define CR0_ET_MASK  (1 << 4)
 196 #define CR0_NE_MASK  (1 << 5)
 197 #define CR0_WP_MASK  (1 << 16)
 198 #define CR0_AM_MASK  (1 << 18)
 199 #define CR0_PG_MASK  (1 << 31)
 200
 201 #define CR4_VME_MASK  (1 << 0)
 202 #define CR4_PVI_MASK  (1 << 1)
 203 #define CR4_TSD_MASK  (1 << 2)
 204 #define CR4_DE_MASK   (1 << 3)
 205 #define CR4_PSE_MASK  (1 << 4)
 206 #define CR4_PAE_MASK  (1 << 5)
 207 #define CR4_MCE_MASK  (1 << 6)
 208 #define CR4_PGE_MASK  (1 << 7)
 209 #define CR4_PCE_MASK  (1 << 8)
 210 #define CR4_OSFXSR_SHIFT 9
 211 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 212 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 213
 214 #define DR6_BD          (1 << 13)
 215 #define DR6_BS          (1 << 14)
 216 #define DR6_BT          (1 << 15)
 217 #define DR6_FIXED_1     0xffff0ff0
 218
 219 #define DR7_GD          (1 << 13)
 220 #define DR7_TYPE_SHIFT  16
 221 #define DR7_LEN_SHIFT   18
 222 #define DR7_FIXED_1     0x00000400
 223
 224 #define PG_PRESENT_BIT  0
 225 #define PG_RW_BIT       1
 226 #define PG_USER_BIT     2
 227 #define PG_PWT_BIT      3
 228 #define PG_PCD_BIT      4
 229 #define PG_ACCESSED_BIT 5
 230 #define PG_DIRTY_BIT    6
 231 #define PG_PSE_BIT      7
 232 #define PG_GLOBAL_BIT   8
 233 #define PG_NX_BIT       63
 234
 235 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 236 #define PG_RW_MASK       (1 << PG_RW_BIT)
 237 #define PG_USER_MASK     (1 << PG_USER_BIT)
 238 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 239 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 240 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 241 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 242 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 243 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 244 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 245
 246 #define PG_ERROR_W_BIT     1
 247
 248 #define PG_ERROR_P_MASK    0x01
 249 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 250 #define PG_ERROR_U_MASK    0x04
 251 #define PG_ERROR_RSVD_MASK 0x08
 252 #define PG_ERROR_I_D_MASK  0x10
 253
 254 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
 255 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
 256
 257 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
 258 #define MCE_BANKS_DEF   10
 259
 260 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
 261 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
 262 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
 263
 264 #define MCI_STATUS_VAL  (1ULL<<63)  /* valid error */
 265 #define MCI_STATUS_OVER (1ULL<<62)  /* previous errors lost */
 266 #define MCI_STATUS_UC   (1ULL<<61)  /* uncorrected error */
 267 #define MCI_STATUS_EN   (1ULL<<60)  /* error enabled */
 268 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
 269 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
 270 #define MCI_STATUS_PCC  (1ULL<<57)  /* processor context corrupt */
 271 #define MCI_STATUS_S    (1ULL<<56)  /* Signaled machine check */
 272 #define MCI_STATUS_AR   (1ULL<<55)  /* Action required */
 273
 274 /* MISC register defines */
 275 #define MCM_ADDR_SEGOFF 0       /* segment offset */
 276 #define MCM_ADDR_LINEAR 1       /* linear address */
 277 #define MCM_ADDR_PHYS   2       /* physical address */
 278 #define MCM_ADDR_MEM    3       /* memory address */
 279 #define MCM_ADDR_GENERIC 7      /* generic */
 280
 281 #define MSR_IA32_TSC                    0x10
 282 #define MSR_IA32_APICBASE               0x1b
 283 #define MSR_IA32_APICBASE_BSP           (1<<8)
 284 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 285 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 286
 287 #define MSR_MTRRcap                     0xfe
 288 #define MSR_MTRRcap_VCNT                8
 289 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 290 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 291
 292 #define MSR_IA32_SYSENTER_CS            0x174
 293 #define MSR_IA32_SYSENTER_ESP           0x175
 294 #define MSR_IA32_SYSENTER_EIP           0x176
 295
 296 #define MSR_MCG_CAP                     0x179
 297 #define MSR_MCG_STATUS                  0x17a
 298 #define MSR_MCG_CTL                     0x17b
 299
 300 #define MSR_IA32_PERF_STATUS            0x198
 301
 302 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 303 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 304
 305 #define MSR_MTRRfix64K_00000            0x250
 306 #define MSR_MTRRfix16K_80000            0x258
 307 #define MSR_MTRRfix16K_A0000            0x259
 308 #define MSR_MTRRfix4K_C0000             0x268
 309 #define MSR_MTRRfix4K_C8000             0x269
 310 #define MSR_MTRRfix4K_D0000             0x26a
 311 #define MSR_MTRRfix4K_D8000             0x26b
 312 #define MSR_MTRRfix4K_E0000             0x26c
 313 #define MSR_MTRRfix4K_E8000             0x26d
 314 #define MSR_MTRRfix4K_F0000             0x26e
 315 #define MSR_MTRRfix4K_F8000             0x26f
 316
 317 #define MSR_PAT                         0x277
 318
 319 #define MSR_MTRRdefType                 0x2ff
 320
 321 #define MSR_MC0_CTL                     0x400
 322 #define MSR_MC0_STATUS                  0x401
 323 #define MSR_MC0_ADDR                    0x402
 324 #define MSR_MC0_MISC                    0x403
 325
 326 #define MSR_EFER                        0xc0000080
 327
 328 #define MSR_EFER_SCE   (1 << 0)
 329 #define MSR_EFER_LME   (1 << 8)
 330 #define MSR_EFER_LMA   (1 << 10)
 331 #define MSR_EFER_NXE   (1 << 11)
 332 #define MSR_EFER_SVME  (1 << 12)
 333 #define MSR_EFER_FFXSR (1 << 14)
 334
 335 #define MSR_STAR                        0xc0000081
 336 #define MSR_LSTAR                       0xc0000082
 337 #define MSR_CSTAR                       0xc0000083
 338 #define MSR_FMASK                       0xc0000084
 339 #define MSR_FSBASE                      0xc0000100
 340 #define MSR_GSBASE                      0xc0000101
 341 #define MSR_KERNELGSBASE                0xc0000102
 342 #define MSR_TSC_AUX                     0xc0000103
 343
 344 #define MSR_VM_HSAVE_PA                 0xc0010117
 345
 346 /* cpuid_features bits */
 347 #define CPUID_FP87 (1 << 0)
 348 #define CPUID_VME  (1 << 1)
 349 #define CPUID_DE   (1 << 2)
 350 #define CPUID_PSE  (1 << 3)
 351 #define CPUID_TSC  (1 << 4)
 352 #define CPUID_MSR  (1 << 5)
 353 #define CPUID_PAE  (1 << 6)
 354 #define CPUID_MCE  (1 << 7)
 355 #define CPUID_CX8  (1 << 8)
 356 #define CPUID_APIC (1 << 9)
 357 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 358 #define CPUID_MTRR (1 << 12)
 359 #define CPUID_PGE  (1 << 13)
 360 #define CPUID_MCA  (1 << 14)
 361 #define CPUID_CMOV (1 << 15)
 362 #define CPUID_PAT  (1 << 16)
 363 #define CPUID_PSE36   (1 << 17)
 364 #define CPUID_PN   (1 << 18)
 365 #define CPUID_CLFLUSH (1 << 19)
 366 #define CPUID_DTS (1 << 21)
 367 #define CPUID_ACPI (1 << 22)
 368 #define CPUID_MMX  (1 << 23)
 369 #define CPUID_FXSR (1 << 24)
 370 #define CPUID_SSE  (1 << 25)
 371 #define CPUID_SSE2 (1 << 26)
 372 #define CPUID_SS (1 << 27)
 373 #define CPUID_HT (1 << 28)
 374 #define CPUID_TM (1 << 29)
 375 #define CPUID_IA64 (1 << 30)
 376 #define CPUID_PBE (1 << 31)
 377
 378 #define CPUID_EXT_SSE3     (1 << 0)
 379 #define CPUID_EXT_DTES64   (1 << 2)
 380 #define CPUID_EXT_MONITOR  (1 << 3)
 381 #define CPUID_EXT_DSCPL    (1 << 4)
 382 #define CPUID_EXT_VMX      (1 << 5)
 383 #define CPUID_EXT_SMX      (1 << 6)
 384 #define CPUID_EXT_EST      (1 << 7)
 385 #define CPUID_EXT_TM2      (1 << 8)
 386 #define CPUID_EXT_SSSE3    (1 << 9)
 387 #define CPUID_EXT_CID      (1 << 10)
 388 #define CPUID_EXT_CX16     (1 << 13)
 389 #define CPUID_EXT_XTPR     (1 << 14)
 390 #define CPUID_EXT_PDCM     (1 << 15)
 391 #define CPUID_EXT_DCA      (1 << 18)
 392 #define CPUID_EXT_SSE41    (1 << 19)
 393 #define CPUID_EXT_SSE42    (1 << 20)
 394 #define CPUID_EXT_X2APIC   (1 << 21)
 395 #define CPUID_EXT_MOVBE    (1 << 22)
 396 #define CPUID_EXT_POPCNT   (1 << 23)
 397 #define CPUID_EXT_XSAVE    (1 << 26)
 398 #define CPUID_EXT_OSXSAVE  (1 << 27)
 399 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 400
 401 #define CPUID_EXT2_SYSCALL (1 << 11)
 402 #define CPUID_EXT2_MP      (1 << 19)
 403 #define CPUID_EXT2_NX      (1 << 20)
 404 #define CPUID_EXT2_MMXEXT  (1 << 22)
 405 #define CPUID_EXT2_FFXSR   (1 << 25)
 406 #define CPUID_EXT2_PDPE1GB (1 << 26)
 407 #define CPUID_EXT2_RDTSCP  (1 << 27)
 408 #define CPUID_EXT2_LM      (1 << 29)
 409 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 410 #define CPUID_EXT2_3DNOW   (1 << 31)
 411
 412 #define CPUID_EXT3_LAHF_LM (1 << 0)
 413 #define CPUID_EXT3_CMP_LEG (1 << 1)
 414 #define CPUID_EXT3_SVM     (1 << 2)
 415 #define CPUID_EXT3_EXTAPIC (1 << 3)
 416 #define CPUID_EXT3_CR8LEG  (1 << 4)
 417 #define CPUID_EXT3_ABM     (1 << 5)
 418 #define CPUID_EXT3_SSE4A   (1 << 6)
 419 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 420 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 421 #define CPUID_EXT3_OSVW    (1 << 9)
 422 #define CPUID_EXT3_IBS     (1 << 10)
 423 #define CPUID_EXT3_SKINIT  (1 << 12)
 424
 425 #define CPUID_SVM_NPT          (1 << 0)
 426 #define CPUID_SVM_LBRV         (1 << 1)
 427 #define CPUID_SVM_SVMLOCK      (1 << 2)
 428 #define CPUID_SVM_NRIPSAVE     (1 << 3)
 429 #define CPUID_SVM_TSCSCALE     (1 << 4)
 430 #define CPUID_SVM_VMCBCLEAN    (1 << 5)
 431 #define CPUID_SVM_FLUSHASID    (1 << 6)
 432 #define CPUID_SVM_DECODEASSIST (1 << 7)
 433 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 434 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 435
 436 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 437 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 438 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 439
 440 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 441 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 442 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 443
 444 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 445 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 446
 447 #define EXCP00_DIVZ     0
 448 #define EXCP01_DB       1
 449 #define EXCP02_NMI      2
 450 #define EXCP03_INT3     3
 451 #define EXCP04_INTO     4
 452 #define EXCP05_BOUND    5
 453 #define EXCP06_ILLOP    6
 454 #define EXCP07_PREX     7
 455 #define EXCP08_DBLE     8
 456 #define EXCP09_XERR     9
 457 #define EXCP0A_TSS      10
 458 #define EXCP0B_NOSEG    11
 459 #define EXCP0C_STACK    12
 460 #define EXCP0D_GPF      13
 461 #define EXCP0E_PAGE     14
 462 #define EXCP10_COPR     16
 463 #define EXCP11_ALGN     17
 464 #define EXCP12_MCHK     18
 465
 466 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 467                                  for syscall instruction */
 468
 469 enum {
 470     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 471     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 472
 473     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 474     CC_OP_MULW,
 475     CC_OP_MULL,
 476     CC_OP_MULQ,
 477
 478     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 479     CC_OP_ADDW,
 480     CC_OP_ADDL,
 481     CC_OP_ADDQ,
 482
 483     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 484     CC_OP_ADCW,
 485     CC_OP_ADCL,
 486     CC_OP_ADCQ,
 487
 488     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 489     CC_OP_SUBW,
 490     CC_OP_SUBL,
 491     CC_OP_SUBQ,
 492
 493     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 494     CC_OP_SBBW,
 495     CC_OP_SBBL,
 496     CC_OP_SBBQ,
 497
 498     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 499     CC_OP_LOGICW,
 500     CC_OP_LOGICL,
 501     CC_OP_LOGICQ,
 502
 503     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 504     CC_OP_INCW,
 505     CC_OP_INCL,
 506     CC_OP_INCQ,
 507
 508     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 509     CC_OP_DECW,
 510     CC_OP_DECL,
 511     CC_OP_DECQ,
 512
 513     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 514     CC_OP_SHLW,
 515     CC_OP_SHLL,
 516     CC_OP_SHLQ,
 517
 518     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 519     CC_OP_SARW,
 520     CC_OP_SARL,
 521     CC_OP_SARQ,
 522
 523     CC_OP_NB,
 524 };
 525
 526 #ifdef FLOATX80
 527 #define USE_X86LDOUBLE
 528 #endif
 529
 530 #ifdef USE_X86LDOUBLE
 531 typedef floatx80 CPU86_LDouble;
 532 #else
 533 typedef float64 CPU86_LDouble;
 534 #endif
 535
 536 typedef struct SegmentCache {
 537     uint32_t selector;
 538     target_ulong base;
 539     uint32_t limit;
 540     uint32_t flags;
 541 } SegmentCache;
 542
 543 typedef union {
 544     uint8_t _b[16];
 545     uint16_t _w[8];
 546     uint32_t _l[4];
 547     uint64_t _q[2];
 548     float32 _s[4];
 549     float64 _d[2];
 550 } XMMReg;
 551
 552 typedef union {
 553     uint8_t _b[8];
 554     uint16_t _w[4];
 555     uint32_t _l[2];
 556     float32 _s[2];
 557     uint64_t q;
 558 } MMXReg;
 559
 560 #ifdef HOST_WORDS_BIGENDIAN
 561 #define XMM_B(n) _b[15 - (n)]
 562 #define XMM_W(n) _w[7 - (n)]
 563 #define XMM_L(n) _l[3 - (n)]
 564 #define XMM_S(n) _s[3 - (n)]
 565 #define XMM_Q(n) _q[1 - (n)]
 566 #define XMM_D(n) _d[1 - (n)]
 567
 568 #define MMX_B(n) _b[7 - (n)]
 569 #define MMX_W(n) _w[3 - (n)]
 570 #define MMX_L(n) _l[1 - (n)]
 571 #define MMX_S(n) _s[1 - (n)]
 572 #else
 573 #define XMM_B(n) _b[n]
 574 #define XMM_W(n) _w[n]
 575 #define XMM_L(n) _l[n]
 576 #define XMM_S(n) _s[n]
 577 #define XMM_Q(n) _q[n]
 578 #define XMM_D(n) _d[n]
 579
 580 #define MMX_B(n) _b[n]
 581 #define MMX_W(n) _w[n]
 582 #define MMX_L(n) _l[n]
 583 #define MMX_S(n) _s[n]
 584 #endif
 585 #define MMX_Q(n) q
 586
 587 typedef union {
 588 #ifdef USE_X86LDOUBLE
 589     CPU86_LDouble d __attribute__((aligned(16)));
 590 #else
 591     CPU86_LDouble d;
 592 #endif
 593     MMXReg mmx;
 594 } FPReg;
 595
 596 typedef struct {
 597     uint64_t base;
 598     uint64_t mask;
 599 } MTRRVar;
 600
 601 #define CPU_NB_REGS64 16
 602 #define CPU_NB_REGS32 8
 603
 604 #ifdef TARGET_X86_64
 605 #define CPU_NB_REGS CPU_NB_REGS64
 606 #else
 607 #define CPU_NB_REGS CPU_NB_REGS32
 608 #endif
 609
 610 #define NB_MMU_MODES 2
 611
 612 typedef struct CPUX86State {
 613     /* standard registers */
 614     target_ulong regs[CPU_NB_REGS];
 615     target_ulong eip;
 616     target_ulong eflags; /* eflags register. During CPU emulation, CC
 617                         flags and DF are set to zero because they are
 618                         stored elsewhere */
 619
 620     /* emulator internal eflags handling */
 621     target_ulong cc_src;
 622     target_ulong cc_dst;
 623     uint32_t cc_op;
 624     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 625     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 626                         are known at translation time. */
 627     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 628
 629     /* segments */
 630     SegmentCache segs[6]; /* selector values */
 631     SegmentCache ldt;
 632     SegmentCache tr;
 633     SegmentCache gdt; /* only base and limit are used */
 634     SegmentCache idt; /* only base and limit are used */
 635
 636     target_ulong cr[5]; /* NOTE: cr1 is unused */
 637     int32_t a20_mask;
 638
 639     /* FPU state */
 640     unsigned int fpstt; /* top of stack index */
 641     uint16_t fpus;
 642     uint16_t fpuc;
 643     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 644     FPReg fpregs[8];
 645
 646     /* emulator internal variables */
 647     float_status fp_status;
 648     CPU86_LDouble ft0;
 649
 650     float_status mmx_status; /* for 3DNow! float ops */
 651     float_status sse_status;
 652     uint32_t mxcsr;
 653     XMMReg xmm_regs[CPU_NB_REGS];
 654     XMMReg xmm_t0;
 655     MMXReg mmx_t0;
 656     target_ulong cc_tmp; /* temporary for rcr/rcl */
 657
 658     /* sysenter registers */
 659     uint32_t sysenter_cs;
 660     target_ulong sysenter_esp;
 661     target_ulong sysenter_eip;
 662     uint64_t efer;
 663     uint64_t star;
 664
 665     uint64_t vm_hsave;
 666     uint64_t vm_vmcb;
 667     uint64_t tsc_offset;
 668     uint64_t intercept;
 669     uint16_t intercept_cr_read;
 670     uint16_t intercept_cr_write;
 671     uint16_t intercept_dr_read;
 672     uint16_t intercept_dr_write;
 673     uint32_t intercept_exceptions;
 674     uint8_t v_tpr;
 675
 676 #ifdef TARGET_X86_64
 677     target_ulong lstar;
 678     target_ulong cstar;
 679     target_ulong fmask;
 680     target_ulong kernelgsbase;
 681 #endif
 682     uint64_t system_time_msr;
 683     uint64_t wall_clock_msr;
 684     uint64_t async_pf_en_msr;
 685
 686     uint64_t tsc;
 687
 688     uint64_t mcg_status;
 689
 690     /* exception/interrupt handling */
 691     int error_code;
 692     int exception_is_int;
 693     target_ulong exception_next_eip;
 694     target_ulong dr[8]; /* debug registers */
 695     union {
 696         CPUBreakpoint *cpu_breakpoint[4];
 697         CPUWatchpoint *cpu_watchpoint[4];
 698     }; /* break/watchpoints for dr[0..3] */
 699     uint32_t smbase;
 700     int old_exception;  /* exception in flight */
 701
 702     /* KVM states, automatically cleared on reset */
 703     uint8_t nmi_injected;
 704     uint8_t nmi_pending;
 705
 706     CPU_COMMON
 707
 708     uint64_t pat;
 709
 710     /* processor features (e.g. for CPUID insn) */
 711     uint32_t cpuid_level;
 712     uint32_t cpuid_vendor1;
 713     uint32_t cpuid_vendor2;
 714     uint32_t cpuid_vendor3;
 715     uint32_t cpuid_version;
 716     uint32_t cpuid_features;
 717     uint32_t cpuid_ext_features;
 718     uint32_t cpuid_xlevel;
 719     uint32_t cpuid_model[12];
 720     uint32_t cpuid_ext2_features;
 721     uint32_t cpuid_ext3_features;
 722     uint32_t cpuid_apic_id;
 723     int cpuid_vendor_override;
 724
 725     /* MTRRs */
 726     uint64_t mtrr_fixed[11];
 727     uint64_t mtrr_deftype;
 728     MTRRVar mtrr_var[8];
 729
 730     /* For KVM */
 731     uint32_t mp_state;
 732     int32_t exception_injected;
 733     int32_t interrupt_injected;
 734     uint8_t soft_interrupt;
 735     uint8_t has_error_code;
 736     uint32_t sipi_vector;
 737     uint32_t cpuid_kvm_features;
 738     uint32_t cpuid_svm_features;
 739     bool tsc_valid;
 740
 741     /* in order to simplify APIC support, we leave this pointer to the
 742        user */
 743     struct DeviceState *apic_state;
 744
 745     uint64_t mcg_cap;
 746     uint64_t mcg_ctl;
 747     uint64_t mce_banks[MCE_BANKS_DEF*4];
 748
 749     uint64_t tsc_aux;
 750
 751     /* vmstate */
 752     uint16_t fpus_vmstate;
 753     uint16_t fptag_vmstate;
 754     uint16_t fpregs_format_vmstate;
 755
 756     uint64_t xstate_bv;
 757     XMMReg ymmh_regs[CPU_NB_REGS];
 758
 759     uint64_t xcr0;
 760 } CPUX86State;
 761
 762 CPUX86State *cpu_x86_init(const char *cpu_model);
 763 int cpu_x86_exec(CPUX86State *s);
 764 void cpu_x86_close(CPUX86State *s);
 765 void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg);
 766 void x86_cpudef_setup(void);
 767 int cpu_x86_support_mca_broadcast(CPUState *env);
 768
 769 int cpu_get_pic_interrupt(CPUX86State *s);
 770 /* MSDOS compatibility mode FPU exception support */
 771 void cpu_set_ferr(CPUX86State *s);
 772
 773 /* this function must always be used to load data in the segment
 774    cache: it synchronizes the hflags with the segment cache values */
 775 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 776                                           int seg_reg, unsigned int selector,
 777                                           target_ulong base,
 778                                           unsigned int limit,
 779                                           unsigned int flags)
 780 {
 781     SegmentCache *sc;
 782     unsigned int new_hflags;
 783
 784     sc = &env->segs[seg_reg];
 785     sc->selector = selector;
 786     sc->base = base;
 787     sc->limit = limit;
 788     sc->flags = flags;
 789
 790     /* update the hidden flags */
 791     {
 792         if (seg_reg == R_CS) {
 793 #ifdef TARGET_X86_64
 794             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 795                 /* long mode */
 796                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 797                 env->hflags &= ~(HF_ADDSEG_MASK);
 798             } else
 799 #endif
 800             {
 801                 /* legacy / compatibility case */
 802                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 803                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 804                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 805                     new_hflags;
 806             }
 807         }
 808         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 809             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 810         if (env->hflags & HF_CS64_MASK) {
 811             /* zero base assumed for DS, ES and SS in long mode */
 812         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 813                    (env->eflags & VM_MASK) ||
 814                    !(env->hflags & HF_CS32_MASK)) {
 815             /* XXX: try to avoid this test. The problem comes from the
 816                fact that is real mode or vm86 mode we only modify the
 817                'base' and 'selector' fields of the segment cache to go
 818                faster. A solution may be to force addseg to one in
 819                translate-i386.c. */
 820             new_hflags |= HF_ADDSEG_MASK;
 821         } else {
 822             new_hflags |= ((env->segs[R_DS].base |
 823                             env->segs[R_ES].base |
 824                             env->segs[R_SS].base) != 0) <<
 825                 HF_ADDSEG_SHIFT;
 826         }
 827         env->hflags = (env->hflags &
 828                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 829     }
 830 }
 831
 832 static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
 833                                                int sipi_vector)
 834 {
 835     env->eip = 0;
 836     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
 837                            sipi_vector << 12,
 838                            env->segs[R_CS].limit,
 839                            env->segs[R_CS].flags);
 840     env->halted = 0;
 841 }
 842
 843 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
 844                             target_ulong *base, unsigned int *limit,
 845                             unsigned int *flags);
 846
 847 /* wrapper, just in case memory mappings must be changed */
 848 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 849 {
 850 #if HF_CPL_MASK == 3
 851     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 852 #else
 853 #error HF_CPL_MASK is hardcoded
 854 #endif
 855 }
 856
 857 /* op_helper.c */
 858 /* used for debug or cpu save/restore */
 859 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 860 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 861
 862 /* cpu-exec.c */
 863 /* the following helpers are only usable in user mode simulation as
 864    they can trigger unexpected exceptions */
 865 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 866 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 867 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 868
 869 /* you can call this signal handler from your SIGBUS and SIGSEGV
 870    signal handlers to inform the virtual CPU of exceptions. non zero
 871    is returned if the signal was handled by the virtual CPU.  */
 872 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 873                            void *puc);
 874
 875 /* cpuid.c */
 876 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
 877                    uint32_t *eax, uint32_t *ebx,
 878                    uint32_t *ecx, uint32_t *edx);
 879 int cpu_x86_register (CPUX86State *env, const char *cpu_model);
 880 void cpu_clear_apic_feature(CPUX86State *env);
 881 void host_cpuid(uint32_t function, uint32_t count,
 882                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
 883
 884 /* helper.c */
 885 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
 886                              int is_write, int mmu_idx, int is_softmmu);
 887 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
 888 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 889
 890 static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
 891 {
 892     return (dr7 >> (index * 2)) & 3;
 893 }
 894
 895 static inline int hw_breakpoint_type(unsigned long dr7, int index)
 896 {
 897     return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
 898 }
 899
 900 static inline int hw_breakpoint_len(unsigned long dr7, int index)
 901 {
 902     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
 903     return (len == 2) ? 8 : len + 1;
 904 }
 905
 906 void hw_breakpoint_insert(CPUX86State *env, int index);
 907 void hw_breakpoint_remove(CPUX86State *env, int index);
 908 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
 909
 910 /* will be suppressed */
 911 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 912 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
 913 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
 914
 915 /* hw/pc.c */
 916 void cpu_smm_update(CPUX86State *env);
 917 uint64_t cpu_get_tsc(CPUX86State *env);
 918
 919 /* used to debug */
 920 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 921 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 922
 923 #define TARGET_PAGE_BITS 12
 924
 925 #ifdef TARGET_X86_64
 926 #define TARGET_PHYS_ADDR_SPACE_BITS 52
 927 /* ??? This is really 48 bits, sign-extended, but the only thing
 928    accessible to userland with bit 48 set is the VSYSCALL, and that
 929    is handled via other mechanisms.  */
 930 #define TARGET_VIRT_ADDR_SPACE_BITS 47
 931 #else
 932 #define TARGET_PHYS_ADDR_SPACE_BITS 36
 933 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 934 #endif
 935
 936 #define cpu_init cpu_x86_init
 937 #define cpu_exec cpu_x86_exec
 938 #define cpu_gen_code cpu_x86_gen_code
 939 #define cpu_signal_handler cpu_x86_signal_handler
 940 #define cpu_list_id x86_cpu_list
 941 #define cpudef_setup    x86_cpudef_setup
 942
 943 #define CPU_SAVE_VERSION 12
 944
 945 /* MMU modes definitions */
 946 #define MMU_MODE0_SUFFIX _kernel
 947 #define MMU_MODE1_SUFFIX _user
 948 #define MMU_USER_IDX 1
 949 static inline int cpu_mmu_index (CPUState *env)
 950 {
 951     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 952 }
 953
 954 /* translate.c */
 955 void optimize_flags_init(void);
 956
 957 typedef struct CCTable {
 958     int (*compute_all)(void); /* return all the flags */
 959     int (*compute_c)(void);  /* return the C flag */
 960 } CCTable;
 961
 962 #if defined(CONFIG_USER_ONLY)
 963 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 964 {
 965     if (newsp)
 966         env->regs[R_ESP] = newsp;
 967     env->regs[R_EAX] = 0;
 968 }
 969 #endif
 970
 971 #include "cpu-all.h"
 972 #include "svm.h"
 973
 974 #if !defined(CONFIG_USER_ONLY)
 975 #include "hw/apic.h"
 976 #endif
 977
 978 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 979                                         target_ulong *cs_base, int *flags)
 980 {
 981     *cs_base = env->segs[R_CS].base;
 982     *pc = *cs_base + env->eip;
 983     *flags = env->hflags |
 984         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
 985 }
 986
 987 void do_cpu_init(CPUState *env);
 988 void do_cpu_sipi(CPUState *env);
 989
 990 #define MCE_INJECT_BROADCAST    1
 991 #define MCE_INJECT_UNCOND_AO    2
 992
 993 void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
 994                         uint64_t status, uint64_t mcg_status, uint64_t addr,
 995                         uint64_t misc, int flags);
 996
 997 #endif /* CPU_I386_H */