hw/cpu/arm11mpcore.c

   1 /*
   2  * ARM11MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "qemu/timer.h"
  12
  13 /* MPCore private memory region.  */
  14
  15 typedef struct ARM11MPCorePriveState {
  16     SysBusDevice busdev;
  17     uint32_t scu_control;
  18     int iomemtype;
  19     uint32_t old_timer_status[8];
  20     uint32_t num_cpu;
  21     MemoryRegion iomem;
  22     MemoryRegion container;
  23     DeviceState *mptimer;
  24     DeviceState *wdtimer;
  25     DeviceState *gic;
  26     uint32_t num_irq;
  27 } ARM11MPCorePriveState;
  28
  29 /* Per-CPU private memory mapped IO.  */
  30
  31 static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
  32                                 unsigned size)
  33 {
  34     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  35     int id;
  36     /* SCU */
  37     switch (offset) {
  38     case 0x00: /* Control.  */
  39         return s->scu_control;
  40     case 0x04: /* Configuration.  */
  41         id = ((1 << s->num_cpu) - 1) << 4;
  42         return id | (s->num_cpu - 1);
  43     case 0x08: /* CPU status.  */
  44         return 0;
  45     case 0x0c: /* Invalidate all.  */
  46         return 0;
  47     default:
  48         qemu_log_mask(LOG_GUEST_ERROR,
  49                       "mpcore_priv_read: Bad offset %x\n", (int)offset);
  50         return 0;
  51     }
  52 }
  53
  54 static void mpcore_scu_write(void *opaque, hwaddr offset,
  55                              uint64_t value, unsigned size)
  56 {
  57     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  58     /* SCU */
  59     switch (offset) {
  60     case 0: /* Control register.  */
  61         s->scu_control = value & 1;
  62         break;
  63     case 0x0c: /* Invalidate all.  */
  64         /* This is a no-op as cache is not emulated.  */
  65         break;
  66     default:
  67         qemu_log_mask(LOG_GUEST_ERROR,
  68                       "mpcore_priv_read: Bad offset %x\n", (int)offset);
  69     }
  70 }
  71
  72 static const MemoryRegionOps mpcore_scu_ops = {
  73     .read = mpcore_scu_read,
  74     .write = mpcore_scu_write,
  75     .endianness = DEVICE_NATIVE_ENDIAN,
  76 };
  77
  78 static void mpcore_priv_set_irq(void *opaque, int irq, int level)
  79 {
  80     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  81     qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
  82 }
  83
  84 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
  85 {
  86     int i;
  87     SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic);
  88     SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer);
  89     SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer);
  90     memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
  91     memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
  92     memory_region_add_subregion(&s->container, 0, &s->iomem);
  93     /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
  94      * at 0x200, 0x300...
  95      */
  96     for (i = 0; i < (s->num_cpu + 1); i++) {
  97         hwaddr offset = 0x100 + (i * 0x100);
  98         memory_region_add_subregion(&s->container, offset,
  99                                     sysbus_mmio_get_region(gicbusdev, i + 1));
 100     }
 101     /* Add the regions for timer and watchdog for "current CPU" and
 102      * for each specific CPU.
 103      */
 104     for (i = 0; i < (s->num_cpu + 1); i++) {
 105         /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
 106         hwaddr offset = 0x600 + i * 0x100;
 107         memory_region_add_subregion(&s->container, offset,
 108                                     sysbus_mmio_get_region(timerbusdev, i));
 109         memory_region_add_subregion(&s->container, offset + 0x20,
 110                                     sysbus_mmio_get_region(wdtbusdev, i));
 111     }
 112     memory_region_add_subregion(&s->container, 0x1000,
 113                                 sysbus_mmio_get_region(gicbusdev, 0));
 114     /* Wire up the interrupt from each watchdog and timer.
 115      * For each core the timer is PPI 29 and the watchdog PPI 30.
 116      */
 117     for (i = 0; i < s->num_cpu; i++) {
 118         int ppibase = (s->num_irq - 32) + i * 32;
 119         sysbus_connect_irq(timerbusdev, i,
 120                            qdev_get_gpio_in(s->gic, ppibase + 29));
 121         sysbus_connect_irq(wdtbusdev, i,
 122                            qdev_get_gpio_in(s->gic, ppibase + 30));
 123     }
 124 }
 125
 126 static int mpcore_priv_init(SysBusDevice *dev)
 127 {
 128     ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev);
 129
 130     s->gic = qdev_create(NULL, "arm_gic");
 131     qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
 132     qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
 133     /* Request the legacy 11MPCore GIC behaviour: */
 134     qdev_prop_set_uint32(s->gic, "revision", 0);
 135     qdev_init_nofail(s->gic);
 136
 137     /* Pass through outbound IRQ lines from the GIC */
 138     sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic));
 139
 140     /* Pass through inbound GPIO lines to the GIC */
 141     qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32);
 142
 143     s->mptimer = qdev_create(NULL, "arm_mptimer");
 144     qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
 145     qdev_init_nofail(s->mptimer);
 146
 147     s->wdtimer = qdev_create(NULL, "arm_mptimer");
 148     qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu);
 149     qdev_init_nofail(s->wdtimer);
 150
 151     mpcore_priv_map_setup(s);
 152     sysbus_init_mmio(dev, &s->container);
 153     return 0;
 154 }
 155
 156 /* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
 157    controllers.  The output of these, plus some of the raw input lines
 158    are fed into a single SMP-aware interrupt controller on the CPU.  */
 159 typedef struct {
 160     SysBusDevice busdev;
 161     SysBusDevice *priv;
 162     qemu_irq cpuic[32];
 163     qemu_irq rvic[4][64];
 164     uint32_t num_cpu;
 165 } mpcore_rirq_state;
 166
 167 /* Map baseboard IRQs onto CPU IRQ lines.  */
 168 static const int mpcore_irq_map[32] = {
 169     -1, -1, -1, -1,  1,  2, -1, -1,
 170     -1, -1,  6, -1,  4,  5, -1, -1,
 171     -1, 14, 15,  0,  7,  8, -1, -1,
 172     -1, -1, -1, -1,  9,  3, -1, -1,
 173 };
 174
 175 static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
 176 {
 177     mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
 178     int i;
 179
 180     for (i = 0; i < 4; i++) {
 181         qemu_set_irq(s->rvic[i][irq], level);
 182     }
 183     if (irq < 32) {
 184         irq = mpcore_irq_map[irq];
 185         if (irq >= 0) {
 186             qemu_set_irq(s->cpuic[irq], level);
 187         }
 188     }
 189 }
 190
 191 static int realview_mpcore_init(SysBusDevice *dev)
 192 {
 193     mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
 194     DeviceState *gic;
 195     DeviceState *priv;
 196     int n;
 197     int i;
 198
 199     priv = qdev_create(NULL, "arm11mpcore_priv");
 200     qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
 201     qdev_init_nofail(priv);
 202     s->priv = SYS_BUS_DEVICE(priv);
 203     sysbus_pass_irq(dev, s->priv);
 204     for (i = 0; i < 32; i++) {
 205         s->cpuic[i] = qdev_get_gpio_in(priv, i);
 206     }
 207     /* ??? IRQ routing is hardcoded to "normal" mode.  */
 208     for (n = 0; n < 4; n++) {
 209         gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
 210                                    s->cpuic[10 + n]);
 211         for (i = 0; i < 64; i++) {
 212             s->rvic[n][i] = qdev_get_gpio_in(gic, i);
 213         }
 214     }
 215     qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
 216     sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
 217     return 0;
 218 }
 219
 220 static Property mpcore_rirq_properties[] = {
 221     DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
 222     DEFINE_PROP_END_OF_LIST(),
 223 };
 224
 225 static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
 226 {
 227     DeviceClass *dc = DEVICE_CLASS(klass);
 228     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 229
 230     k->init = realview_mpcore_init;
 231     dc->props = mpcore_rirq_properties;
 232 }
 233
 234 static const TypeInfo mpcore_rirq_info = {
 235     .name          = "realview_mpcore",
 236     .parent        = TYPE_SYS_BUS_DEVICE,
 237     .instance_size = sizeof(mpcore_rirq_state),
 238     .class_init    = mpcore_rirq_class_init,
 239 };
 240
 241 static Property mpcore_priv_properties[] = {
 242     DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
 243     /* The ARM11 MPCORE TRM says the on-chip controller may have
 244      * anything from 0 to 224 external interrupt IRQ lines (with another
 245      * 32 internal). We default to 32+32, which is the number provided by
 246      * the ARM11 MPCore test chip in the Realview Versatile Express
 247      * coretile. Other boards may differ and should set this property
 248      * appropriately. Some Linux kernels may not boot if the hardware
 249      * has more IRQ lines than the kernel expects.
 250      */
 251     DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
 252     DEFINE_PROP_END_OF_LIST(),
 253 };
 254
 255 static void mpcore_priv_class_init(ObjectClass *klass, void *data)
 256 {
 257     DeviceClass *dc = DEVICE_CLASS(klass);
 258     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 259
 260     k->init = mpcore_priv_init;
 261     dc->props = mpcore_priv_properties;
 262 }
 263
 264 static const TypeInfo mpcore_priv_info = {
 265     .name          = "arm11mpcore_priv",
 266     .parent        = TYPE_SYS_BUS_DEVICE,
 267     .instance_size = sizeof(ARM11MPCorePriveState),
 268     .class_init    = mpcore_priv_class_init,
 269 };
 270
 271 static void arm11mpcore_register_types(void)
 272 {
 273     type_register_static(&mpcore_rirq_info);
 274     type_register_static(&mpcore_priv_info);
 275 }
 276
 277 type_init(arm11mpcore_register_types)