hw/ppc/mac_oldworld.c

   1
   2 /*
   3  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   4  *
   5  * Copyright (c) 2004-2007 Fabrice Bellard
   6  * Copyright (c) 2007 Jocelyn Mayer
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "hw/hw.h"
  27 #include "hw/ppc/ppc.h"
  28 #include "mac.h"
  29 #include "hw/input/adb.h"
  30 #include "hw/timer/m48t59.h"
  31 #include "sysemu/sysemu.h"
  32 #include "net/net.h"
  33 #include "hw/isa/isa.h"
  34 #include "hw/pci/pci.h"
  35 #include "hw/boards.h"
  36 #include "hw/nvram/fw_cfg.h"
  37 #include "hw/char/escc.h"
  38 #include "hw/ide.h"
  39 #include "hw/loader.h"
  40 #include "elf.h"
  41 #include "sysemu/kvm.h"
  42 #include "kvm_ppc.h"
  43 #include "sysemu/blockdev.h"
  44 #include "exec/address-spaces.h"
  45
  46 #define MAX_IDE_BUS 2
  47 #define CFG_ADDR 0xf0000510
  48
  49 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
  50 {
  51     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  52     return 0;
  53 }
  54
  55
  56 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
  57 {
  58     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
  59 }
  60
  61 static hwaddr round_page(hwaddr addr)
  62 {
  63     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
  64 }
  65
  66 static void ppc_heathrow_reset(void *opaque)
  67 {
  68     PowerPCCPU *cpu = opaque;
  69
  70     cpu_reset(CPU(cpu));
  71 }
  72
  73 static void ppc_heathrow_init(QEMUMachineInitArgs *args)
  74 {
  75     ram_addr_t ram_size = args->ram_size;
  76     const char *cpu_model = args->cpu_model;
  77     const char *kernel_filename = args->kernel_filename;
  78     const char *kernel_cmdline = args->kernel_cmdline;
  79     const char *initrd_filename = args->initrd_filename;
  80     const char *boot_device = args->boot_device;
  81     MemoryRegion *sysmem = get_system_memory();
  82     PowerPCCPU *cpu = NULL;
  83     CPUPPCState *env = NULL;
  84     char *filename;
  85     qemu_irq *pic, **heathrow_irqs;
  86     int linux_boot, i;
  87     MemoryRegion *ram = g_new(MemoryRegion, 1);
  88     MemoryRegion *bios = g_new(MemoryRegion, 1);
  89     uint32_t kernel_base, initrd_base, cmdline_base = 0;
  90     int32_t kernel_size, initrd_size;
  91     PCIBus *pci_bus;
  92     PCIDevice *macio;
  93     MACIOIDEState *macio_ide;
  94     DeviceState *dev;
  95     BusState *adb_bus;
  96     int bios_size;
  97     MemoryRegion *pic_mem;
  98     MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1);
  99     uint16_t ppc_boot_device;
 100     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 101     void *fw_cfg;
 102
 103     linux_boot = (kernel_filename != NULL);
 104
 105     /* init CPUs */
 106     if (cpu_model == NULL)
 107         cpu_model = "G3";
 108     for (i = 0; i < smp_cpus; i++) {
 109         cpu = cpu_ppc_init(cpu_model);
 110         if (cpu == NULL) {
 111             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 112             exit(1);
 113         }
 114         env = &cpu->env;
 115
 116         /* Set time-base frequency to 16.6 Mhz */
 117         cpu_ppc_tb_init(env,  16600000UL);
 118         qemu_register_reset(ppc_heathrow_reset, cpu);
 119     }
 120
 121     /* allocate RAM */
 122     if (ram_size > (2047 << 20)) {
 123         fprintf(stderr,
 124                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 125                 ((unsigned int)ram_size / (1 << 20)));
 126         exit(1);
 127     }
 128
 129     memory_region_init_ram(ram, "ppc_heathrow.ram", ram_size);
 130     vmstate_register_ram_global(ram);
 131     memory_region_add_subregion(sysmem, 0, ram);
 132
 133     /* allocate and load BIOS */
 134     memory_region_init_ram(bios, "ppc_heathrow.bios", BIOS_SIZE);
 135     vmstate_register_ram_global(bios);
 136     if (bios_name == NULL)
 137         bios_name = PROM_FILENAME;
 138     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 139     memory_region_set_readonly(bios, true);
 140     memory_region_add_subregion(sysmem, PROM_ADDR, bios);
 141
 142     /* Load OpenBIOS (ELF) */
 143     if (filename) {
 144         bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
 145                              1, ELF_MACHINE, 0);
 146         g_free(filename);
 147     } else {
 148         bios_size = -1;
 149     }
 150     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 151         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 152         exit(1);
 153     }
 154
 155     if (linux_boot) {
 156         uint64_t lowaddr = 0;
 157         int bswap_needed;
 158
 159 #ifdef BSWAP_NEEDED
 160         bswap_needed = 1;
 161 #else
 162         bswap_needed = 0;
 163 #endif
 164         kernel_base = KERNEL_LOAD_ADDR;
 165         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 166                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 167         if (kernel_size < 0)
 168             kernel_size = load_aout(kernel_filename, kernel_base,
 169                                     ram_size - kernel_base, bswap_needed,
 170                                     TARGET_PAGE_SIZE);
 171         if (kernel_size < 0)
 172             kernel_size = load_image_targphys(kernel_filename,
 173                                               kernel_base,
 174                                               ram_size - kernel_base);
 175         if (kernel_size < 0) {
 176             hw_error("qemu: could not load kernel '%s'\n",
 177                       kernel_filename);
 178             exit(1);
 179         }
 180         /* load initrd */
 181         if (initrd_filename) {
 182             initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 183             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 184                                               ram_size - initrd_base);
 185             if (initrd_size < 0) {
 186                 hw_error("qemu: could not load initial ram disk '%s'\n",
 187                          initrd_filename);
 188                 exit(1);
 189             }
 190             cmdline_base = round_page(initrd_base + initrd_size);
 191         } else {
 192             initrd_base = 0;
 193             initrd_size = 0;
 194             cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 195         }
 196         ppc_boot_device = 'm';
 197     } else {
 198         kernel_base = 0;
 199         kernel_size = 0;
 200         initrd_base = 0;
 201         initrd_size = 0;
 202         ppc_boot_device = '\0';
 203         for (i = 0; boot_device[i] != '\0'; i++) {
 204             /* TOFIX: for now, the second IDE channel is not properly
 205              *        used by OHW. The Mac floppy disk are not emulated.
 206              *        For now, OHW cannot boot from the network.
 207              */
 208 #if 0
 209             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 210                 ppc_boot_device = boot_device[i];
 211                 break;
 212             }
 213 #else
 214             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 215                 ppc_boot_device = boot_device[i];
 216                 break;
 217             }
 218 #endif
 219         }
 220         if (ppc_boot_device == '\0') {
 221             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 222             exit(1);
 223         }
 224     }
 225
 226     /* Register 2 MB of ISA IO space */
 227     isa_mmio_init(0xfe000000, 0x00200000);
 228
 229     /* XXX: we register only 1 output pin for heathrow PIC */
 230     heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 231     heathrow_irqs[0] =
 232         g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
 233     /* Connect the heathrow PIC outputs to the 6xx bus */
 234     for (i = 0; i < smp_cpus; i++) {
 235         switch (PPC_INPUT(env)) {
 236         case PPC_FLAGS_INPUT_6xx:
 237             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 238             heathrow_irqs[i][0] =
 239                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 240             break;
 241         default:
 242             hw_error("Bus model not supported on OldWorld Mac machine\n");
 243         }
 244     }
 245
 246     /* init basic PC hardware */
 247     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 248         hw_error("Only 6xx bus is supported on heathrow machine\n");
 249     }
 250     pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
 251     pci_bus = pci_grackle_init(0xfec00000, pic,
 252                                get_system_memory(),
 253                                get_system_io());
 254     pci_vga_init(pci_bus);
 255
 256     escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
 257                                serial_hds[1], ESCC_CLOCK, 4);
 258     memory_region_init_alias(escc_bar, "escc-bar",
 259                              escc_mem, 0, memory_region_size(escc_mem));
 260
 261     for(i = 0; i < nb_nics; i++)
 262         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 263
 264
 265     ide_drive_get(hd, MAX_IDE_BUS);
 266
 267     macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
 268     dev = DEVICE(macio);
 269     qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
 270     qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE */
 271     qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
 272     macio_init(macio, pic_mem, escc_bar);
 273
 274     /* First IDE channel is a MAC IDE on the MacIO bus */
 275     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
 276                                                         "ide"));
 277     macio_ide_init_drives(macio_ide, hd);
 278
 279     /* Second IDE channel is a CMD646 on the PCI bus */
 280     hd[0] = hd[MAX_IDE_DEVS];
 281     hd[1] = hd[MAX_IDE_DEVS + 1];
 282     hd[3] = hd[2] = NULL;
 283     pci_cmd646_ide_init(pci_bus, hd, 0);
 284
 285     dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
 286     adb_bus = qdev_get_child_bus(dev, "adb.0");
 287     dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
 288     qdev_init_nofail(dev);
 289     dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
 290     qdev_init_nofail(dev);
 291
 292     if (usb_enabled(false)) {
 293         pci_create_simple(pci_bus, -1, "pci-ohci");
 294     }
 295
 296     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 297         graphic_depth = 15;
 298
 299     /* No PCI init: the BIOS will do it */
 300
 301     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 302     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 303     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 304     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 305     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 306     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 307     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 308     if (kernel_cmdline) {
 309         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
 310         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
 311     } else {
 312         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 313     }
 314     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 315     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 316     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 317
 318     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 319     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 320     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 321
 322     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 323     if (kvm_enabled()) {
 324 #ifdef CONFIG_KVM
 325         uint8_t *hypercall;
 326
 327         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 328         hypercall = g_malloc(16);
 329         kvmppc_get_hypercall(env, hypercall, 16);
 330         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 331         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 332 #endif
 333     } else {
 334         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
 335     }
 336
 337     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 338 }
 339
 340 static QEMUMachine heathrow_machine = {
 341     .name = "g3beige",
 342     .desc = "Heathrow based PowerMAC",
 343     .init = ppc_heathrow_init,
 344     .max_cpus = MAX_CPUS,
 345 #ifndef TARGET_PPC64
 346     .is_default = 1,
 347 #endif
 348     DEFAULT_MACHINE_OPTIONS,
 349 };
 350
 351 static void heathrow_machine_init(void)
 352 {
 353     qemu_register_machine(&heathrow_machine);
 354 }
 355
 356 machine_init(heathrow_machine_init);