hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/timer/m48t59.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/char/serial.h"
  28 #include "hw/block/fdc.h"
  29 #include "net/net.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/ppc/ppc.h"
  35 #include "hw/boards.h"
  36 #include "qemu/log.h"
  37 #include "hw/ide.h"
  38 #include "hw/loader.h"
  39 #include "hw/timer/mc146818rtc.h"
  40 #include "hw/isa/pc87312.h"
  41 #include "sysemu/blockdev.h"
  42 #include "sysemu/arch_init.h"
  43 #include "sysemu/qtest.h"
  44 #include "exec/address-spaces.h"
  45 #include "elf.h"
  46
  47 //#define HARD_DEBUG_PPC_IO
  48 //#define DEBUG_PPC_IO
  49
  50 /* SMP is not enabled, for now */
  51 #define MAX_CPUS 1
  52
  53 #define MAX_IDE_BUS 2
  54
  55 #define BIOS_SIZE (1024 * 1024)
  56 #define BIOS_FILENAME "ppc_rom.bin"
  57 #define KERNEL_LOAD_ADDR 0x01000000
  58 #define INITRD_LOAD_ADDR 0x01800000
  59
  60 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  61 #define DEBUG_PPC_IO
  62 #endif
  63
  64 #if defined (HARD_DEBUG_PPC_IO)
  65 #define PPC_IO_DPRINTF(fmt, ...)                         \
  66 do {                                                     \
  67     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  68         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  69     } else {                                             \
  70         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  71     }                                                    \
  72 } while (0)
  73 #elif defined (DEBUG_PPC_IO)
  74 #define PPC_IO_DPRINTF(fmt, ...) \
  75 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  76 #else
  77 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  78 #endif
  79
  80 /* Constants for devices init */
  81 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  82 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  83 static const int ide_irq[2] = { 13, 13 };
  84
  85 #define NE2000_NB_MAX 6
  86
  87 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  88 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  89
  90 /* ISA IO ports bridge */
  91 #define PPC_IO_BASE 0x80000000
  92
  93 /* PowerPC control and status registers */
  94 #if 0 // Not used
  95 static struct {
  96     /* IDs */
  97     uint32_t veni_devi;
  98     uint32_t revi;
  99     /* Control and status */
 100     uint32_t gcsr;
 101     uint32_t xcfr;
 102     uint32_t ct32;
 103     uint32_t mcsr;
 104     /* General purpose registers */
 105     uint32_t gprg[6];
 106     /* Exceptions */
 107     uint32_t feen;
 108     uint32_t fest;
 109     uint32_t fema;
 110     uint32_t fecl;
 111     uint32_t eeen;
 112     uint32_t eest;
 113     uint32_t eecl;
 114     uint32_t eeint;
 115     uint32_t eemck0;
 116     uint32_t eemck1;
 117     /* Error diagnostic */
 118 } XCSR;
 119
 120 static void PPC_XCSR_writeb (void *opaque,
 121                              hwaddr addr, uint32_t value)
 122 {
 123     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 124            value);
 125 }
 126
 127 static void PPC_XCSR_writew (void *opaque,
 128                              hwaddr addr, uint32_t value)
 129 {
 130     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 131            value);
 132 }
 133
 134 static void PPC_XCSR_writel (void *opaque,
 135                              hwaddr addr, uint32_t value)
 136 {
 137     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 138            value);
 139 }
 140
 141 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
 142 {
 143     uint32_t retval = 0;
 144
 145     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 146            retval);
 147
 148     return retval;
 149 }
 150
 151 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
 152 {
 153     uint32_t retval = 0;
 154
 155     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 156            retval);
 157
 158     return retval;
 159 }
 160
 161 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
 162 {
 163     uint32_t retval = 0;
 164
 165     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 166            retval);
 167
 168     return retval;
 169 }
 170
 171 static const MemoryRegionOps PPC_XCSR_ops = {
 172     .old_mmio = {
 173         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 174         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 175     },
 176     .endianness = DEVICE_LITTLE_ENDIAN,
 177 };
 178
 179 #endif
 180
 181 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 182 typedef struct sysctrl_t {
 183     qemu_irq reset_irq;
 184     M48t59State *nvram;
 185     uint8_t state;
 186     uint8_t syscontrol;
 187     int contiguous_map;
 188     int endian;
 189 } sysctrl_t;
 190
 191 enum {
 192     STATE_HARDFILE = 0x01,
 193 };
 194
 195 static sysctrl_t *sysctrl;
 196
 197 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 198 {
 199     sysctrl_t *sysctrl = opaque;
 200
 201     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 202                    addr - PPC_IO_BASE, val);
 203     switch (addr) {
 204     case 0x0092:
 205         /* Special port 92 */
 206         /* Check soft reset asked */
 207         if (val & 0x01) {
 208             qemu_irq_raise(sysctrl->reset_irq);
 209         } else {
 210             qemu_irq_lower(sysctrl->reset_irq);
 211         }
 212         /* Check LE mode */
 213         if (val & 0x02) {
 214             sysctrl->endian = 1;
 215         } else {
 216             sysctrl->endian = 0;
 217         }
 218         break;
 219     case 0x0800:
 220         /* Motorola CPU configuration register : read-only */
 221         break;
 222     case 0x0802:
 223         /* Motorola base module feature register : read-only */
 224         break;
 225     case 0x0803:
 226         /* Motorola base module status register : read-only */
 227         break;
 228     case 0x0808:
 229         /* Hardfile light register */
 230         if (val & 1)
 231             sysctrl->state |= STATE_HARDFILE;
 232         else
 233             sysctrl->state &= ~STATE_HARDFILE;
 234         break;
 235     case 0x0810:
 236         /* Password protect 1 register */
 237         if (sysctrl->nvram != NULL)
 238             m48t59_toggle_lock(sysctrl->nvram, 1);
 239         break;
 240     case 0x0812:
 241         /* Password protect 2 register */
 242         if (sysctrl->nvram != NULL)
 243             m48t59_toggle_lock(sysctrl->nvram, 2);
 244         break;
 245     case 0x0814:
 246         /* L2 invalidate register */
 247         //        tlb_flush(first_cpu, 1);
 248         break;
 249     case 0x081C:
 250         /* system control register */
 251         sysctrl->syscontrol = val & 0x0F;
 252         break;
 253     case 0x0850:
 254         /* I/O map type register */
 255         sysctrl->contiguous_map = val & 0x01;
 256         break;
 257     default:
 258         printf("ERROR: unaffected IO port write: %04" PRIx32
 259                " => %02" PRIx32"\n", addr, val);
 260         break;
 261     }
 262 }
 263
 264 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 265 {
 266     sysctrl_t *sysctrl = opaque;
 267     uint32_t retval = 0xFF;
 268
 269     switch (addr) {
 270     case 0x0092:
 271         /* Special port 92 */
 272         retval = sysctrl->endian << 1;
 273         break;
 274     case 0x0800:
 275         /* Motorola CPU configuration register */
 276         retval = 0xEF; /* MPC750 */
 277         break;
 278     case 0x0802:
 279         /* Motorola Base module feature register */
 280         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 281         break;
 282     case 0x0803:
 283         /* Motorola base module status register */
 284         retval = 0xE0; /* Standard MPC750 */
 285         break;
 286     case 0x080C:
 287         /* Equipment present register:
 288          *  no L2 cache
 289          *  no upgrade processor
 290          *  no cards in PCI slots
 291          *  SCSI fuse is bad
 292          */
 293         retval = 0x3C;
 294         break;
 295     case 0x0810:
 296         /* Motorola base module extended feature register */
 297         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 298         break;
 299     case 0x0814:
 300         /* L2 invalidate: don't care */
 301         break;
 302     case 0x0818:
 303         /* Keylock */
 304         retval = 0x00;
 305         break;
 306     case 0x081C:
 307         /* system control register
 308          * 7 - 6 / 1 - 0: L2 cache enable
 309          */
 310         retval = sysctrl->syscontrol;
 311         break;
 312     case 0x0823:
 313         /* */
 314         retval = 0x03; /* no L2 cache */
 315         break;
 316     case 0x0850:
 317         /* I/O map type register */
 318         retval = sysctrl->contiguous_map;
 319         break;
 320     default:
 321         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 322         break;
 323     }
 324     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 325                    addr - PPC_IO_BASE, retval);
 326
 327     return retval;
 328 }
 329
 330 static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
 331                                                  hwaddr addr)
 332 {
 333     if (sysctrl->contiguous_map == 0) {
 334         /* 64 KB contiguous space for IOs */
 335         addr &= 0xFFFF;
 336     } else {
 337         /* 8 MB non-contiguous space for IOs */
 338         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 339     }
 340
 341     return addr;
 342 }
 343
 344 static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
 345                                 uint32_t value)
 346 {
 347     sysctrl_t *sysctrl = opaque;
 348
 349     addr = prep_IO_address(sysctrl, addr);
 350     cpu_outb(addr, value);
 351 }
 352
 353 static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
 354 {
 355     sysctrl_t *sysctrl = opaque;
 356     uint32_t ret;
 357
 358     addr = prep_IO_address(sysctrl, addr);
 359     ret = cpu_inb(addr);
 360
 361     return ret;
 362 }
 363
 364 static void PPC_prep_io_writew (void *opaque, hwaddr addr,
 365                                 uint32_t value)
 366 {
 367     sysctrl_t *sysctrl = opaque;
 368
 369     addr = prep_IO_address(sysctrl, addr);
 370     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 371     cpu_outw(addr, value);
 372 }
 373
 374 static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
 375 {
 376     sysctrl_t *sysctrl = opaque;
 377     uint32_t ret;
 378
 379     addr = prep_IO_address(sysctrl, addr);
 380     ret = cpu_inw(addr);
 381     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 382
 383     return ret;
 384 }
 385
 386 static void PPC_prep_io_writel (void *opaque, hwaddr addr,
 387                                 uint32_t value)
 388 {
 389     sysctrl_t *sysctrl = opaque;
 390
 391     addr = prep_IO_address(sysctrl, addr);
 392     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 393     cpu_outl(addr, value);
 394 }
 395
 396 static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
 397 {
 398     sysctrl_t *sysctrl = opaque;
 399     uint32_t ret;
 400
 401     addr = prep_IO_address(sysctrl, addr);
 402     ret = cpu_inl(addr);
 403     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 404
 405     return ret;
 406 }
 407
 408 static const MemoryRegionOps PPC_prep_io_ops = {
 409     .old_mmio = {
 410         .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
 411         .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
 412     },
 413     .endianness = DEVICE_LITTLE_ENDIAN,
 414 };
 415
 416 #define NVRAM_SIZE        0x2000
 417
 418 static void cpu_request_exit(void *opaque, int irq, int level)
 419 {
 420     CPUPPCState *env = cpu_single_env;
 421
 422     if (env && level) {
 423         cpu_exit(env);
 424     }
 425 }
 426
 427 static void ppc_prep_reset(void *opaque)
 428 {
 429     PowerPCCPU *cpu = opaque;
 430
 431     cpu_reset(CPU(cpu));
 432
 433     /* Reset address */
 434     cpu->env.nip = 0xfffffffc;
 435 }
 436
 437 /* PowerPC PREP hardware initialisation */
 438 static void ppc_prep_init(QEMUMachineInitArgs *args)
 439 {
 440     ram_addr_t ram_size = args->ram_size;
 441     const char *cpu_model = args->cpu_model;
 442     const char *kernel_filename = args->kernel_filename;
 443     const char *kernel_cmdline = args->kernel_cmdline;
 444     const char *initrd_filename = args->initrd_filename;
 445     const char *boot_device = args->boot_device;
 446     MemoryRegion *sysmem = get_system_memory();
 447     PowerPCCPU *cpu = NULL;
 448     CPUPPCState *env = NULL;
 449     char *filename;
 450     nvram_t nvram;
 451     M48t59State *m48t59;
 452     MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
 453 #if 0
 454     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 455 #endif
 456     int linux_boot, i, nb_nics1, bios_size;
 457     MemoryRegion *ram = g_new(MemoryRegion, 1);
 458     MemoryRegion *bios = g_new(MemoryRegion, 1);
 459     uint32_t kernel_base, initrd_base;
 460     long kernel_size, initrd_size;
 461     DeviceState *dev;
 462     PCIHostState *pcihost;
 463     PCIBus *pci_bus;
 464     PCIDevice *pci;
 465     ISABus *isa_bus;
 466     ISADevice *isa;
 467     qemu_irq *cpu_exit_irq;
 468     int ppc_boot_device;
 469     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 470
 471     sysctrl = g_malloc0(sizeof(sysctrl_t));
 472
 473     linux_boot = (kernel_filename != NULL);
 474
 475     /* init CPUs */
 476     if (cpu_model == NULL)
 477         cpu_model = "602";
 478     for (i = 0; i < smp_cpus; i++) {
 479         cpu = cpu_ppc_init(cpu_model);
 480         if (cpu == NULL) {
 481             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 482             exit(1);
 483         }
 484         env = &cpu->env;
 485
 486         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 487             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 488             cpu_ppc_tb_init(env, 7812500UL);
 489         } else {
 490             /* Set time-base frequency to 100 Mhz */
 491             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 492         }
 493         qemu_register_reset(ppc_prep_reset, cpu);
 494     }
 495
 496     /* allocate RAM */
 497     memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
 498     vmstate_register_ram_global(ram);
 499     memory_region_add_subregion(sysmem, 0, ram);
 500
 501     /* allocate and load BIOS */
 502     memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
 503     memory_region_set_readonly(bios, true);
 504     memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios);
 505     vmstate_register_ram_global(bios);
 506     if (bios_name == NULL)
 507         bios_name = BIOS_FILENAME;
 508     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 509     if (filename) {
 510         bios_size = load_elf(filename, NULL, NULL, NULL,
 511                              NULL, NULL, 1, ELF_MACHINE, 0);
 512         if (bios_size < 0) {
 513             bios_size = get_image_size(filename);
 514             if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 515                 hwaddr bios_addr;
 516                 bios_size = (bios_size + 0xfff) & ~0xfff;
 517                 bios_addr = (uint32_t)(-bios_size);
 518                 bios_size = load_image_targphys(filename, bios_addr, bios_size);
 519             }
 520             if (bios_size > BIOS_SIZE) {
 521                 fprintf(stderr, "qemu: PReP bios '%s' is too large (0x%x)\n",
 522                         bios_name, bios_size);
 523                 exit(1);
 524             }
 525         }
 526     } else {
 527         bios_size = -1;
 528     }
 529     if (bios_size < 0 && !qtest_enabled()) {
 530         fprintf(stderr, "qemu: could not load PPC PReP bios '%s'\n",
 531                 bios_name);
 532         exit(1);
 533     }
 534     if (filename) {
 535         g_free(filename);
 536     }
 537
 538     if (linux_boot) {
 539         kernel_base = KERNEL_LOAD_ADDR;
 540         /* now we can load the kernel */
 541         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 542                                           ram_size - kernel_base);
 543         if (kernel_size < 0) {
 544             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 545             exit(1);
 546         }
 547         /* load initrd */
 548         if (initrd_filename) {
 549             initrd_base = INITRD_LOAD_ADDR;
 550             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 551                                               ram_size - initrd_base);
 552             if (initrd_size < 0) {
 553                 hw_error("qemu: could not load initial ram disk '%s'\n",
 554                           initrd_filename);
 555             }
 556         } else {
 557             initrd_base = 0;
 558             initrd_size = 0;
 559         }
 560         ppc_boot_device = 'm';
 561     } else {
 562         kernel_base = 0;
 563         kernel_size = 0;
 564         initrd_base = 0;
 565         initrd_size = 0;
 566         ppc_boot_device = '\0';
 567         /* For now, OHW cannot boot from the network. */
 568         for (i = 0; boot_device[i] != '\0'; i++) {
 569             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 570                 ppc_boot_device = boot_device[i];
 571                 break;
 572             }
 573         }
 574         if (ppc_boot_device == '\0') {
 575             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 576             exit(1);
 577         }
 578     }
 579
 580     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 581         hw_error("Only 6xx bus is supported on PREP machine\n");
 582     }
 583
 584     dev = qdev_create(NULL, "raven-pcihost");
 585     pcihost = PCI_HOST_BRIDGE(dev);
 586     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 587     qdev_init_nofail(dev);
 588     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 589     if (pci_bus == NULL) {
 590         fprintf(stderr, "Couldn't create PCI host controller.\n");
 591         exit(1);
 592     }
 593
 594     /* PCI -> ISA bridge */
 595     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 596     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 597     qdev_connect_gpio_out(&pci->qdev, 0,
 598                           first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 599     qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
 600     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 601     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 602     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 603     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 604     isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
 605
 606     /* Super I/O (parallel + serial ports) */
 607     isa = isa_create(isa_bus, TYPE_PC87312);
 608     qdev_prop_set_uint8(&isa->qdev, "config", 13); /* fdc, ser0, ser1, par0 */
 609     qdev_init_nofail(&isa->qdev);
 610
 611     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 612     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
 613                           "ppc-io", 0x00800000);
 614     memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
 615
 616     /* init basic PC hardware */
 617     pci_vga_init(pci_bus);
 618
 619     nb_nics1 = nb_nics;
 620     if (nb_nics1 > NE2000_NB_MAX)
 621         nb_nics1 = NE2000_NB_MAX;
 622     for(i = 0; i < nb_nics1; i++) {
 623         if (nd_table[i].model == NULL) {
 624             nd_table[i].model = g_strdup("ne2k_isa");
 625         }
 626         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 627             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 628                             &nd_table[i]);
 629         } else {
 630             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 631         }
 632     }
 633
 634     ide_drive_get(hd, MAX_IDE_BUS);
 635     for(i = 0; i < MAX_IDE_BUS; i++) {
 636         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 637                      hd[2 * i],
 638                      hd[2 * i + 1]);
 639     }
 640     isa_create_simple(isa_bus, "i8042");
 641
 642     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 643     /* System control ports */
 644     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 645     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 646     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 647     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 648     /* PowerPC control and status register group */
 649 #if 0
 650     memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 651     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 652 #endif
 653
 654     if (usb_enabled(false)) {
 655         pci_create_simple(pci_bus, -1, "pci-ohci");
 656     }
 657
 658     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 659     if (m48t59 == NULL)
 660         return;
 661     sysctrl->nvram = m48t59;
 662
 663     /* Initialise NVRAM */
 664     nvram.opaque = m48t59;
 665     nvram.read_fn = &m48t59_read;
 666     nvram.write_fn = &m48t59_write;
 667     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 668                          kernel_base, kernel_size,
 669                          kernel_cmdline,
 670                          initrd_base, initrd_size,
 671                          /* XXX: need an option to load a NVRAM image */
 672                          0,
 673                          graphic_width, graphic_height, graphic_depth);
 674
 675     /* Special port to get debug messages from Open-Firmware */
 676     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 677 }
 678
 679 static QEMUMachine prep_machine = {
 680     .name = "prep",
 681     .desc = "PowerPC PREP platform",
 682     .init = ppc_prep_init,
 683     .max_cpus = MAX_CPUS,
 684     DEFAULT_MACHINE_OPTIONS,
 685 };
 686
 687 static void prep_machine_init(void)
 688 {
 689     qemu_register_machine(&prep_machine);
 690 }
 691
 692 machine_init(prep_machine_init);