hw/timer/imx_timer.c

   1 /*
   2  * IMX31 Timer
   3  *
   4  * Copyright (c) 2008 OK Labs
   5  * Copyright (c) 2011 NICTA Pty Ltd
   6  * Originally written by Hans Jiang
   7  * Updated by Peter Chubb
   8  *
   9  * This code is licensed under GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  *
  12  */
  13
  14 #include "hw/hw.h"
  15 #include "qemu/timer.h"
  16 #include "hw/ptimer.h"
  17 #include "hw/sysbus.h"
  18 #include "hw/arm/imx.h"
  19
  20 //#define DEBUG_TIMER 1
  21 #ifdef DEBUG_TIMER
  22 #  define DPRINTF(fmt, args...) \
  23       do { printf("imx_timer: " fmt , ##args); } while (0)
  24 #else
  25 #  define DPRINTF(fmt, args...) do {} while (0)
  26 #endif
  27
  28 /*
  29  * Define to 1 for messages about attempts to
  30  * access unimplemented registers or similar.
  31  */
  32 #define DEBUG_IMPLEMENTATION 1
  33 #if DEBUG_IMPLEMENTATION
  34 #  define IPRINTF(fmt, args...)                                         \
  35     do  { fprintf(stderr, "imx_timer: " fmt, ##args); } while (0)
  36 #else
  37 #  define IPRINTF(fmt, args...) do {} while (0)
  38 #endif
  39
  40 /*
  41  * GPT : General purpose timer
  42  *
  43  * This timer counts up continuously while it is enabled, resetting itself
  44  * to 0 when it reaches TIMER_MAX (in freerun mode) or when it
  45  * reaches the value of ocr1 (in periodic mode).  WE simulate this using a
  46  * QEMU ptimer counting down from ocr1 and reloading from ocr1 in
  47  * periodic mode, or counting from ocr1 to zero, then TIMER_MAX - ocr1.
  48  * waiting_rov is set when counting from TIMER_MAX.
  49  *
  50  * In the real hardware, there are three comparison registers that can
  51  * trigger interrupts, and compare channel 1 can be used to
  52  * force-reset the timer. However, this is a `bare-bones'
  53  * implementation: only what Linux 3.x uses has been implemented
  54  * (free-running timer from 0 to OCR1 or TIMER_MAX) .
  55  */
  56
  57
  58 #define TIMER_MAX  0XFFFFFFFFUL
  59
  60 /* Control register.  Not all of these bits have any effect (yet) */
  61 #define GPT_CR_EN     (1 << 0)  /* GPT Enable */
  62 #define GPT_CR_ENMOD  (1 << 1)  /* GPT Enable Mode */
  63 #define GPT_CR_DBGEN  (1 << 2)  /* GPT Debug mode enable */
  64 #define GPT_CR_WAITEN (1 << 3)  /* GPT Wait Mode Enable  */
  65 #define GPT_CR_DOZEN  (1 << 4)  /* GPT Doze mode enable */
  66 #define GPT_CR_STOPEN (1 << 5)  /* GPT Stop Mode Enable */
  67 #define GPT_CR_CLKSRC_SHIFT (6)
  68 #define GPT_CR_CLKSRC_MASK  (0x7)
  69
  70 #define GPT_CR_FRR    (1 << 9)  /* Freerun or Restart */
  71 #define GPT_CR_SWR    (1 << 15) /* Software Reset */
  72 #define GPT_CR_IM1    (3 << 16) /* Input capture channel 1 mode (2 bits) */
  73 #define GPT_CR_IM2    (3 << 18) /* Input capture channel 2 mode (2 bits) */
  74 #define GPT_CR_OM1    (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
  75 #define GPT_CR_OM2    (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
  76 #define GPT_CR_OM3    (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
  77 #define GPT_CR_FO1    (1 << 29) /* Force Output Compare Channel 1 */
  78 #define GPT_CR_FO2    (1 << 30) /* Force Output Compare Channel 2 */
  79 #define GPT_CR_FO3    (1 << 31) /* Force Output Compare Channel 3 */
  80
  81 #define GPT_SR_OF1  (1 << 0)
  82 #define GPT_SR_ROV  (1 << 5)
  83
  84 #define GPT_IR_OF1IE  (1 << 0)
  85 #define GPT_IR_ROVIE  (1 << 5)
  86
  87 typedef struct {
  88     SysBusDevice busdev;
  89     ptimer_state *timer;
  90     MemoryRegion iomem;
  91     DeviceState *ccm;
  92
  93     uint32_t cr;
  94     uint32_t pr;
  95     uint32_t sr;
  96     uint32_t ir;
  97     uint32_t ocr1;
  98     uint32_t ocr2;
  99     uint32_t ocr3;
 100     uint32_t icr1;
 101     uint32_t icr2;
 102     uint32_t cnt;
 103
 104     uint32_t waiting_rov;
 105     qemu_irq irq;
 106 } IMXTimerGState;
 107
 108 static const VMStateDescription vmstate_imx_timerg = {
 109     .name = "imx-timerg",
 110     .version_id = 2,
 111     .minimum_version_id = 2,
 112     .minimum_version_id_old = 2,
 113     .fields      = (VMStateField[]) {
 114         VMSTATE_UINT32(cr, IMXTimerGState),
 115         VMSTATE_UINT32(pr, IMXTimerGState),
 116         VMSTATE_UINT32(sr, IMXTimerGState),
 117         VMSTATE_UINT32(ir, IMXTimerGState),
 118         VMSTATE_UINT32(ocr1, IMXTimerGState),
 119         VMSTATE_UINT32(ocr2, IMXTimerGState),
 120         VMSTATE_UINT32(ocr3, IMXTimerGState),
 121         VMSTATE_UINT32(icr1, IMXTimerGState),
 122         VMSTATE_UINT32(icr2, IMXTimerGState),
 123         VMSTATE_UINT32(cnt, IMXTimerGState),
 124         VMSTATE_UINT32(waiting_rov, IMXTimerGState),
 125         VMSTATE_PTIMER(timer, IMXTimerGState),
 126         VMSTATE_END_OF_LIST()
 127     }
 128 };
 129
 130 static const IMXClk imx_timerg_clocks[] = {
 131     NOCLK,    /* 000 No clock source */
 132     IPG,      /* 001 ipg_clk, 532MHz*/
 133     IPG,      /* 010 ipg_clk_highfreq */
 134     NOCLK,    /* 011 not defined */
 135     CLK_32k,  /* 100 ipg_clk_32k */
 136     NOCLK,    /* 101 not defined */
 137     NOCLK,    /* 110 not defined */
 138     NOCLK,    /* 111 not defined */
 139 };
 140
 141
 142 static void imx_timerg_set_freq(IMXTimerGState *s)
 143 {
 144     int clksrc;
 145     uint32_t freq;
 146
 147     clksrc = (s->cr >> GPT_CR_CLKSRC_SHIFT) & GPT_CR_CLKSRC_MASK;
 148     freq = imx_clock_frequency(s->ccm, imx_timerg_clocks[clksrc]) / (1 + s->pr);
 149
 150     DPRINTF("Setting gtimer clksrc %d to frequency %d\n", clksrc, freq);
 151     if (freq) {
 152         ptimer_set_freq(s->timer, freq);
 153     }
 154 }
 155
 156 static void imx_timerg_update(IMXTimerGState *s)
 157 {
 158     uint32_t flags = s->sr & s->ir & (GPT_SR_OF1 | GPT_SR_ROV);
 159
 160     DPRINTF("g-timer SR: %s %s IR=%s %s, %s\n",
 161             s->sr & GPT_SR_OF1 ? "OF1" : "",
 162             s->sr & GPT_SR_ROV ? "ROV" : "",
 163             s->ir & GPT_SR_OF1 ? "OF1" : "",
 164             s->ir & GPT_SR_ROV ? "ROV" : "",
 165             s->cr & GPT_CR_EN ? "CR_EN" : "Not Enabled");
 166
 167     qemu_set_irq(s->irq, (s->cr & GPT_CR_EN) && flags);
 168 }
 169
 170 static uint32_t imx_timerg_update_counts(IMXTimerGState *s)
 171 {
 172     uint64_t target = s->waiting_rov ? TIMER_MAX : s->ocr1;
 173     uint64_t cnt = ptimer_get_count(s->timer);
 174     s->cnt = target - cnt;
 175     return s->cnt;
 176 }
 177
 178 static void imx_timerg_reload(IMXTimerGState *s, uint32_t timeout)
 179 {
 180     uint64_t diff_cnt;
 181
 182     if (!(s->cr & GPT_CR_FRR)) {
 183         IPRINTF("IMX_timerg_reload --- called in reset-mode\n");
 184         return;
 185     }
 186
 187     /*
 188      * For small timeouts, qemu sometimes runs too slow.
 189      * Better deliver a late interrupt than none.
 190      *
 191      * In Reset mode (FRR bit clear)
 192      * the ptimer reloads itself from OCR1;
 193      * in free-running mode we need to fake
 194      * running from 0 to ocr1 to TIMER_MAX
 195      */
 196     if (timeout > s->cnt) {
 197         diff_cnt = timeout - s->cnt;
 198     } else {
 199         diff_cnt = 0;
 200     }
 201     ptimer_set_count(s->timer, diff_cnt);
 202 }
 203
 204 static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
 205                                 unsigned size)
 206 {
 207     IMXTimerGState *s = (IMXTimerGState *)opaque;
 208
 209     DPRINTF("g-read(offset=%x)", offset >> 2);
 210     switch (offset >> 2) {
 211     case 0: /* Control Register */
 212         DPRINTF(" cr = %x\n", s->cr);
 213         return s->cr;
 214
 215     case 1: /* prescaler */
 216         DPRINTF(" pr = %x\n", s->pr);
 217         return s->pr;
 218
 219     case 2: /* Status Register */
 220         DPRINTF(" sr = %x\n", s->sr);
 221         return s->sr;
 222
 223     case 3: /* Interrupt Register */
 224         DPRINTF(" ir = %x\n", s->ir);
 225         return s->ir;
 226
 227     case 4: /* Output Compare Register 1 */
 228         DPRINTF(" ocr1 = %x\n", s->ocr1);
 229         return s->ocr1;
 230
 231     case 5: /* Output Compare Register 2 */
 232         DPRINTF(" ocr2 = %x\n", s->ocr2);
 233         return s->ocr2;
 234
 235     case 6: /* Output Compare Register 3 */
 236         DPRINTF(" ocr3 = %x\n", s->ocr3);
 237         return s->ocr3;
 238
 239     case 7: /* input Capture Register 1 */
 240         DPRINTF(" icr1 = %x\n", s->icr1);
 241         return s->icr1;
 242
 243     case 8: /* input Capture Register 2 */
 244         DPRINTF(" icr2 = %x\n", s->icr2);
 245         return s->icr2;
 246
 247     case 9: /* cnt */
 248         imx_timerg_update_counts(s);
 249         DPRINTF(" cnt = %x\n", s->cnt);
 250         return s->cnt;
 251     }
 252
 253     IPRINTF("imx_timerg_read: Bad offset %x\n",
 254             (int)offset >> 2);
 255
 256     return 0;
 257 }
 258
 259 static void imx_timerg_reset(DeviceState *dev)
 260 {
 261     IMXTimerGState *s = container_of(dev, IMXTimerGState, busdev.qdev);
 262
 263     /*
 264      * Soft reset doesn't touch some bits; hard reset clears them
 265      */
 266     s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
 267                GPT_CR_WAITEN|GPT_CR_DBGEN);
 268     s->sr = 0;
 269     s->pr = 0;
 270     s->ir = 0;
 271     s->cnt = 0;
 272     s->ocr1 = TIMER_MAX;
 273     s->ocr2 = TIMER_MAX;
 274     s->ocr3 = TIMER_MAX;
 275     s->icr1 = 0;
 276     s->icr2 = 0;
 277     ptimer_stop(s->timer);
 278     ptimer_set_limit(s->timer, TIMER_MAX, 1);
 279     ptimer_set_count(s->timer, TIMER_MAX);
 280     imx_timerg_set_freq(s);
 281 }
 282
 283 static void imx_timerg_write(void *opaque, hwaddr offset,
 284                              uint64_t value, unsigned size)
 285 {
 286     IMXTimerGState *s = (IMXTimerGState *)opaque;
 287     DPRINTF("g-write(offset=%x, value = 0x%x)\n", (unsigned int)offset >> 2,
 288             (unsigned int)value);
 289
 290     switch (offset >> 2) {
 291     case 0: {
 292         uint32_t oldcr = s->cr;
 293         /* CR */
 294         if (value & GPT_CR_SWR) { /* force reset */
 295             value &= ~GPT_CR_SWR;
 296             imx_timerg_reset(&s->busdev.qdev);
 297             imx_timerg_update(s);
 298         }
 299
 300         s->cr = value & ~0x7c00;
 301         imx_timerg_set_freq(s);
 302         if ((oldcr ^ value) & GPT_CR_EN) {
 303             if (value & GPT_CR_EN) {
 304                 if (value & GPT_CR_ENMOD) {
 305                     ptimer_set_count(s->timer, s->ocr1);
 306                     s->cnt = 0;
 307                 }
 308                 ptimer_run(s->timer,
 309                            (value & GPT_CR_FRR) && (s->ocr1 != TIMER_MAX));
 310             } else {
 311                 ptimer_stop(s->timer);
 312             };
 313         }
 314         return;
 315     }
 316
 317     case 1: /* Prescaler */
 318         s->pr = value & 0xfff;
 319         imx_timerg_set_freq(s);
 320         return;
 321
 322     case 2: /* SR */
 323         /*
 324          * No point in implementing the status register bits to do with
 325          * external interrupt sources.
 326          */
 327         value &= GPT_SR_OF1 | GPT_SR_ROV;
 328         s->sr &= ~value;
 329         imx_timerg_update(s);
 330         return;
 331
 332     case 3: /* IR -- interrupt register */
 333         s->ir = value & 0x3f;
 334         imx_timerg_update(s);
 335         return;
 336
 337     case 4: /* OCR1 -- output compare register */
 338         /* In non-freerun mode, reset count when this register is written */
 339         if (!(s->cr & GPT_CR_FRR)) {
 340             s->waiting_rov = 0;
 341             ptimer_set_limit(s->timer, value, 1);
 342         } else {
 343             imx_timerg_update_counts(s);
 344             if (value > s->cnt) {
 345                 s->waiting_rov = 0;
 346                 imx_timerg_reload(s, value);
 347             } else {
 348                 s->waiting_rov = 1;
 349                 imx_timerg_reload(s, TIMER_MAX - s->cnt);
 350             }
 351         }
 352         s->ocr1 = value;
 353         return;
 354
 355     case 5: /* OCR2 -- output compare register */
 356     case 6: /* OCR3 -- output compare register */
 357     default:
 358         IPRINTF("imx_timerg_write: Bad offset %x\n",
 359                 (int)offset >> 2);
 360     }
 361 }
 362
 363 static void imx_timerg_timeout(void *opaque)
 364 {
 365     IMXTimerGState *s = (IMXTimerGState *)opaque;
 366
 367     DPRINTF("imx_timerg_timeout, waiting rov=%d\n", s->waiting_rov);
 368     if (s->cr & GPT_CR_FRR) {
 369         /*
 370          * Free running timer from 0 -> TIMERMAX
 371          * Generates interrupt at TIMER_MAX and at cnt==ocr1
 372          * If ocr1 == TIMER_MAX, then no need to reload timer.
 373          */
 374         if (s->ocr1 == TIMER_MAX) {
 375             DPRINTF("s->ocr1 == TIMER_MAX, FRR\n");
 376             s->sr |= GPT_SR_OF1 | GPT_SR_ROV;
 377             imx_timerg_update(s);
 378             return;
 379         }
 380
 381         if (s->waiting_rov) {
 382             /*
 383              * We were waiting for cnt==TIMER_MAX
 384              */
 385             s->sr |= GPT_SR_ROV;
 386             s->waiting_rov = 0;
 387             s->cnt = 0;
 388             imx_timerg_reload(s, s->ocr1);
 389         } else {
 390             /* Must have got a cnt==ocr1 timeout. */
 391             s->sr |= GPT_SR_OF1;
 392             s->cnt = s->ocr1;
 393             s->waiting_rov = 1;
 394             imx_timerg_reload(s, TIMER_MAX);
 395         }
 396         imx_timerg_update(s);
 397         return;
 398     }
 399
 400     s->sr |= GPT_SR_OF1;
 401     imx_timerg_update(s);
 402 }
 403
 404 static const MemoryRegionOps imx_timerg_ops = {
 405     .read = imx_timerg_read,
 406     .write = imx_timerg_write,
 407     .endianness = DEVICE_NATIVE_ENDIAN,
 408 };
 409
 410
 411 static int imx_timerg_init(SysBusDevice *dev)
 412 {
 413     IMXTimerGState *s = FROM_SYSBUS(IMXTimerGState, dev);
 414     QEMUBH *bh;
 415
 416     sysbus_init_irq(dev, &s->irq);
 417     memory_region_init_io(&s->iomem, &imx_timerg_ops,
 418                           s, "imxg-timer",
 419                           0x00001000);
 420     sysbus_init_mmio(dev, &s->iomem);
 421
 422     bh = qemu_bh_new(imx_timerg_timeout, s);
 423     s->timer = ptimer_init(bh);
 424
 425     /* Hard reset resets extra bits in CR */
 426     s->cr = 0;
 427     return 0;
 428 }
 429
 430
 431
 432 /*
 433  * EPIT: Enhanced periodic interrupt timer
 434  */
 435
 436 #define CR_EN       (1 << 0)
 437 #define CR_ENMOD    (1 << 1)
 438 #define CR_OCIEN    (1 << 2)
 439 #define CR_RLD      (1 << 3)
 440 #define CR_PRESCALE_SHIFT (4)
 441 #define CR_PRESCALE_MASK  (0xfff)
 442 #define CR_SWR      (1 << 16)
 443 #define CR_IOVW     (1 << 17)
 444 #define CR_DBGEN    (1 << 18)
 445 #define CR_WAITEN   (1 << 19)
 446 #define CR_DOZEN    (1 << 20)
 447 #define CR_STOPEN   (1 << 21)
 448 #define CR_CLKSRC_SHIFT (24)
 449 #define CR_CLKSRC_MASK  (0x3 << CR_CLKSRC_SHIFT)
 450
 451
 452 /*
 453  * Exact clock frequencies vary from board to board.
 454  * These are typical.
 455  */
 456 static const IMXClk imx_timerp_clocks[] =  {
 457     0,        /* 00 disabled */
 458     IPG,      /* 01 ipg_clk, ~532MHz */
 459     IPG,      /* 10 ipg_clk_highfreq */
 460     CLK_32k,  /* 11 ipg_clk_32k -- ~32kHz */
 461 };
 462
 463 typedef struct {
 464     SysBusDevice busdev;
 465     ptimer_state *timer_reload;
 466     ptimer_state *timer_cmp;
 467     MemoryRegion iomem;
 468     DeviceState *ccm;
 469
 470     uint32_t cr;
 471     uint32_t sr;
 472     uint32_t lr;
 473     uint32_t cmp;
 474     uint32_t cnt;
 475
 476     uint32_t freq;
 477     qemu_irq irq;
 478 } IMXTimerPState;
 479
 480 /*
 481  * Update interrupt status
 482  */
 483 static void imx_timerp_update(IMXTimerPState *s)
 484 {
 485     if (s->sr && (s->cr & CR_OCIEN)) {
 486         qemu_irq_raise(s->irq);
 487     } else {
 488         qemu_irq_lower(s->irq);
 489     }
 490 }
 491
 492 static void set_timerp_freq(IMXTimerPState *s)
 493 {
 494     int clksrc;
 495     unsigned prescaler;
 496     uint32_t freq;
 497
 498     clksrc = (s->cr & CR_CLKSRC_MASK) >> CR_CLKSRC_SHIFT;
 499     prescaler = 1 + ((s->cr >> CR_PRESCALE_SHIFT) & CR_PRESCALE_MASK);
 500     freq = imx_clock_frequency(s->ccm, imx_timerp_clocks[clksrc]) / prescaler;
 501
 502     s->freq = freq;
 503     DPRINTF("Setting ptimer frequency to %u\n", freq);
 504
 505     if (freq) {
 506         ptimer_set_freq(s->timer_reload, freq);
 507         ptimer_set_freq(s->timer_cmp, freq);
 508     }
 509 }
 510
 511 static void imx_timerp_reset(DeviceState *dev)
 512 {
 513     IMXTimerPState *s = container_of(dev, IMXTimerPState, busdev.qdev);
 514
 515     /*
 516      * Soft reset doesn't touch some bits; hard reset clears them
 517      */
 518     s->cr &= ~(CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
 519     s->sr = 0;
 520     s->lr = TIMER_MAX;
 521     s->cmp = 0;
 522     s->cnt = 0;
 523     /* stop both timers */
 524     ptimer_stop(s->timer_cmp);
 525     ptimer_stop(s->timer_reload);
 526     /* compute new frequency */
 527     set_timerp_freq(s);
 528     /* init both timers to TIMER_MAX */
 529     ptimer_set_limit(s->timer_cmp, TIMER_MAX, 1);
 530     ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
 531     if (s->freq && (s->cr & CR_EN)) {
 532         /* if the timer is still enabled, restart it */
 533         ptimer_run(s->timer_reload, 1);
 534     }
 535 }
 536
 537 static uint32_t imx_timerp_update_counts(IMXTimerPState *s)
 538 {
 539      s->cnt = ptimer_get_count(s->timer_reload);
 540
 541      return s->cnt;
 542 }
 543
 544 static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
 545                                 unsigned size)
 546 {
 547     IMXTimerPState *s = (IMXTimerPState *)opaque;
 548
 549     DPRINTF("p-read(offset=%x)", offset >> 2);
 550     switch (offset >> 2) {
 551     case 0: /* Control Register */
 552         DPRINTF("cr %x\n", s->cr);
 553         return s->cr;
 554
 555     case 1: /* Status Register */
 556         DPRINTF("sr %x\n", s->sr);
 557         return s->sr;
 558
 559     case 2: /* LR - ticks*/
 560         DPRINTF("lr %x\n", s->lr);
 561         return s->lr;
 562
 563     case 3: /* CMP */
 564         DPRINTF("cmp %x\n", s->cmp);
 565         return s->cmp;
 566
 567     case 4: /* CNT */
 568         imx_timerp_update_counts(s);
 569         DPRINTF(" cnt = %x\n", s->cnt);
 570         return s->cnt;
 571     }
 572
 573     IPRINTF("imx_timerp_read: Bad offset %x\n",
 574             (int)offset >> 2);
 575     return 0;
 576 }
 577
 578 static void imx_reload_compare_timer(IMXTimerPState *s)
 579 {
 580     if ((s->cr & CR_OCIEN) && s->cmp) {
 581         /* if the compare feature is on */
 582         uint32_t tmp = imx_timerp_update_counts(s);
 583         if (tmp > s->cmp) {
 584             /* reinit the cmp timer if required */
 585             ptimer_set_count(s->timer_cmp, tmp - s->cmp);
 586             if ((s->cr & CR_EN)) {
 587                 /* Restart the cmp timer if required */
 588                 ptimer_run(s->timer_cmp, 0);
 589             }
 590         }
 591     }
 592 }
 593
 594 static void imx_timerp_write(void *opaque, hwaddr offset,
 595                              uint64_t value, unsigned size)
 596 {
 597     IMXTimerPState *s = (IMXTimerPState *)opaque;
 598     DPRINTF("p-write(offset=%x, value = %x)\n", (unsigned int)offset >> 2,
 599             (unsigned int)value);
 600
 601     switch (offset >> 2) {
 602     case 0: /* CR */
 603         s->cr = value & 0x03ffffff;
 604         if (s->cr & CR_SWR) {
 605             /* handle the reset */
 606             imx_timerp_reset(&s->busdev.qdev);
 607         } else {
 608             set_timerp_freq(s);
 609         }
 610
 611         if (s->freq && (s->cr & CR_EN)) {
 612             if (s->cr & CR_ENMOD) {
 613                 if (s->cr & CR_RLD) {
 614                     ptimer_set_limit(s->timer_reload, s->lr, 1);
 615                 } else {
 616                     ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
 617                 }
 618             }
 619
 620             imx_reload_compare_timer(s);
 621
 622             ptimer_run(s->timer_reload, 1);
 623         } else {
 624             /* stop both timers */
 625             ptimer_stop(s->timer_reload);
 626             ptimer_stop(s->timer_cmp);
 627         }
 628         break;
 629
 630     case 1: /* SR - ACK*/
 631         /* writing 1 to OCIF clear the OCIF bit */
 632         if (value & 0x01) {
 633             s->sr = 0;
 634             imx_timerp_update(s);
 635         }
 636         break;
 637
 638     case 2: /* LR - set ticks */
 639         s->lr = value;
 640
 641         if (s->cr & CR_RLD) {
 642             /* Also set the limit if the LRD bit is set */
 643             /* If IOVW bit is set then set the timer value */
 644             ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
 645         } else if (s->cr & CR_IOVW) {
 646             /* If IOVW bit is set then set the timer value */
 647             ptimer_set_count(s->timer_reload, s->lr);
 648         }
 649
 650         imx_reload_compare_timer(s);
 651
 652         break;
 653
 654     case 3: /* CMP */
 655         s->cmp = value;
 656
 657         imx_reload_compare_timer(s);
 658
 659         break;
 660
 661     default:
 662         IPRINTF("imx_timerp_write: Bad offset %x\n",
 663                    (int)offset >> 2);
 664     }
 665 }
 666
 667 static void imx_timerp_reload(void *opaque)
 668 {
 669     IMXTimerPState *s = (IMXTimerPState *)opaque;
 670
 671     DPRINTF("imxp reload\n");
 672
 673     if (!(s->cr & CR_EN)) {
 674         return;
 675     }
 676
 677     if (s->cr & CR_RLD) {
 678         ptimer_set_limit(s->timer_reload, s->lr, 1);
 679     } else {
 680         ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
 681     }
 682
 683     if (s->cr & CR_OCIEN) {
 684         /* if compare register is 0 then we handle the interrupt here */
 685         if (s->cmp == 0) {
 686             s->sr = 1;
 687             imx_timerp_update(s);
 688         } else if (s->cmp <= s->lr) {
 689             /* We should launch the compare register */
 690             ptimer_set_count(s->timer_cmp, s->lr - s->cmp);
 691             ptimer_run(s->timer_cmp, 0);
 692         } else {
 693             IPRINTF("imxp reload: s->lr < s->cmp\n");
 694         }
 695     }
 696 }
 697
 698 static void imx_timerp_cmp(void *opaque)
 699 {
 700     IMXTimerPState *s = (IMXTimerPState *)opaque;
 701
 702     DPRINTF("imxp compare\n");
 703
 704     ptimer_stop(s->timer_cmp);
 705
 706     /* compare register is not 0 */
 707     if (s->cmp) {
 708         s->sr = 1;
 709         imx_timerp_update(s);
 710     }
 711 }
 712
 713 void imx_timerp_create(const hwaddr addr,
 714                               qemu_irq irq,
 715                               DeviceState *ccm)
 716 {
 717     IMXTimerPState *pp;
 718     DeviceState *dev;
 719
 720     dev = sysbus_create_simple("imx_timerp", addr, irq);
 721     pp = container_of(dev, IMXTimerPState, busdev.qdev);
 722     pp->ccm = ccm;
 723 }
 724
 725 static const MemoryRegionOps imx_timerp_ops = {
 726   .read = imx_timerp_read,
 727   .write = imx_timerp_write,
 728   .endianness = DEVICE_NATIVE_ENDIAN,
 729 };
 730
 731 static const VMStateDescription vmstate_imx_timerp = {
 732     .name = "imx-timerp",
 733     .version_id = 2,
 734     .minimum_version_id = 2,
 735     .minimum_version_id_old = 2,
 736     .fields      = (VMStateField[]) {
 737         VMSTATE_UINT32(cr, IMXTimerPState),
 738         VMSTATE_UINT32(sr, IMXTimerPState),
 739         VMSTATE_UINT32(lr, IMXTimerPState),
 740         VMSTATE_UINT32(cmp, IMXTimerPState),
 741         VMSTATE_UINT32(cnt, IMXTimerPState),
 742         VMSTATE_UINT32(freq, IMXTimerPState),
 743         VMSTATE_PTIMER(timer_reload, IMXTimerPState),
 744         VMSTATE_PTIMER(timer_cmp, IMXTimerPState),
 745         VMSTATE_END_OF_LIST()
 746     }
 747 };
 748
 749 static int imx_timerp_init(SysBusDevice *dev)
 750 {
 751     IMXTimerPState *s = FROM_SYSBUS(IMXTimerPState, dev);
 752     QEMUBH *bh;
 753
 754     DPRINTF("imx_timerp_init\n");
 755     sysbus_init_irq(dev, &s->irq);
 756     memory_region_init_io(&s->iomem, &imx_timerp_ops,
 757                           s, "imxp-timer",
 758                           0x00001000);
 759     sysbus_init_mmio(dev, &s->iomem);
 760
 761     bh = qemu_bh_new(imx_timerp_reload, s);
 762     s->timer_reload = ptimer_init(bh);
 763
 764     bh = qemu_bh_new(imx_timerp_cmp, s);
 765     s->timer_cmp = ptimer_init(bh);
 766
 767     return 0;
 768 }
 769
 770
 771 void imx_timerg_create(const hwaddr addr,
 772                               qemu_irq irq,
 773                               DeviceState *ccm)
 774 {
 775     IMXTimerGState *pp;
 776     DeviceState *dev;
 777
 778     dev = sysbus_create_simple("imx_timerg", addr, irq);
 779     pp = container_of(dev, IMXTimerGState, busdev.qdev);
 780     pp->ccm = ccm;
 781 }
 782
 783 static void imx_timerg_class_init(ObjectClass *klass, void *data)
 784 {
 785     DeviceClass *dc  = DEVICE_CLASS(klass);
 786     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 787     k->init = imx_timerg_init;
 788     dc->vmsd = &vmstate_imx_timerg;
 789     dc->reset = imx_timerg_reset;
 790     dc->desc = "i.MX general timer";
 791 }
 792
 793 static void imx_timerp_class_init(ObjectClass *klass, void *data)
 794 {
 795     DeviceClass *dc  = DEVICE_CLASS(klass);
 796     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 797     k->init = imx_timerp_init;
 798     dc->vmsd = &vmstate_imx_timerp;
 799     dc->reset = imx_timerp_reset;
 800     dc->desc = "i.MX periodic timer";
 801 }
 802
 803 static const TypeInfo imx_timerp_info = {
 804     .name = "imx_timerp",
 805     .parent = TYPE_SYS_BUS_DEVICE,
 806     .instance_size = sizeof(IMXTimerPState),
 807     .class_init = imx_timerp_class_init,
 808 };
 809
 810 static const TypeInfo imx_timerg_info = {
 811     .name = "imx_timerg",
 812     .parent = TYPE_SYS_BUS_DEVICE,
 813     .instance_size = sizeof(IMXTimerGState),
 814     .class_init = imx_timerg_class_init,
 815 };
 816
 817 static void imx_timer_register_types(void)
 818 {
 819     type_register_static(&imx_timerp_info);
 820     type_register_static(&imx_timerg_info);
 821 }
 822
 823 type_init(imx_timer_register_types)