hw/timer/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "qemu/timer.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/timer/mc146818rtc.h"
  28 #include "qapi/visitor.h"
  29
  30 #ifdef TARGET_I386
  31 #include "hw/i386/apic.h"
  32 #endif
  33
  34 //#define DEBUG_CMOS
  35 //#define DEBUG_COALESCED
  36
  37 #ifdef DEBUG_CMOS
  38 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  39 #else
  40 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  41 #endif
  42
  43 #ifdef DEBUG_COALESCED
  44 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  45 #else
  46 # define DPRINTF_C(format, ...)      do { } while (0)
  47 #endif
  48
  49 #define NSEC_PER_SEC    1000000000LL
  50 #define SEC_PER_MIN     60
  51 #define MIN_PER_HOUR    60
  52 #define SEC_PER_HOUR    3600
  53 #define HOUR_PER_DAY    24
  54 #define SEC_PER_DAY     86400
  55
  56 #define RTC_REINJECT_ON_ACK_COUNT 20
  57 #define RTC_CLOCK_RATE            32768
  58 #define UIP_HOLD_LENGTH           (8 * NSEC_PER_SEC / 32768)
  59
  60 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
  61
  62 typedef struct RTCState {
  63     ISADevice parent_obj;
  64
  65     MemoryRegion io;
  66     uint8_t cmos_data[128];
  67     uint8_t cmos_index;
  68     int32_t base_year;
  69     uint64_t base_rtc;
  70     uint64_t last_update;
  71     int64_t offset;
  72     qemu_irq irq;
  73     qemu_irq sqw_irq;
  74     int it_shift;
  75     /* periodic timer */
  76     QEMUTimer *periodic_timer;
  77     int64_t next_periodic_time;
  78     /* update-ended timer */
  79     QEMUTimer *update_timer;
  80     uint64_t next_alarm_time;
  81     uint16_t irq_reinject_on_ack_count;
  82     uint32_t irq_coalesced;
  83     uint32_t period;
  84     QEMUTimer *coalesced_timer;
  85     Notifier clock_reset_notifier;
  86     LostTickPolicy lost_tick_policy;
  87     Notifier suspend_notifier;
  88 } RTCState;
  89
  90 static void rtc_set_time(RTCState *s);
  91 static void rtc_update_time(RTCState *s);
  92 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  93 static inline int rtc_from_bcd(RTCState *s, int a);
  94 static uint64_t get_next_alarm(RTCState *s);
  95
  96 static inline bool rtc_running(RTCState *s)
  97 {
  98     return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
  99             (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
 100 }
 101
 102 static uint64_t get_guest_rtc_ns(RTCState *s)
 103 {
 104     uint64_t guest_rtc;
 105     uint64_t guest_clock = qemu_get_clock_ns(rtc_clock);
 106
 107     guest_rtc = s->base_rtc * NSEC_PER_SEC
 108                  + guest_clock - s->last_update + s->offset;
 109     return guest_rtc;
 110 }
 111
 112 #ifdef TARGET_I386
 113 static void rtc_coalesced_timer_update(RTCState *s)
 114 {
 115     if (s->irq_coalesced == 0) {
 116         qemu_del_timer(s->coalesced_timer);
 117     } else {
 118         /* divide each RTC interval to 2 - 8 smaller intervals */
 119         int c = MIN(s->irq_coalesced, 7) + 1;
 120         int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
 121             muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
 122         qemu_mod_timer(s->coalesced_timer, next_clock);
 123     }
 124 }
 125
 126 static void rtc_coalesced_timer(void *opaque)
 127 {
 128     RTCState *s = opaque;
 129
 130     if (s->irq_coalesced != 0) {
 131         apic_reset_irq_delivered();
 132         s->cmos_data[RTC_REG_C] |= 0xc0;
 133         DPRINTF_C("cmos: injecting from timer\n");
 134         qemu_irq_raise(s->irq);
 135         if (apic_get_irq_delivered()) {
 136             s->irq_coalesced--;
 137             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 138                       s->irq_coalesced);
 139         }
 140     }
 141
 142     rtc_coalesced_timer_update(s);
 143 }
 144 #endif
 145
 146 /* handle periodic timer */
 147 static void periodic_timer_update(RTCState *s, int64_t current_time)
 148 {
 149     int period_code, period;
 150     int64_t cur_clock, next_irq_clock;
 151
 152     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 153     if (period_code != 0
 154         && ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
 155             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 156         if (period_code <= 2)
 157             period_code += 7;
 158         /* period in 32 Khz cycles */
 159         period = 1 << (period_code - 1);
 160 #ifdef TARGET_I386
 161         if (period != s->period) {
 162             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 163             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 164         }
 165         s->period = period;
 166 #endif
 167         /* compute 32 khz clock */
 168         cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
 169         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 170         s->next_periodic_time =
 171             muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
 172         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 173     } else {
 174 #ifdef TARGET_I386
 175         s->irq_coalesced = 0;
 176 #endif
 177         qemu_del_timer(s->periodic_timer);
 178     }
 179 }
 180
 181 static void rtc_periodic_timer(void *opaque)
 182 {
 183     RTCState *s = opaque;
 184
 185     periodic_timer_update(s, s->next_periodic_time);
 186     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 187     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 188         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 189 #ifdef TARGET_I386
 190         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 191             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 192                 s->irq_reinject_on_ack_count = 0;
 193             apic_reset_irq_delivered();
 194             qemu_irq_raise(s->irq);
 195             if (!apic_get_irq_delivered()) {
 196                 s->irq_coalesced++;
 197                 rtc_coalesced_timer_update(s);
 198                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 199                           s->irq_coalesced);
 200             }
 201         } else
 202 #endif
 203         qemu_irq_raise(s->irq);
 204     }
 205     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 206         /* Not square wave at all but we don't want 2048Hz interrupts!
 207            Must be seen as a pulse.  */
 208         qemu_irq_raise(s->sqw_irq);
 209     }
 210 }
 211
 212 /* handle update-ended timer */
 213 static void check_update_timer(RTCState *s)
 214 {
 215     uint64_t next_update_time;
 216     uint64_t guest_nsec;
 217     int next_alarm_sec;
 218
 219     /* From the data sheet: "Holding the dividers in reset prevents
 220      * interrupts from operating, while setting the SET bit allows"
 221      * them to occur.  However, it will prevent an alarm interrupt
 222      * from occurring, because the time of day is not updated.
 223      */
 224     if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
 225         qemu_del_timer(s->update_timer);
 226         return;
 227     }
 228     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 229         (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 230         qemu_del_timer(s->update_timer);
 231         return;
 232     }
 233     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 234         (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
 235         qemu_del_timer(s->update_timer);
 236         return;
 237     }
 238
 239     guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 240     /* if UF is clear, reprogram to next second */
 241     next_update_time = qemu_get_clock_ns(rtc_clock)
 242         + NSEC_PER_SEC - guest_nsec;
 243
 244     /* Compute time of next alarm.  One second is already accounted
 245      * for in next_update_time.
 246      */
 247     next_alarm_sec = get_next_alarm(s);
 248     s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
 249
 250     if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
 251         /* UF is set, but AF is clear.  Program the timer to target
 252          * the alarm time.  */
 253         next_update_time = s->next_alarm_time;
 254     }
 255     if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
 256         qemu_mod_timer(s->update_timer, next_update_time);
 257     }
 258 }
 259
 260 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
 261 {
 262     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 263         hour %= 12;
 264         if (s->cmos_data[RTC_HOURS] & 0x80) {
 265             hour += 12;
 266         }
 267     }
 268     return hour;
 269 }
 270
 271 static uint64_t get_next_alarm(RTCState *s)
 272 {
 273     int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
 274     int32_t hour, min, sec;
 275
 276     rtc_update_time(s);
 277
 278     alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
 279     alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
 280     alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
 281     alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
 282
 283     cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 284     cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 285     cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
 286     cur_hour = convert_hour(s, cur_hour);
 287
 288     if (alarm_hour == -1) {
 289         alarm_hour = cur_hour;
 290         if (alarm_min == -1) {
 291             alarm_min = cur_min;
 292             if (alarm_sec == -1) {
 293                 alarm_sec = cur_sec + 1;
 294             } else if (cur_sec > alarm_sec) {
 295                 alarm_min++;
 296             }
 297         } else if (cur_min == alarm_min) {
 298             if (alarm_sec == -1) {
 299                 alarm_sec = cur_sec + 1;
 300             } else {
 301                 if (cur_sec > alarm_sec) {
 302                     alarm_hour++;
 303                 }
 304             }
 305             if (alarm_sec == SEC_PER_MIN) {
 306                 /* wrap to next hour, minutes is not in don't care mode */
 307                 alarm_sec = 0;
 308                 alarm_hour++;
 309             }
 310         } else if (cur_min > alarm_min) {
 311             alarm_hour++;
 312         }
 313     } else if (cur_hour == alarm_hour) {
 314         if (alarm_min == -1) {
 315             alarm_min = cur_min;
 316             if (alarm_sec == -1) {
 317                 alarm_sec = cur_sec + 1;
 318             } else if (cur_sec > alarm_sec) {
 319                 alarm_min++;
 320             }
 321
 322             if (alarm_sec == SEC_PER_MIN) {
 323                 alarm_sec = 0;
 324                 alarm_min++;
 325             }
 326             /* wrap to next day, hour is not in don't care mode */
 327             alarm_min %= MIN_PER_HOUR;
 328         } else if (cur_min == alarm_min) {
 329             if (alarm_sec == -1) {
 330                 alarm_sec = cur_sec + 1;
 331             }
 332             /* wrap to next day, hours+minutes not in don't care mode */
 333             alarm_sec %= SEC_PER_MIN;
 334         }
 335     }
 336
 337     /* values that are still don't care fire at the next min/sec */
 338     if (alarm_min == -1) {
 339         alarm_min = 0;
 340     }
 341     if (alarm_sec == -1) {
 342         alarm_sec = 0;
 343     }
 344
 345     /* keep values in range */
 346     if (alarm_sec == SEC_PER_MIN) {
 347         alarm_sec = 0;
 348         alarm_min++;
 349     }
 350     if (alarm_min == MIN_PER_HOUR) {
 351         alarm_min = 0;
 352         alarm_hour++;
 353     }
 354     alarm_hour %= HOUR_PER_DAY;
 355
 356     hour = alarm_hour - cur_hour;
 357     min = hour * MIN_PER_HOUR + alarm_min - cur_min;
 358     sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
 359     return sec <= 0 ? sec + SEC_PER_DAY : sec;
 360 }
 361
 362 static void rtc_update_timer(void *opaque)
 363 {
 364     RTCState *s = opaque;
 365     int32_t irqs = REG_C_UF;
 366     int32_t new_irqs;
 367
 368     assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
 369
 370     /* UIP might have been latched, update time and clear it.  */
 371     rtc_update_time(s);
 372     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 373
 374     if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
 375         irqs |= REG_C_AF;
 376         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 377             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 378         }
 379     }
 380
 381     new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
 382     s->cmos_data[RTC_REG_C] |= irqs;
 383     if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
 384         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 385         qemu_irq_raise(s->irq);
 386     }
 387     check_update_timer(s);
 388 }
 389
 390 static void cmos_ioport_write(void *opaque, hwaddr addr,
 391                               uint64_t data, unsigned size)
 392 {
 393     RTCState *s = opaque;
 394
 395     if ((addr & 1) == 0) {
 396         s->cmos_index = data & 0x7f;
 397     } else {
 398         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 399                      s->cmos_index, data);
 400         switch(s->cmos_index) {
 401         case RTC_SECONDS_ALARM:
 402         case RTC_MINUTES_ALARM:
 403         case RTC_HOURS_ALARM:
 404             s->cmos_data[s->cmos_index] = data;
 405             check_update_timer(s);
 406             break;
 407         case RTC_IBM_PS2_CENTURY_BYTE:
 408             s->cmos_index = RTC_CENTURY;
 409             /* fall through */
 410         case RTC_CENTURY:
 411         case RTC_SECONDS:
 412         case RTC_MINUTES:
 413         case RTC_HOURS:
 414         case RTC_DAY_OF_WEEK:
 415         case RTC_DAY_OF_MONTH:
 416         case RTC_MONTH:
 417         case RTC_YEAR:
 418             s->cmos_data[s->cmos_index] = data;
 419             /* if in set mode, do not update the time */
 420             if (rtc_running(s)) {
 421                 rtc_set_time(s);
 422                 check_update_timer(s);
 423             }
 424             break;
 425         case RTC_REG_A:
 426             if ((data & 0x60) == 0x60) {
 427                 if (rtc_running(s)) {
 428                     rtc_update_time(s);
 429                 }
 430                 /* What happens to UIP when divider reset is enabled is
 431                  * unclear from the datasheet.  Shouldn't matter much
 432                  * though.
 433                  */
 434                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 435             } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
 436                     (data & 0x70)  <= 0x20) {
 437                 /* when the divider reset is removed, the first update cycle
 438                  * begins one-half second later*/
 439                 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 440                     s->offset = 500000000;
 441                     rtc_set_time(s);
 442                 }
 443                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 444             }
 445             /* UIP bit is read only */
 446             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 447                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 448             periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
 449             check_update_timer(s);
 450             break;
 451         case RTC_REG_B:
 452             if (data & REG_B_SET) {
 453                 /* update cmos to when the rtc was stopping */
 454                 if (rtc_running(s)) {
 455                     rtc_update_time(s);
 456                 }
 457                 /* set mode: reset UIP mode */
 458                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 459                 data &= ~REG_B_UIE;
 460             } else {
 461                 /* if disabling set mode, update the time */
 462                 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 463                     (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
 464                     s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 465                     rtc_set_time(s);
 466                 }
 467             }
 468             /* if an interrupt flag is already set when the interrupt
 469              * becomes enabled, raise an interrupt immediately.  */
 470             if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
 471                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 472                 qemu_irq_raise(s->irq);
 473             } else {
 474                 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
 475                 qemu_irq_lower(s->irq);
 476             }
 477             s->cmos_data[RTC_REG_B] = data;
 478             periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
 479             check_update_timer(s);
 480             break;
 481         case RTC_REG_C:
 482         case RTC_REG_D:
 483             /* cannot write to them */
 484             break;
 485         default:
 486             s->cmos_data[s->cmos_index] = data;
 487             break;
 488         }
 489     }
 490 }
 491
 492 static inline int rtc_to_bcd(RTCState *s, int a)
 493 {
 494     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 495         return a;
 496     } else {
 497         return ((a / 10) << 4) | (a % 10);
 498     }
 499 }
 500
 501 static inline int rtc_from_bcd(RTCState *s, int a)
 502 {
 503     if ((a & 0xc0) == 0xc0) {
 504         return -1;
 505     }
 506     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 507         return a;
 508     } else {
 509         return ((a >> 4) * 10) + (a & 0x0f);
 510     }
 511 }
 512
 513 static void rtc_get_time(RTCState *s, struct tm *tm)
 514 {
 515     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 516     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 517     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 518     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 519         tm->tm_hour %= 12;
 520         if (s->cmos_data[RTC_HOURS] & 0x80) {
 521             tm->tm_hour += 12;
 522         }
 523     }
 524     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 525     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 526     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 527     tm->tm_year =
 528         rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
 529         rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
 530 }
 531
 532 static void rtc_set_time(RTCState *s)
 533 {
 534     struct tm tm;
 535
 536     rtc_get_time(s, &tm);
 537     s->base_rtc = mktimegm(&tm);
 538     s->last_update = qemu_get_clock_ns(rtc_clock);
 539
 540     rtc_change_mon_event(&tm);
 541 }
 542
 543 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
 544 {
 545     int year;
 546
 547     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 548     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 549     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 550         /* 24 hour format */
 551         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 552     } else {
 553         /* 12 hour format */
 554         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 555         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 556         if (tm->tm_hour >= 12)
 557             s->cmos_data[RTC_HOURS] |= 0x80;
 558     }
 559     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 560     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 561     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 562     year = tm->tm_year + 1900 - s->base_year;
 563     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
 564     s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
 565 }
 566
 567 static void rtc_update_time(RTCState *s)
 568 {
 569     struct tm ret;
 570     time_t guest_sec;
 571     int64_t guest_nsec;
 572
 573     guest_nsec = get_guest_rtc_ns(s);
 574     guest_sec = guest_nsec / NSEC_PER_SEC;
 575     gmtime_r(&guest_sec, &ret);
 576
 577     /* Is SET flag of Register B disabled? */
 578     if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
 579         rtc_set_cmos(s, &ret);
 580     }
 581 }
 582
 583 static int update_in_progress(RTCState *s)
 584 {
 585     int64_t guest_nsec;
 586
 587     if (!rtc_running(s)) {
 588         return 0;
 589     }
 590     if (qemu_timer_pending(s->update_timer)) {
 591         int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer);
 592         /* Latch UIP until the timer expires.  */
 593         if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
 594             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 595             return 1;
 596         }
 597     }
 598
 599     guest_nsec = get_guest_rtc_ns(s);
 600     /* UIP bit will be set at last 244us of every second. */
 601     if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
 602         return 1;
 603     }
 604     return 0;
 605 }
 606
 607 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
 608                                  unsigned size)
 609 {
 610     RTCState *s = opaque;
 611     int ret;
 612     if ((addr & 1) == 0) {
 613         return 0xff;
 614     } else {
 615         switch(s->cmos_index) {
 616         case RTC_IBM_PS2_CENTURY_BYTE:
 617             s->cmos_index = RTC_CENTURY;
 618             /* fall through */
 619         case RTC_CENTURY:
 620         case RTC_SECONDS:
 621         case RTC_MINUTES:
 622         case RTC_HOURS:
 623         case RTC_DAY_OF_WEEK:
 624         case RTC_DAY_OF_MONTH:
 625         case RTC_MONTH:
 626         case RTC_YEAR:
 627             /* if not in set mode, calibrate cmos before
 628              * reading*/
 629             if (rtc_running(s)) {
 630                 rtc_update_time(s);
 631             }
 632             ret = s->cmos_data[s->cmos_index];
 633             break;
 634         case RTC_REG_A:
 635             if (update_in_progress(s)) {
 636                 s->cmos_data[s->cmos_index] |= REG_A_UIP;
 637             } else {
 638                 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
 639             }
 640             ret = s->cmos_data[s->cmos_index];
 641             break;
 642         case RTC_REG_C:
 643             ret = s->cmos_data[s->cmos_index];
 644             qemu_irq_lower(s->irq);
 645             s->cmos_data[RTC_REG_C] = 0x00;
 646             if (ret & (REG_C_UF | REG_C_AF)) {
 647                 check_update_timer(s);
 648             }
 649 #ifdef TARGET_I386
 650             if(s->irq_coalesced &&
 651                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 652                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 653                 s->irq_reinject_on_ack_count++;
 654                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 655                 apic_reset_irq_delivered();
 656                 DPRINTF_C("cmos: injecting on ack\n");
 657                 qemu_irq_raise(s->irq);
 658                 if (apic_get_irq_delivered()) {
 659                     s->irq_coalesced--;
 660                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 661                               s->irq_coalesced);
 662                 }
 663             }
 664 #endif
 665             break;
 666         default:
 667             ret = s->cmos_data[s->cmos_index];
 668             break;
 669         }
 670         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 671                      s->cmos_index, ret);
 672         return ret;
 673     }
 674 }
 675
 676 void rtc_set_memory(ISADevice *dev, int addr, int val)
 677 {
 678     RTCState *s = MC146818_RTC(dev);
 679     if (addr >= 0 && addr <= 127)
 680         s->cmos_data[addr] = val;
 681 }
 682
 683 int rtc_get_memory(ISADevice *dev, int addr)
 684 {
 685     RTCState *s = MC146818_RTC(dev);
 686     assert(addr >= 0 && addr <= 127);
 687     return s->cmos_data[addr];
 688 }
 689
 690 static void rtc_set_date_from_host(ISADevice *dev)
 691 {
 692     RTCState *s = MC146818_RTC(dev);
 693     struct tm tm;
 694
 695     qemu_get_timedate(&tm, 0);
 696
 697     s->base_rtc = mktimegm(&tm);
 698     s->last_update = qemu_get_clock_ns(rtc_clock);
 699     s->offset = 0;
 700
 701     /* set the CMOS date */
 702     rtc_set_cmos(s, &tm);
 703 }
 704
 705 static int rtc_post_load(void *opaque, int version_id)
 706 {
 707     RTCState *s = opaque;
 708
 709     if (version_id <= 2) {
 710         rtc_set_time(s);
 711         s->offset = 0;
 712         check_update_timer(s);
 713     }
 714
 715 #ifdef TARGET_I386
 716     if (version_id >= 2) {
 717         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 718             rtc_coalesced_timer_update(s);
 719         }
 720     }
 721 #endif
 722     return 0;
 723 }
 724
 725 static const VMStateDescription vmstate_rtc = {
 726     .name = "mc146818rtc",
 727     .version_id = 3,
 728     .minimum_version_id = 1,
 729     .minimum_version_id_old = 1,
 730     .post_load = rtc_post_load,
 731     .fields      = (VMStateField []) {
 732         VMSTATE_BUFFER(cmos_data, RTCState),
 733         VMSTATE_UINT8(cmos_index, RTCState),
 734         VMSTATE_UNUSED(7*4),
 735         VMSTATE_TIMER(periodic_timer, RTCState),
 736         VMSTATE_INT64(next_periodic_time, RTCState),
 737         VMSTATE_UNUSED(3*8),
 738         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 739         VMSTATE_UINT32_V(period, RTCState, 2),
 740         VMSTATE_UINT64_V(base_rtc, RTCState, 3),
 741         VMSTATE_UINT64_V(last_update, RTCState, 3),
 742         VMSTATE_INT64_V(offset, RTCState, 3),
 743         VMSTATE_TIMER_V(update_timer, RTCState, 3),
 744         VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
 745         VMSTATE_END_OF_LIST()
 746     }
 747 };
 748
 749 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 750 {
 751     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 752     int64_t now = *(int64_t *)data;
 753
 754     rtc_set_date_from_host(ISA_DEVICE(s));
 755     periodic_timer_update(s, now);
 756     check_update_timer(s);
 757 #ifdef TARGET_I386
 758     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 759         rtc_coalesced_timer_update(s);
 760     }
 761 #endif
 762 }
 763
 764 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 765    BIOS will read it and start S3 resume at POST Entry */
 766 static void rtc_notify_suspend(Notifier *notifier, void *data)
 767 {
 768     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 769     rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
 770 }
 771
 772 static void rtc_reset(void *opaque)
 773 {
 774     RTCState *s = opaque;
 775
 776     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 777     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 778     check_update_timer(s);
 779
 780     qemu_irq_lower(s->irq);
 781
 782 #ifdef TARGET_I386
 783     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 784         s->irq_coalesced = 0;
 785     }
 786 #endif
 787 }
 788
 789 static const MemoryRegionOps cmos_ops = {
 790     .read = cmos_ioport_read,
 791     .write = cmos_ioport_write,
 792     .impl = {
 793         .min_access_size = 1,
 794         .max_access_size = 1,
 795     },
 796     .endianness = DEVICE_LITTLE_ENDIAN,
 797 };
 798
 799 static void rtc_get_date(Object *obj, Visitor *v, void *opaque,
 800                          const char *name, Error **errp)
 801 {
 802     RTCState *s = MC146818_RTC(obj);
 803     struct tm current_tm;
 804
 805     rtc_update_time(s);
 806     rtc_get_time(s, &current_tm);
 807     visit_start_struct(v, NULL, "struct tm", name, 0, errp);
 808     visit_type_int32(v, &current_tm.tm_year, "tm_year", errp);
 809     visit_type_int32(v, &current_tm.tm_mon, "tm_mon", errp);
 810     visit_type_int32(v, &current_tm.tm_mday, "tm_mday", errp);
 811     visit_type_int32(v, &current_tm.tm_hour, "tm_hour", errp);
 812     visit_type_int32(v, &current_tm.tm_min, "tm_min", errp);
 813     visit_type_int32(v, &current_tm.tm_sec, "tm_sec", errp);
 814     visit_end_struct(v, errp);
 815 }
 816
 817 static int rtc_initfn(ISADevice *dev)
 818 {
 819     RTCState *s = MC146818_RTC(dev);
 820     int base = 0x70;
 821
 822     s->cmos_data[RTC_REG_A] = 0x26;
 823     s->cmos_data[RTC_REG_B] = 0x02;
 824     s->cmos_data[RTC_REG_C] = 0x00;
 825     s->cmos_data[RTC_REG_D] = 0x80;
 826
 827     /* This is for historical reasons.  The default base year qdev property
 828      * was set to 2000 for most machine types before the century byte was
 829      * implemented.
 830      *
 831      * This if statement means that the century byte will be always 0
 832      * (at least until 2079...) for base_year = 1980, but will be set
 833      * correctly for base_year = 2000.
 834      */
 835     if (s->base_year == 2000) {
 836         s->base_year = 0;
 837     }
 838
 839     rtc_set_date_from_host(dev);
 840
 841 #ifdef TARGET_I386
 842     switch (s->lost_tick_policy) {
 843     case LOST_TICK_SLEW:
 844         s->coalesced_timer =
 845             qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
 846         break;
 847     case LOST_TICK_DISCARD:
 848         break;
 849     default:
 850         return -EINVAL;
 851     }
 852 #endif
 853
 854     s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
 855     s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s);
 856     check_update_timer(s);
 857
 858     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 859     qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
 860
 861     s->suspend_notifier.notify = rtc_notify_suspend;
 862     qemu_register_suspend_notifier(&s->suspend_notifier);
 863
 864     memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
 865     isa_register_ioport(dev, &s->io, base);
 866
 867     qdev_set_legacy_instance_id(&dev->qdev, base, 3);
 868     qemu_register_reset(rtc_reset, s);
 869
 870     object_property_add(OBJECT(s), "date", "struct tm",
 871                         rtc_get_date, NULL, NULL, s, NULL);
 872
 873     return 0;
 874 }
 875
 876 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 877 {
 878     DeviceState *dev;
 879     ISADevice *isadev;
 880     RTCState *s;
 881
 882     isadev = isa_create(bus, TYPE_MC146818_RTC);
 883     dev = DEVICE(isadev);
 884     s = MC146818_RTC(isadev);
 885     qdev_prop_set_int32(dev, "base_year", base_year);
 886     qdev_init_nofail(dev);
 887     if (intercept_irq) {
 888         s->irq = intercept_irq;
 889     } else {
 890         isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
 891     }
 892     return isadev;
 893 }
 894
 895 static Property mc146818rtc_properties[] = {
 896     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 897     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 898                                lost_tick_policy, LOST_TICK_DISCARD),
 899     DEFINE_PROP_END_OF_LIST(),
 900 };
 901
 902 static void rtc_class_initfn(ObjectClass *klass, void *data)
 903 {
 904     DeviceClass *dc = DEVICE_CLASS(klass);
 905     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 906     ic->init = rtc_initfn;
 907     dc->no_user = 1;
 908     dc->vmsd = &vmstate_rtc;
 909     dc->props = mc146818rtc_properties;
 910 }
 911
 912 static const TypeInfo mc146818rtc_info = {
 913     .name          = TYPE_MC146818_RTC,
 914     .parent        = TYPE_ISA_DEVICE,
 915     .instance_size = sizeof(RTCState),
 916     .class_init    = rtc_class_initfn,
 917 };
 918
 919 static void mc146818rtc_register_types(void)
 920 {
 921     type_register_static(&mc146818rtc_info);
 922 }
 923
 924 type_init(mc146818rtc_register_types)