hw/timer/pl031.c

   1 /*
   2  * ARM AMBA PrimeCell PL031 RTC
   3  *
   4  * Copyright (c) 2007 CodeSourcery
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Contributions after 2012-01-13 are licensed under the terms of the
  11  * GNU GPL, version 2 or (at your option) any later version.
  12  */
  13
  14 #include "hw/sysbus.h"
  15 #include "qemu/timer.h"
  16 #include "sysemu/sysemu.h"
  17
  18 //#define DEBUG_PL031
  19
  20 #ifdef DEBUG_PL031
  21 #define DPRINTF(fmt, ...) \
  22 do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
  23 #else
  24 #define DPRINTF(fmt, ...) do {} while(0)
  25 #endif
  26
  27 #define RTC_DR      0x00    /* Data read register */
  28 #define RTC_MR      0x04    /* Match register */
  29 #define RTC_LR      0x08    /* Data load register */
  30 #define RTC_CR      0x0c    /* Control register */
  31 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
  32 #define RTC_RIS     0x14    /* Raw interrupt status register */
  33 #define RTC_MIS     0x18    /* Masked interrupt status register */
  34 #define RTC_ICR     0x1c    /* Interrupt clear register */
  35
  36 typedef struct {
  37     SysBusDevice busdev;
  38     MemoryRegion iomem;
  39     QEMUTimer *timer;
  40     qemu_irq irq;
  41
  42     /* Needed to preserve the tick_count across migration, even if the
  43      * absolute value of the rtc_clock is different on the source and
  44      * destination.
  45      */
  46     uint32_t tick_offset_vmstate;
  47     uint32_t tick_offset;
  48
  49     uint32_t mr;
  50     uint32_t lr;
  51     uint32_t cr;
  52     uint32_t im;
  53     uint32_t is;
  54 } pl031_state;
  55
  56 static const unsigned char pl031_id[] = {
  57     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
  58     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
  59 };
  60
  61 static void pl031_update(pl031_state *s)
  62 {
  63     qemu_set_irq(s->irq, s->is & s->im);
  64 }
  65
  66 static void pl031_interrupt(void * opaque)
  67 {
  68     pl031_state *s = (pl031_state *)opaque;
  69
  70     s->is = 1;
  71     DPRINTF("Alarm raised\n");
  72     pl031_update(s);
  73 }
  74
  75 static uint32_t pl031_get_count(pl031_state *s)
  76 {
  77     int64_t now = qemu_get_clock_ns(rtc_clock);
  78     return s->tick_offset + now / get_ticks_per_sec();
  79 }
  80
  81 static void pl031_set_alarm(pl031_state *s)
  82 {
  83     uint32_t ticks;
  84
  85     /* The timer wraps around.  This subtraction also wraps in the same way,
  86        and gives correct results when alarm < now_ticks.  */
  87     ticks = s->mr - pl031_get_count(s);
  88     DPRINTF("Alarm set in %ud ticks\n", ticks);
  89     if (ticks == 0) {
  90         qemu_del_timer(s->timer);
  91         pl031_interrupt(s);
  92     } else {
  93         int64_t now = qemu_get_clock_ns(rtc_clock);
  94         qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
  95     }
  96 }
  97
  98 static uint64_t pl031_read(void *opaque, hwaddr offset,
  99                            unsigned size)
 100 {
 101     pl031_state *s = (pl031_state *)opaque;
 102
 103     if (offset >= 0xfe0  &&  offset < 0x1000)
 104         return pl031_id[(offset - 0xfe0) >> 2];
 105
 106     switch (offset) {
 107     case RTC_DR:
 108         return pl031_get_count(s);
 109     case RTC_MR:
 110         return s->mr;
 111     case RTC_IMSC:
 112         return s->im;
 113     case RTC_RIS:
 114         return s->is;
 115     case RTC_LR:
 116         return s->lr;
 117     case RTC_CR:
 118         /* RTC is permanently enabled.  */
 119         return 1;
 120     case RTC_MIS:
 121         return s->is & s->im;
 122     case RTC_ICR:
 123         qemu_log_mask(LOG_GUEST_ERROR,
 124                       "pl031: read of write-only register at offset 0x%x\n",
 125                       (int)offset);
 126         break;
 127     default:
 128         qemu_log_mask(LOG_GUEST_ERROR,
 129                       "pl031_read: Bad offset 0x%x\n", (int)offset);
 130         break;
 131     }
 132
 133     return 0;
 134 }
 135
 136 static void pl031_write(void * opaque, hwaddr offset,
 137                         uint64_t value, unsigned size)
 138 {
 139     pl031_state *s = (pl031_state *)opaque;
 140
 141
 142     switch (offset) {
 143     case RTC_LR:
 144         s->tick_offset += value - pl031_get_count(s);
 145         pl031_set_alarm(s);
 146         break;
 147     case RTC_MR:
 148         s->mr = value;
 149         pl031_set_alarm(s);
 150         break;
 151     case RTC_IMSC:
 152         s->im = value & 1;
 153         DPRINTF("Interrupt mask %d\n", s->im);
 154         pl031_update(s);
 155         break;
 156     case RTC_ICR:
 157         /* The PL031 documentation (DDI0224B) states that the interrupt is
 158            cleared when bit 0 of the written value is set.  However the
 159            arm926e documentation (DDI0287B) states that the interrupt is
 160            cleared when any value is written.  */
 161         DPRINTF("Interrupt cleared");
 162         s->is = 0;
 163         pl031_update(s);
 164         break;
 165     case RTC_CR:
 166         /* Written value is ignored.  */
 167         break;
 168
 169     case RTC_DR:
 170     case RTC_MIS:
 171     case RTC_RIS:
 172         qemu_log_mask(LOG_GUEST_ERROR,
 173                       "pl031: write to read-only register at offset 0x%x\n",
 174                       (int)offset);
 175         break;
 176
 177     default:
 178         qemu_log_mask(LOG_GUEST_ERROR,
 179                       "pl031_write: Bad offset 0x%x\n", (int)offset);
 180         break;
 181     }
 182 }
 183
 184 static const MemoryRegionOps pl031_ops = {
 185     .read = pl031_read,
 186     .write = pl031_write,
 187     .endianness = DEVICE_NATIVE_ENDIAN,
 188 };
 189
 190 static int pl031_init(SysBusDevice *dev)
 191 {
 192     pl031_state *s = FROM_SYSBUS(pl031_state, dev);
 193     struct tm tm;
 194
 195     memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
 196     sysbus_init_mmio(dev, &s->iomem);
 197
 198     sysbus_init_irq(dev, &s->irq);
 199     qemu_get_timedate(&tm, 0);
 200     s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
 201
 202     s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
 203     return 0;
 204 }
 205
 206 static void pl031_pre_save(void *opaque)
 207 {
 208     pl031_state *s = opaque;
 209
 210     /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
 211      * store the base time relative to the vm_clock for backwards-compatibility.  */
 212     int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
 213     s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
 214 }
 215
 216 static int pl031_post_load(void *opaque, int version_id)
 217 {
 218     pl031_state *s = opaque;
 219
 220     int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
 221     s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
 222     pl031_set_alarm(s);
 223     return 0;
 224 }
 225
 226 static const VMStateDescription vmstate_pl031 = {
 227     .name = "pl031",
 228     .version_id = 1,
 229     .minimum_version_id = 1,
 230     .pre_save = pl031_pre_save,
 231     .post_load = pl031_post_load,
 232     .fields = (VMStateField[]) {
 233         VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
 234         VMSTATE_UINT32(mr, pl031_state),
 235         VMSTATE_UINT32(lr, pl031_state),
 236         VMSTATE_UINT32(cr, pl031_state),
 237         VMSTATE_UINT32(im, pl031_state),
 238         VMSTATE_UINT32(is, pl031_state),
 239         VMSTATE_END_OF_LIST()
 240     }
 241 };
 242
 243 static void pl031_class_init(ObjectClass *klass, void *data)
 244 {
 245     DeviceClass *dc = DEVICE_CLASS(klass);
 246     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 247
 248     k->init = pl031_init;
 249     dc->no_user = 1;
 250     dc->vmsd = &vmstate_pl031;
 251 }
 252
 253 static const TypeInfo pl031_info = {
 254     .name          = "pl031",
 255     .parent        = TYPE_SYS_BUS_DEVICE,
 256     .instance_size = sizeof(pl031_state),
 257     .class_init    = pl031_class_init,
 258 };
 259
 260 static void pl031_register_types(void)
 261 {
 262     type_register_static(&pl031_info);
 263 }
 264
 265 type_init(pl031_register_types)