2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/sparc/sun4m.h"
26 #include "qemu/timer.h"
27 #include "hw/ptimer.h"
28 #include "hw/sysbus.h"
32 * Registers of hardware timer in sun4m.
34 * This is the timer/counter part of chip STP2001 (Slave I/O), also
35 * produced as NCR89C105. See
36 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
38 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
39 * are zero. Bit 31 is 1 when count has been reached.
41 * Per-CPU timers interrupt local CPU, system timer uses normal
48 typedef struct CPUTimerState
{
51 uint32_t count
, counthigh
, reached
;
57 typedef struct SLAVIO_TIMERState
{
60 uint32_t cputimer_mode
;
61 CPUTimerState cputimer
[MAX_CPUS
+ 1];
64 typedef struct TimerContext
{
67 unsigned int timer_index
; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
70 #define SYS_TIMER_SIZE 0x14
71 #define CPU_TIMER_SIZE 0x10
74 #define TIMER_COUNTER 1
75 #define TIMER_COUNTER_NORST 2
76 #define TIMER_STATUS 3
79 #define TIMER_COUNT_MASK32 0xfffffe00
80 #define TIMER_LIMIT_MASK32 0x7fffffff
81 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
82 #define TIMER_MAX_COUNT32 0x7ffffe00ULL
83 #define TIMER_REACHED 0x80000000
84 #define TIMER_PERIOD 500ULL // 500ns
85 #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
86 #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
88 static int slavio_timer_is_user(TimerContext
*tc
)
90 SLAVIO_TIMERState
*s
= tc
->s
;
91 unsigned int timer_index
= tc
->timer_index
;
93 return timer_index
!= 0 && (s
->cputimer_mode
& (1 << (timer_index
- 1)));
96 // Update count, set irq, update expire_time
97 // Convert from ptimer countdown units
98 static void slavio_timer_get_out(CPUTimerState
*t
)
100 uint64_t count
, limit
;
102 if (t
->limit
== 0) { /* free-run system or processor counter */
103 limit
= TIMER_MAX_COUNT32
;
107 count
= limit
- PERIODS_TO_LIMIT(ptimer_get_count(t
->timer
));
109 trace_slavio_timer_get_out(t
->limit
, t
->counthigh
, t
->count
);
110 t
->count
= count
& TIMER_COUNT_MASK32
;
111 t
->counthigh
= count
>> 32;
115 static void slavio_timer_irq(void *opaque
)
117 TimerContext
*tc
= opaque
;
118 SLAVIO_TIMERState
*s
= tc
->s
;
119 CPUTimerState
*t
= &s
->cputimer
[tc
->timer_index
];
121 slavio_timer_get_out(t
);
122 trace_slavio_timer_irq(t
->counthigh
, t
->count
);
123 /* if limit is 0 (free-run), there will be no match */
125 t
->reached
= TIMER_REACHED
;
127 /* there is no interrupt if user timer or free-run */
128 if (!slavio_timer_is_user(tc
) && t
->limit
!= 0) {
129 qemu_irq_raise(t
->irq
);
133 static uint64_t slavio_timer_mem_readl(void *opaque
, hwaddr addr
,
136 TimerContext
*tc
= opaque
;
137 SLAVIO_TIMERState
*s
= tc
->s
;
139 unsigned int timer_index
= tc
->timer_index
;
140 CPUTimerState
*t
= &s
->cputimer
[timer_index
];
145 // read limit (system counter mode) or read most signifying
146 // part of counter (user mode)
147 if (slavio_timer_is_user(tc
)) {
148 // read user timer MSW
149 slavio_timer_get_out(t
);
150 ret
= t
->counthigh
| t
->reached
;
154 qemu_irq_lower(t
->irq
);
156 ret
= t
->limit
& TIMER_LIMIT_MASK32
;
160 // read counter and reached bit (system mode) or read lsbits
161 // of counter (user mode)
162 slavio_timer_get_out(t
);
163 if (slavio_timer_is_user(tc
)) { // read user timer LSW
164 ret
= t
->count
& TIMER_MAX_COUNT64
;
165 } else { // read limit
166 ret
= (t
->count
& TIMER_MAX_COUNT32
) |
171 // only available in processor counter/timer
172 // read start/stop status
173 if (timer_index
> 0) {
180 // only available in system counter
181 // read user/system mode
182 ret
= s
->cputimer_mode
;
185 trace_slavio_timer_mem_readl_invalid(addr
);
189 trace_slavio_timer_mem_readl(addr
, ret
);
193 static void slavio_timer_mem_writel(void *opaque
, hwaddr addr
,
194 uint64_t val
, unsigned size
)
196 TimerContext
*tc
= opaque
;
197 SLAVIO_TIMERState
*s
= tc
->s
;
199 unsigned int timer_index
= tc
->timer_index
;
200 CPUTimerState
*t
= &s
->cputimer
[timer_index
];
202 trace_slavio_timer_mem_writel(addr
, val
);
206 if (slavio_timer_is_user(tc
)) {
209 // set user counter MSW, reset counter
210 t
->limit
= TIMER_MAX_COUNT64
;
211 t
->counthigh
= val
& (TIMER_MAX_COUNT64
>> 32);
213 count
= ((uint64_t)t
->counthigh
<< 32) | t
->count
;
214 trace_slavio_timer_mem_writel_limit(timer_index
, count
);
215 ptimer_set_count(t
->timer
, LIMIT_TO_PERIODS(t
->limit
- count
));
217 // set limit, reset counter
218 qemu_irq_lower(t
->irq
);
219 t
->limit
= val
& TIMER_MAX_COUNT32
;
221 if (t
->limit
== 0) { /* free-run */
222 ptimer_set_limit(t
->timer
,
223 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 1);
225 ptimer_set_limit(t
->timer
, LIMIT_TO_PERIODS(t
->limit
), 1);
231 if (slavio_timer_is_user(tc
)) {
234 // set user counter LSW, reset counter
235 t
->limit
= TIMER_MAX_COUNT64
;
236 t
->count
= val
& TIMER_MAX_COUNT64
;
238 count
= ((uint64_t)t
->counthigh
) << 32 | t
->count
;
239 trace_slavio_timer_mem_writel_limit(timer_index
, count
);
240 ptimer_set_count(t
->timer
, LIMIT_TO_PERIODS(t
->limit
- count
));
242 trace_slavio_timer_mem_writel_counter_invalid();
245 case TIMER_COUNTER_NORST
:
246 // set limit without resetting counter
247 t
->limit
= val
& TIMER_MAX_COUNT32
;
248 if (t
->limit
== 0) { /* free-run */
249 ptimer_set_limit(t
->timer
, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 0);
251 ptimer_set_limit(t
->timer
, LIMIT_TO_PERIODS(t
->limit
), 0);
255 if (slavio_timer_is_user(tc
)) {
256 // start/stop user counter
257 if ((val
& 1) && !t
->running
) {
258 trace_slavio_timer_mem_writel_status_start(timer_index
);
259 ptimer_run(t
->timer
, 0);
261 } else if (!(val
& 1) && t
->running
) {
262 trace_slavio_timer_mem_writel_status_stop(timer_index
);
263 ptimer_stop(t
->timer
);
269 if (timer_index
== 0) {
272 for (i
= 0; i
< s
->num_cpus
; i
++) {
273 unsigned int processor
= 1 << i
;
274 CPUTimerState
*curr_timer
= &s
->cputimer
[i
+ 1];
276 // check for a change in timer mode for this processor
277 if ((val
& processor
) != (s
->cputimer_mode
& processor
)) {
278 if (val
& processor
) { // counter -> user timer
279 qemu_irq_lower(curr_timer
->irq
);
280 // counters are always running
281 ptimer_stop(curr_timer
->timer
);
282 curr_timer
->running
= 0;
283 // user timer limit is always the same
284 curr_timer
->limit
= TIMER_MAX_COUNT64
;
285 ptimer_set_limit(curr_timer
->timer
,
286 LIMIT_TO_PERIODS(curr_timer
->limit
),
288 // set this processors user timer bit in config
290 s
->cputimer_mode
|= processor
;
291 trace_slavio_timer_mem_writel_mode_user(timer_index
);
292 } else { // user timer -> counter
293 // stop the user timer if it is running
294 if (curr_timer
->running
) {
295 ptimer_stop(curr_timer
->timer
);
298 ptimer_run(curr_timer
->timer
, 0);
299 curr_timer
->running
= 1;
300 // clear this processors user timer bit in config
302 s
->cputimer_mode
&= ~processor
;
303 trace_slavio_timer_mem_writel_mode_counter(timer_index
);
308 trace_slavio_timer_mem_writel_mode_invalid();
312 trace_slavio_timer_mem_writel_invalid(addr
);
317 static const MemoryRegionOps slavio_timer_mem_ops
= {
318 .read
= slavio_timer_mem_readl
,
319 .write
= slavio_timer_mem_writel
,
320 .endianness
= DEVICE_NATIVE_ENDIAN
,
322 .min_access_size
= 4,
323 .max_access_size
= 4,
327 static const VMStateDescription vmstate_timer
= {
330 .minimum_version_id
= 3,
331 .minimum_version_id_old
= 3,
332 .fields
= (VMStateField
[]) {
333 VMSTATE_UINT64(limit
, CPUTimerState
),
334 VMSTATE_UINT32(count
, CPUTimerState
),
335 VMSTATE_UINT32(counthigh
, CPUTimerState
),
336 VMSTATE_UINT32(reached
, CPUTimerState
),
337 VMSTATE_UINT32(running
, CPUTimerState
),
338 VMSTATE_PTIMER(timer
, CPUTimerState
),
339 VMSTATE_END_OF_LIST()
343 static const VMStateDescription vmstate_slavio_timer
= {
344 .name
="slavio_timer",
346 .minimum_version_id
= 3,
347 .minimum_version_id_old
= 3,
348 .fields
= (VMStateField
[]) {
349 VMSTATE_STRUCT_ARRAY(cputimer
, SLAVIO_TIMERState
, MAX_CPUS
+ 1, 3,
350 vmstate_timer
, CPUTimerState
),
351 VMSTATE_END_OF_LIST()
355 static void slavio_timer_reset(DeviceState
*d
)
357 SLAVIO_TIMERState
*s
= container_of(d
, SLAVIO_TIMERState
, busdev
.qdev
);
359 CPUTimerState
*curr_timer
;
361 for (i
= 0; i
<= MAX_CPUS
; i
++) {
362 curr_timer
= &s
->cputimer
[i
];
363 curr_timer
->limit
= 0;
364 curr_timer
->count
= 0;
365 curr_timer
->reached
= 0;
366 if (i
<= s
->num_cpus
) {
367 ptimer_set_limit(curr_timer
->timer
,
368 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 1);
369 ptimer_run(curr_timer
->timer
, 0);
370 curr_timer
->running
= 1;
373 s
->cputimer_mode
= 0;
376 static int slavio_timer_init1(SysBusDevice
*dev
)
378 SLAVIO_TIMERState
*s
= FROM_SYSBUS(SLAVIO_TIMERState
, dev
);
383 for (i
= 0; i
<= MAX_CPUS
; i
++) {
387 tc
= g_malloc0(sizeof(TimerContext
));
391 bh
= qemu_bh_new(slavio_timer_irq
, tc
);
392 s
->cputimer
[i
].timer
= ptimer_init(bh
);
393 ptimer_set_period(s
->cputimer
[i
].timer
, TIMER_PERIOD
);
395 size
= i
== 0 ? SYS_TIMER_SIZE
: CPU_TIMER_SIZE
;
396 snprintf(timer_name
, sizeof(timer_name
), "timer-%i", i
);
397 memory_region_init_io(&tc
->iomem
, &slavio_timer_mem_ops
, tc
,
399 sysbus_init_mmio(dev
, &tc
->iomem
);
401 sysbus_init_irq(dev
, &s
->cputimer
[i
].irq
);
407 static Property slavio_timer_properties
[] = {
408 DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState
, num_cpus
, 0),
409 DEFINE_PROP_END_OF_LIST(),
412 static void slavio_timer_class_init(ObjectClass
*klass
, void *data
)
414 DeviceClass
*dc
= DEVICE_CLASS(klass
);
415 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
417 k
->init
= slavio_timer_init1
;
418 dc
->reset
= slavio_timer_reset
;
419 dc
->vmsd
= &vmstate_slavio_timer
;
420 dc
->props
= slavio_timer_properties
;
423 static const TypeInfo slavio_timer_info
= {
424 .name
= "slavio_timer",
425 .parent
= TYPE_SYS_BUS_DEVICE
,
426 .instance_size
= sizeof(SLAVIO_TIMERState
),
427 .class_init
= slavio_timer_class_init
,
430 static void slavio_timer_register_types(void)
432 type_register_static(&slavio_timer_info
);
435 type_init(slavio_timer_register_types
)