hw/pci-bridge/ioh3420.c

   1 /*
   2  * ioh3420.c
   3  * Intel X58 north bridge IOH
   4  * PCI Express root port device id 3420
   5  *
   6  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   7  *                    VA Linux Systems Japan K.K.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw/pci/pci_ids.h"
  24 #include "hw/pci/msi.h"
  25 #include "hw/pci/pcie.h"
  26 #include "ioh3420.h"
  27
  28 #define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
  29 #define PCI_DEVICE_ID_IOH_REV           0x2
  30 #define IOH_EP_SSVID_OFFSET             0x40
  31 #define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
  32 #define IOH_EP_SSVID_SSID               0
  33 #define IOH_EP_MSI_OFFSET               0x60
  34 #define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
  35 #define IOH_EP_MSI_NR_VECTOR            2
  36 #define IOH_EP_EXP_OFFSET               0x90
  37 #define IOH_EP_AER_OFFSET               0x100
  38
  39 /*
  40  * If two MSI vector are allocated, Advanced Error Interrupt Message Number
  41  * is 1. otherwise 0.
  42  * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
  43  */
  44 static uint8_t ioh3420_aer_vector(const PCIDevice *d)
  45 {
  46     switch (msi_nr_vectors_allocated(d)) {
  47     case 1:
  48         return 0;
  49     case 2:
  50         return 1;
  51     case 4:
  52     case 8:
  53     case 16:
  54     case 32:
  55     default:
  56         break;
  57     }
  58     abort();
  59     return 0;
  60 }
  61
  62 static void ioh3420_aer_vector_update(PCIDevice *d)
  63 {
  64     pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
  65 }
  66
  67 static void ioh3420_write_config(PCIDevice *d,
  68                                    uint32_t address, uint32_t val, int len)
  69 {
  70     uint32_t root_cmd =
  71         pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
  72
  73     pci_bridge_write_config(d, address, val, len);
  74     ioh3420_aer_vector_update(d);
  75     pcie_cap_slot_write_config(d, address, val, len);
  76     pcie_aer_write_config(d, address, val, len);
  77     pcie_aer_root_write_config(d, address, val, len, root_cmd);
  78 }
  79
  80 static void ioh3420_reset(DeviceState *qdev)
  81 {
  82     PCIDevice *d = PCI_DEVICE(qdev);
  83
  84     ioh3420_aer_vector_update(d);
  85     pcie_cap_root_reset(d);
  86     pcie_cap_deverr_reset(d);
  87     pcie_cap_slot_reset(d);
  88     pcie_cap_arifwd_reset(d);
  89     pcie_aer_root_reset(d);
  90     pci_bridge_reset(qdev);
  91     pci_bridge_disable_base_limit(d);
  92 }
  93
  94 static int ioh3420_initfn(PCIDevice *d)
  95 {
  96     PCIEPort *p = PCIE_PORT(d);
  97     PCIESlot *s = PCIE_SLOT(d);
  98     int rc;
  99
 100     rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
 101     if (rc < 0) {
 102         return rc;
 103     }
 104
 105     pcie_port_init_reg(d);
 106
 107     rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
 108                                IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
 109     if (rc < 0) {
 110         goto err_bridge;
 111     }
 112     rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
 113                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
 114                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
 115     if (rc < 0) {
 116         goto err_bridge;
 117     }
 118     rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
 119     if (rc < 0) {
 120         goto err_msi;
 121     }
 122
 123     pcie_cap_arifwd_init(d);
 124     pcie_cap_deverr_init(d);
 125     pcie_cap_slot_init(d, s->slot);
 126     pcie_chassis_create(s->chassis);
 127     rc = pcie_chassis_add_slot(s);
 128     if (rc < 0) {
 129         goto err_pcie_cap;
 130     }
 131     pcie_cap_root_init(d);
 132     rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
 133     if (rc < 0) {
 134         goto err;
 135     }
 136     pcie_aer_root_init(d);
 137     ioh3420_aer_vector_update(d);
 138     return 0;
 139
 140 err:
 141     pcie_chassis_del_slot(s);
 142 err_pcie_cap:
 143     pcie_cap_exit(d);
 144 err_msi:
 145     msi_uninit(d);
 146 err_bridge:
 147     pci_bridge_exitfn(d);
 148     return rc;
 149 }
 150
 151 static void ioh3420_exitfn(PCIDevice *d)
 152 {
 153     PCIESlot *s = PCIE_SLOT(d);
 154
 155     pcie_aer_exit(d);
 156     pcie_chassis_del_slot(s);
 157     pcie_cap_exit(d);
 158     msi_uninit(d);
 159     pci_bridge_exitfn(d);
 160 }
 161
 162 static Property ioh3420_props[] = {
 163     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
 164                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
 165     DEFINE_PROP_END_OF_LIST()
 166 };
 167
 168 static const VMStateDescription vmstate_ioh3420 = {
 169     .name = "ioh-3240-express-root-port",
 170     .version_id = 1,
 171     .minimum_version_id = 1,
 172     .post_load = pcie_cap_slot_post_load,
 173     .fields = (VMStateField[]) {
 174         VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 175         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 176                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 177         VMSTATE_END_OF_LIST()
 178     }
 179 };
 180
 181 static void ioh3420_class_init(ObjectClass *klass, void *data)
 182 {
 183     DeviceClass *dc = DEVICE_CLASS(klass);
 184     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 185
 186     k->is_express = 1;
 187     k->is_bridge = 1;
 188     k->config_write = ioh3420_write_config;
 189     k->init = ioh3420_initfn;
 190     k->exit = ioh3420_exitfn;
 191     k->vendor_id = PCI_VENDOR_ID_INTEL;
 192     k->device_id = PCI_DEVICE_ID_IOH_EPORT;
 193     k->revision = PCI_DEVICE_ID_IOH_REV;
 194     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 195     dc->desc = "Intel IOH device id 3420 PCIE Root Port";
 196     dc->reset = ioh3420_reset;
 197     dc->vmsd = &vmstate_ioh3420;
 198     dc->props = ioh3420_props;
 199 }
 200
 201 static const TypeInfo ioh3420_info = {
 202     .name          = "ioh3420",
 203     .parent        = TYPE_PCIE_SLOT,
 204     .class_init    = ioh3420_class_init,
 205 };
 206
 207 static void ioh3420_register_types(void)
 208 {
 209     type_register_static(&ioh3420_info);
 210 }
 211
 212 type_init(ioh3420_register_types)
 213
 214 /*
 215  * Local variables:
 216  *  c-indent-level: 4
 217  *  c-basic-offset: 4
 218  *  tab-width: 8
 219  *  indent-tab-mode: nil
 220  * End:
 221  */