hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licensed under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "i2c.h"
  21 #include "blockdev.h"
  22 #include "exec-memory.h"
  23
  24 #define MP_MISC_BASE            0x80002000
  25 #define MP_MISC_SIZE            0x00001000
  26
  27 #define MP_ETH_BASE             0x80008000
  28 #define MP_ETH_SIZE             0x00001000
  29
  30 #define MP_WLAN_BASE            0x8000C000
  31 #define MP_WLAN_SIZE            0x00000800
  32
  33 #define MP_UART1_BASE           0x8000C840
  34 #define MP_UART2_BASE           0x8000C940
  35
  36 #define MP_GPIO_BASE            0x8000D000
  37 #define MP_GPIO_SIZE            0x00001000
  38
  39 #define MP_FLASHCFG_BASE        0x90006000
  40 #define MP_FLASHCFG_SIZE        0x00001000
  41
  42 #define MP_AUDIO_BASE           0x90007000
  43
  44 #define MP_PIC_BASE             0x90008000
  45 #define MP_PIC_SIZE             0x00001000
  46
  47 #define MP_PIT_BASE             0x90009000
  48 #define MP_PIT_SIZE             0x00001000
  49
  50 #define MP_LCD_BASE             0x9000c000
  51 #define MP_LCD_SIZE             0x00001000
  52
  53 #define MP_SRAM_BASE            0xC0000000
  54 #define MP_SRAM_SIZE            0x00020000
  55
  56 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  57 #define MP_FLASH_SIZE_MAX       32*1024*1024
  58
  59 #define MP_TIMER1_IRQ           4
  60 #define MP_TIMER2_IRQ           5
  61 #define MP_TIMER3_IRQ           6
  62 #define MP_TIMER4_IRQ           7
  63 #define MP_EHCI_IRQ             8
  64 #define MP_ETH_IRQ              9
  65 #define MP_UART1_IRQ            11
  66 #define MP_UART2_IRQ            11
  67 #define MP_GPIO_IRQ             12
  68 #define MP_RTC_IRQ              28
  69 #define MP_AUDIO_IRQ            30
  70
  71 /* Wolfson 8750 I2C address */
  72 #define MP_WM_ADDR              0x1A
  73
  74 /* Ethernet register offsets */
  75 #define MP_ETH_SMIR             0x010
  76 #define MP_ETH_PCXR             0x408
  77 #define MP_ETH_SDCMR            0x448
  78 #define MP_ETH_ICR              0x450
  79 #define MP_ETH_IMR              0x458
  80 #define MP_ETH_FRDP0            0x480
  81 #define MP_ETH_FRDP1            0x484
  82 #define MP_ETH_FRDP2            0x488
  83 #define MP_ETH_FRDP3            0x48C
  84 #define MP_ETH_CRDP0            0x4A0
  85 #define MP_ETH_CRDP1            0x4A4
  86 #define MP_ETH_CRDP2            0x4A8
  87 #define MP_ETH_CRDP3            0x4AC
  88 #define MP_ETH_CTDP0            0x4E0
  89 #define MP_ETH_CTDP1            0x4E4
  90 #define MP_ETH_CTDP2            0x4E8
  91 #define MP_ETH_CTDP3            0x4EC
  92
  93 /* MII PHY access */
  94 #define MP_ETH_SMIR_DATA        0x0000FFFF
  95 #define MP_ETH_SMIR_ADDR        0x03FF0000
  96 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
  97 #define MP_ETH_SMIR_RDVALID     (1 << 27)
  98
  99 /* PHY registers */
 100 #define MP_ETH_PHY1_BMSR        0x00210000
 101 #define MP_ETH_PHY1_PHYSID1     0x00410000
 102 #define MP_ETH_PHY1_PHYSID2     0x00610000
 103
 104 #define MP_PHY_BMSR_LINK        0x0004
 105 #define MP_PHY_BMSR_AUTONEG     0x0008
 106
 107 #define MP_PHY_88E3015          0x01410E20
 108
 109 /* TX descriptor status */
 110 #define MP_ETH_TX_OWN           (1 << 31)
 111
 112 /* RX descriptor status */
 113 #define MP_ETH_RX_OWN           (1 << 31)
 114
 115 /* Interrupt cause/mask bits */
 116 #define MP_ETH_IRQ_RX_BIT       0
 117 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 118 #define MP_ETH_IRQ_TXHI_BIT     2
 119 #define MP_ETH_IRQ_TXLO_BIT     3
 120
 121 /* Port config bits */
 122 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 123
 124 /* SDMA command bits */
 125 #define MP_ETH_CMD_TXHI         (1 << 23)
 126 #define MP_ETH_CMD_TXLO         (1 << 22)
 127
 128 typedef struct mv88w8618_tx_desc {
 129     uint32_t cmdstat;
 130     uint16_t res;
 131     uint16_t bytes;
 132     uint32_t buffer;
 133     uint32_t next;
 134 } mv88w8618_tx_desc;
 135
 136 typedef struct mv88w8618_rx_desc {
 137     uint32_t cmdstat;
 138     uint16_t bytes;
 139     uint16_t buffer_size;
 140     uint32_t buffer;
 141     uint32_t next;
 142 } mv88w8618_rx_desc;
 143
 144 typedef struct mv88w8618_eth_state {
 145     SysBusDevice busdev;
 146     MemoryRegion iomem;
 147     qemu_irq irq;
 148     uint32_t smir;
 149     uint32_t icr;
 150     uint32_t imr;
 151     int mmio_index;
 152     uint32_t vlan_header;
 153     uint32_t tx_queue[2];
 154     uint32_t rx_queue[4];
 155     uint32_t frx_queue[4];
 156     uint32_t cur_rx[4];
 157     NICState *nic;
 158     NICConf conf;
 159 } mv88w8618_eth_state;
 160
 161 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 162 {
 163     cpu_to_le32s(&desc->cmdstat);
 164     cpu_to_le16s(&desc->bytes);
 165     cpu_to_le16s(&desc->buffer_size);
 166     cpu_to_le32s(&desc->buffer);
 167     cpu_to_le32s(&desc->next);
 168     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 169 }
 170
 171 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 172 {
 173     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 174     le32_to_cpus(&desc->cmdstat);
 175     le16_to_cpus(&desc->bytes);
 176     le16_to_cpus(&desc->buffer_size);
 177     le32_to_cpus(&desc->buffer);
 178     le32_to_cpus(&desc->next);
 179 }
 180
 181 static int eth_can_receive(VLANClientState *nc)
 182 {
 183     return 1;
 184 }
 185
 186 static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
 187 {
 188     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 189     uint32_t desc_addr;
 190     mv88w8618_rx_desc desc;
 191     int i;
 192
 193     for (i = 0; i < 4; i++) {
 194         desc_addr = s->cur_rx[i];
 195         if (!desc_addr) {
 196             continue;
 197         }
 198         do {
 199             eth_rx_desc_get(desc_addr, &desc);
 200             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 201                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 202                                           buf, size);
 203                 desc.bytes = size + s->vlan_header;
 204                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 205                 s->cur_rx[i] = desc.next;
 206
 207                 s->icr |= MP_ETH_IRQ_RX;
 208                 if (s->icr & s->imr) {
 209                     qemu_irq_raise(s->irq);
 210                 }
 211                 eth_rx_desc_put(desc_addr, &desc);
 212                 return size;
 213             }
 214             desc_addr = desc.next;
 215         } while (desc_addr != s->rx_queue[i]);
 216     }
 217     return size;
 218 }
 219
 220 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 221 {
 222     cpu_to_le32s(&desc->cmdstat);
 223     cpu_to_le16s(&desc->res);
 224     cpu_to_le16s(&desc->bytes);
 225     cpu_to_le32s(&desc->buffer);
 226     cpu_to_le32s(&desc->next);
 227     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 228 }
 229
 230 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 231 {
 232     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 233     le32_to_cpus(&desc->cmdstat);
 234     le16_to_cpus(&desc->res);
 235     le16_to_cpus(&desc->bytes);
 236     le32_to_cpus(&desc->buffer);
 237     le32_to_cpus(&desc->next);
 238 }
 239
 240 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 241 {
 242     uint32_t desc_addr = s->tx_queue[queue_index];
 243     mv88w8618_tx_desc desc;
 244     uint32_t next_desc;
 245     uint8_t buf[2048];
 246     int len;
 247
 248     do {
 249         eth_tx_desc_get(desc_addr, &desc);
 250         next_desc = desc.next;
 251         if (desc.cmdstat & MP_ETH_TX_OWN) {
 252             len = desc.bytes;
 253             if (len < 2048) {
 254                 cpu_physical_memory_read(desc.buffer, buf, len);
 255                 qemu_send_packet(&s->nic->nc, buf, len);
 256             }
 257             desc.cmdstat &= ~MP_ETH_TX_OWN;
 258             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 259             eth_tx_desc_put(desc_addr, &desc);
 260         }
 261         desc_addr = next_desc;
 262     } while (desc_addr != s->tx_queue[queue_index]);
 263 }
 264
 265 static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
 266                                    unsigned size)
 267 {
 268     mv88w8618_eth_state *s = opaque;
 269
 270     switch (offset) {
 271     case MP_ETH_SMIR:
 272         if (s->smir & MP_ETH_SMIR_OPCODE) {
 273             switch (s->smir & MP_ETH_SMIR_ADDR) {
 274             case MP_ETH_PHY1_BMSR:
 275                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 276                        MP_ETH_SMIR_RDVALID;
 277             case MP_ETH_PHY1_PHYSID1:
 278                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 279             case MP_ETH_PHY1_PHYSID2:
 280                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 281             default:
 282                 return MP_ETH_SMIR_RDVALID;
 283             }
 284         }
 285         return 0;
 286
 287     case MP_ETH_ICR:
 288         return s->icr;
 289
 290     case MP_ETH_IMR:
 291         return s->imr;
 292
 293     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 294         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 295
 296     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 297         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 298
 299     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 300         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 301
 302     default:
 303         return 0;
 304     }
 305 }
 306
 307 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 308                                 uint64_t value, unsigned size)
 309 {
 310     mv88w8618_eth_state *s = opaque;
 311
 312     switch (offset) {
 313     case MP_ETH_SMIR:
 314         s->smir = value;
 315         break;
 316
 317     case MP_ETH_PCXR:
 318         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 319         break;
 320
 321     case MP_ETH_SDCMR:
 322         if (value & MP_ETH_CMD_TXHI) {
 323             eth_send(s, 1);
 324         }
 325         if (value & MP_ETH_CMD_TXLO) {
 326             eth_send(s, 0);
 327         }
 328         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 329             qemu_irq_raise(s->irq);
 330         }
 331         break;
 332
 333     case MP_ETH_ICR:
 334         s->icr &= value;
 335         break;
 336
 337     case MP_ETH_IMR:
 338         s->imr = value;
 339         if (s->icr & s->imr) {
 340             qemu_irq_raise(s->irq);
 341         }
 342         break;
 343
 344     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 345         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 346         break;
 347
 348     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 349         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 350             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 351         break;
 352
 353     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 354         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 355         break;
 356     }
 357 }
 358
 359 static const MemoryRegionOps mv88w8618_eth_ops = {
 360     .read = mv88w8618_eth_read,
 361     .write = mv88w8618_eth_write,
 362     .endianness = DEVICE_NATIVE_ENDIAN,
 363 };
 364
 365 static void eth_cleanup(VLANClientState *nc)
 366 {
 367     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 368
 369     s->nic = NULL;
 370 }
 371
 372 static NetClientInfo net_mv88w8618_info = {
 373     .type = NET_CLIENT_TYPE_NIC,
 374     .size = sizeof(NICState),
 375     .can_receive = eth_can_receive,
 376     .receive = eth_receive,
 377     .cleanup = eth_cleanup,
 378 };
 379
 380 static int mv88w8618_eth_init(SysBusDevice *dev)
 381 {
 382     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 383
 384     sysbus_init_irq(dev, &s->irq);
 385     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 386                           dev->qdev.info->name, dev->qdev.id, s);
 387     memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
 388                           MP_ETH_SIZE);
 389     sysbus_init_mmio(dev, &s->iomem);
 390     return 0;
 391 }
 392
 393 static const VMStateDescription mv88w8618_eth_vmsd = {
 394     .name = "mv88w8618_eth",
 395     .version_id = 1,
 396     .minimum_version_id = 1,
 397     .minimum_version_id_old = 1,
 398     .fields = (VMStateField[]) {
 399         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 400         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 401         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 402         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 403         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 404         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 405         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 406         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 407         VMSTATE_END_OF_LIST()
 408     }
 409 };
 410
 411 static SysBusDeviceInfo mv88w8618_eth_info = {
 412     .init = mv88w8618_eth_init,
 413     .qdev.name = "mv88w8618_eth",
 414     .qdev.size = sizeof(mv88w8618_eth_state),
 415     .qdev.vmsd = &mv88w8618_eth_vmsd,
 416     .qdev.props = (Property[]) {
 417         DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 418         DEFINE_PROP_END_OF_LIST(),
 419     },
 420 };
 421
 422 /* LCD register offsets */
 423 #define MP_LCD_IRQCTRL          0x180
 424 #define MP_LCD_IRQSTAT          0x184
 425 #define MP_LCD_SPICTRL          0x1ac
 426 #define MP_LCD_INST             0x1bc
 427 #define MP_LCD_DATA             0x1c0
 428
 429 /* Mode magics */
 430 #define MP_LCD_SPI_DATA         0x00100011
 431 #define MP_LCD_SPI_CMD          0x00104011
 432 #define MP_LCD_SPI_INVALID      0x00000000
 433
 434 /* Commmands */
 435 #define MP_LCD_INST_SETPAGE0    0xB0
 436 /* ... */
 437 #define MP_LCD_INST_SETPAGE7    0xB7
 438
 439 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 440
 441 typedef struct musicpal_lcd_state {
 442     SysBusDevice busdev;
 443     MemoryRegion iomem;
 444     uint32_t brightness;
 445     uint32_t mode;
 446     uint32_t irqctrl;
 447     uint32_t page;
 448     uint32_t page_off;
 449     DisplayState *ds;
 450     uint8_t video_ram[128*64/8];
 451 } musicpal_lcd_state;
 452
 453 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 454 {
 455     switch (s->brightness) {
 456     case 7:
 457         return col;
 458     case 0:
 459         return 0;
 460     default:
 461         return (col * s->brightness) / 7;
 462     }
 463 }
 464
 465 #define SET_LCD_PIXEL(depth, type) \
 466 static inline void glue(set_lcd_pixel, depth) \
 467         (musicpal_lcd_state *s, int x, int y, type col) \
 468 { \
 469     int dx, dy; \
 470     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 471 \
 472     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 473         for (dx = 0; dx < 3; dx++, pixel++) \
 474             *pixel = col; \
 475 }
 476 SET_LCD_PIXEL(8, uint8_t)
 477 SET_LCD_PIXEL(16, uint16_t)
 478 SET_LCD_PIXEL(32, uint32_t)
 479
 480 #include "pixel_ops.h"
 481
 482 static void lcd_refresh(void *opaque)
 483 {
 484     musicpal_lcd_state *s = opaque;
 485     int x, y, col;
 486
 487     switch (ds_get_bits_per_pixel(s->ds)) {
 488     case 0:
 489         return;
 490 #define LCD_REFRESH(depth, func) \
 491     case depth: \
 492         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 493                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 494                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 495         for (x = 0; x < 128; x++) { \
 496             for (y = 0; y < 64; y++) { \
 497                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 498                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 499                 } else { \
 500                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 501                 } \
 502             } \
 503         } \
 504         break;
 505     LCD_REFRESH(8, rgb_to_pixel8)
 506     LCD_REFRESH(16, rgb_to_pixel16)
 507     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 508                      rgb_to_pixel32bgr : rgb_to_pixel32))
 509     default:
 510         hw_error("unsupported colour depth %i\n",
 511                   ds_get_bits_per_pixel(s->ds));
 512     }
 513
 514     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 515 }
 516
 517 static void lcd_invalidate(void *opaque)
 518 {
 519 }
 520
 521 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 522 {
 523     musicpal_lcd_state *s = opaque;
 524     s->brightness &= ~(1 << irq);
 525     s->brightness |= level << irq;
 526 }
 527
 528 static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
 529                                   unsigned size)
 530 {
 531     musicpal_lcd_state *s = opaque;
 532
 533     switch (offset) {
 534     case MP_LCD_IRQCTRL:
 535         return s->irqctrl;
 536
 537     default:
 538         return 0;
 539     }
 540 }
 541
 542 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 543                                uint64_t value, unsigned size)
 544 {
 545     musicpal_lcd_state *s = opaque;
 546
 547     switch (offset) {
 548     case MP_LCD_IRQCTRL:
 549         s->irqctrl = value;
 550         break;
 551
 552     case MP_LCD_SPICTRL:
 553         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 554             s->mode = value;
 555         } else {
 556             s->mode = MP_LCD_SPI_INVALID;
 557         }
 558         break;
 559
 560     case MP_LCD_INST:
 561         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 562             s->page = value - MP_LCD_INST_SETPAGE0;
 563             s->page_off = 0;
 564         }
 565         break;
 566
 567     case MP_LCD_DATA:
 568         if (s->mode == MP_LCD_SPI_CMD) {
 569             if (value >= MP_LCD_INST_SETPAGE0 &&
 570                 value <= MP_LCD_INST_SETPAGE7) {
 571                 s->page = value - MP_LCD_INST_SETPAGE0;
 572                 s->page_off = 0;
 573             }
 574         } else if (s->mode == MP_LCD_SPI_DATA) {
 575             s->video_ram[s->page*128 + s->page_off] = value;
 576             s->page_off = (s->page_off + 1) & 127;
 577         }
 578         break;
 579     }
 580 }
 581
 582 static const MemoryRegionOps musicpal_lcd_ops = {
 583     .read = musicpal_lcd_read,
 584     .write = musicpal_lcd_write,
 585     .endianness = DEVICE_NATIVE_ENDIAN,
 586 };
 587
 588 static int musicpal_lcd_init(SysBusDevice *dev)
 589 {
 590     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 591
 592     s->brightness = 7;
 593
 594     memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
 595                           "musicpal-lcd", MP_LCD_SIZE);
 596     sysbus_init_mmio(dev, &s->iomem);
 597
 598     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 599                                  NULL, NULL, s);
 600     qemu_console_resize(s->ds, 128*3, 64*3);
 601
 602     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 603
 604     return 0;
 605 }
 606
 607 static const VMStateDescription musicpal_lcd_vmsd = {
 608     .name = "musicpal_lcd",
 609     .version_id = 1,
 610     .minimum_version_id = 1,
 611     .minimum_version_id_old = 1,
 612     .fields = (VMStateField[]) {
 613         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 614         VMSTATE_UINT32(mode, musicpal_lcd_state),
 615         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 616         VMSTATE_UINT32(page, musicpal_lcd_state),
 617         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 618         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 619         VMSTATE_END_OF_LIST()
 620     }
 621 };
 622
 623 static SysBusDeviceInfo musicpal_lcd_info = {
 624     .init = musicpal_lcd_init,
 625     .qdev.name = "musicpal_lcd",
 626     .qdev.size = sizeof(musicpal_lcd_state),
 627     .qdev.vmsd = &musicpal_lcd_vmsd,
 628 };
 629
 630 /* PIC register offsets */
 631 #define MP_PIC_STATUS           0x00
 632 #define MP_PIC_ENABLE_SET       0x08
 633 #define MP_PIC_ENABLE_CLR       0x0C
 634
 635 typedef struct mv88w8618_pic_state
 636 {
 637     SysBusDevice busdev;
 638     MemoryRegion iomem;
 639     uint32_t level;
 640     uint32_t enabled;
 641     qemu_irq parent_irq;
 642 } mv88w8618_pic_state;
 643
 644 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 645 {
 646     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 647 }
 648
 649 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 650 {
 651     mv88w8618_pic_state *s = opaque;
 652
 653     if (level) {
 654         s->level |= 1 << irq;
 655     } else {
 656         s->level &= ~(1 << irq);
 657     }
 658     mv88w8618_pic_update(s);
 659 }
 660
 661 static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
 662                                    unsigned size)
 663 {
 664     mv88w8618_pic_state *s = opaque;
 665
 666     switch (offset) {
 667     case MP_PIC_STATUS:
 668         return s->level & s->enabled;
 669
 670     default:
 671         return 0;
 672     }
 673 }
 674
 675 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 676                                 uint64_t value, unsigned size)
 677 {
 678     mv88w8618_pic_state *s = opaque;
 679
 680     switch (offset) {
 681     case MP_PIC_ENABLE_SET:
 682         s->enabled |= value;
 683         break;
 684
 685     case MP_PIC_ENABLE_CLR:
 686         s->enabled &= ~value;
 687         s->level &= ~value;
 688         break;
 689     }
 690     mv88w8618_pic_update(s);
 691 }
 692
 693 static void mv88w8618_pic_reset(DeviceState *d)
 694 {
 695     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
 696                                          sysbus_from_qdev(d));
 697
 698     s->level = 0;
 699     s->enabled = 0;
 700 }
 701
 702 static const MemoryRegionOps mv88w8618_pic_ops = {
 703     .read = mv88w8618_pic_read,
 704     .write = mv88w8618_pic_write,
 705     .endianness = DEVICE_NATIVE_ENDIAN,
 706 };
 707
 708 static int mv88w8618_pic_init(SysBusDevice *dev)
 709 {
 710     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 711
 712     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 713     sysbus_init_irq(dev, &s->parent_irq);
 714     memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
 715                           "musicpal-pic", MP_PIC_SIZE);
 716     sysbus_init_mmio(dev, &s->iomem);
 717     return 0;
 718 }
 719
 720 static const VMStateDescription mv88w8618_pic_vmsd = {
 721     .name = "mv88w8618_pic",
 722     .version_id = 1,
 723     .minimum_version_id = 1,
 724     .minimum_version_id_old = 1,
 725     .fields = (VMStateField[]) {
 726         VMSTATE_UINT32(level, mv88w8618_pic_state),
 727         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 728         VMSTATE_END_OF_LIST()
 729     }
 730 };
 731
 732 static SysBusDeviceInfo mv88w8618_pic_info = {
 733     .init = mv88w8618_pic_init,
 734     .qdev.name = "mv88w8618_pic",
 735     .qdev.size = sizeof(mv88w8618_pic_state),
 736     .qdev.reset = mv88w8618_pic_reset,
 737     .qdev.vmsd = &mv88w8618_pic_vmsd,
 738 };
 739
 740 /* PIT register offsets */
 741 #define MP_PIT_TIMER1_LENGTH    0x00
 742 /* ... */
 743 #define MP_PIT_TIMER4_LENGTH    0x0C
 744 #define MP_PIT_CONTROL          0x10
 745 #define MP_PIT_TIMER1_VALUE     0x14
 746 /* ... */
 747 #define MP_PIT_TIMER4_VALUE     0x20
 748 #define MP_BOARD_RESET          0x34
 749
 750 /* Magic board reset value (probably some watchdog behind it) */
 751 #define MP_BOARD_RESET_MAGIC    0x10000
 752
 753 typedef struct mv88w8618_timer_state {
 754     ptimer_state *ptimer;
 755     uint32_t limit;
 756     int freq;
 757     qemu_irq irq;
 758 } mv88w8618_timer_state;
 759
 760 typedef struct mv88w8618_pit_state {
 761     SysBusDevice busdev;
 762     MemoryRegion iomem;
 763     mv88w8618_timer_state timer[4];
 764 } mv88w8618_pit_state;
 765
 766 static void mv88w8618_timer_tick(void *opaque)
 767 {
 768     mv88w8618_timer_state *s = opaque;
 769
 770     qemu_irq_raise(s->irq);
 771 }
 772
 773 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 774                                  uint32_t freq)
 775 {
 776     QEMUBH *bh;
 777
 778     sysbus_init_irq(dev, &s->irq);
 779     s->freq = freq;
 780
 781     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 782     s->ptimer = ptimer_init(bh);
 783 }
 784
 785 static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
 786                                    unsigned size)
 787 {
 788     mv88w8618_pit_state *s = opaque;
 789     mv88w8618_timer_state *t;
 790
 791     switch (offset) {
 792     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 793         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 794         return ptimer_get_count(t->ptimer);
 795
 796     default:
 797         return 0;
 798     }
 799 }
 800
 801 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 802                                 uint64_t value, unsigned size)
 803 {
 804     mv88w8618_pit_state *s = opaque;
 805     mv88w8618_timer_state *t;
 806     int i;
 807
 808     switch (offset) {
 809     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 810         t = &s->timer[offset >> 2];
 811         t->limit = value;
 812         if (t->limit > 0) {
 813             ptimer_set_limit(t->ptimer, t->limit, 1);
 814         } else {
 815             ptimer_stop(t->ptimer);
 816         }
 817         break;
 818
 819     case MP_PIT_CONTROL:
 820         for (i = 0; i < 4; i++) {
 821             t = &s->timer[i];
 822             if (value & 0xf && t->limit > 0) {
 823                 ptimer_set_limit(t->ptimer, t->limit, 0);
 824                 ptimer_set_freq(t->ptimer, t->freq);
 825                 ptimer_run(t->ptimer, 0);
 826             } else {
 827                 ptimer_stop(t->ptimer);
 828             }
 829             value >>= 4;
 830         }
 831         break;
 832
 833     case MP_BOARD_RESET:
 834         if (value == MP_BOARD_RESET_MAGIC) {
 835             qemu_system_reset_request();
 836         }
 837         break;
 838     }
 839 }
 840
 841 static void mv88w8618_pit_reset(DeviceState *d)
 842 {
 843     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
 844                                          sysbus_from_qdev(d));
 845     int i;
 846
 847     for (i = 0; i < 4; i++) {
 848         ptimer_stop(s->timer[i].ptimer);
 849         s->timer[i].limit = 0;
 850     }
 851 }
 852
 853 static const MemoryRegionOps mv88w8618_pit_ops = {
 854     .read = mv88w8618_pit_read,
 855     .write = mv88w8618_pit_write,
 856     .endianness = DEVICE_NATIVE_ENDIAN,
 857 };
 858
 859 static int mv88w8618_pit_init(SysBusDevice *dev)
 860 {
 861     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 862     int i;
 863
 864     /* Letting them all run at 1 MHz is likely just a pragmatic
 865      * simplification. */
 866     for (i = 0; i < 4; i++) {
 867         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 868     }
 869
 870     memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
 871                           "musicpal-pit", MP_PIT_SIZE);
 872     sysbus_init_mmio(dev, &s->iomem);
 873     return 0;
 874 }
 875
 876 static const VMStateDescription mv88w8618_timer_vmsd = {
 877     .name = "timer",
 878     .version_id = 1,
 879     .minimum_version_id = 1,
 880     .minimum_version_id_old = 1,
 881     .fields = (VMStateField[]) {
 882         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 883         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 884         VMSTATE_END_OF_LIST()
 885     }
 886 };
 887
 888 static const VMStateDescription mv88w8618_pit_vmsd = {
 889     .name = "mv88w8618_pit",
 890     .version_id = 1,
 891     .minimum_version_id = 1,
 892     .minimum_version_id_old = 1,
 893     .fields = (VMStateField[]) {
 894         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 895                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 896         VMSTATE_END_OF_LIST()
 897     }
 898 };
 899
 900 static SysBusDeviceInfo mv88w8618_pit_info = {
 901     .init = mv88w8618_pit_init,
 902     .qdev.name  = "mv88w8618_pit",
 903     .qdev.size  = sizeof(mv88w8618_pit_state),
 904     .qdev.reset = mv88w8618_pit_reset,
 905     .qdev.vmsd  = &mv88w8618_pit_vmsd,
 906 };
 907
 908 /* Flash config register offsets */
 909 #define MP_FLASHCFG_CFGR0    0x04
 910
 911 typedef struct mv88w8618_flashcfg_state {
 912     SysBusDevice busdev;
 913     MemoryRegion iomem;
 914     uint32_t cfgr0;
 915 } mv88w8618_flashcfg_state;
 916
 917 static uint64_t mv88w8618_flashcfg_read(void *opaque,
 918                                         target_phys_addr_t offset,
 919                                         unsigned size)
 920 {
 921     mv88w8618_flashcfg_state *s = opaque;
 922
 923     switch (offset) {
 924     case MP_FLASHCFG_CFGR0:
 925         return s->cfgr0;
 926
 927     default:
 928         return 0;
 929     }
 930 }
 931
 932 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 933                                      uint64_t value, unsigned size)
 934 {
 935     mv88w8618_flashcfg_state *s = opaque;
 936
 937     switch (offset) {
 938     case MP_FLASHCFG_CFGR0:
 939         s->cfgr0 = value;
 940         break;
 941     }
 942 }
 943
 944 static const MemoryRegionOps mv88w8618_flashcfg_ops = {
 945     .read = mv88w8618_flashcfg_read,
 946     .write = mv88w8618_flashcfg_write,
 947     .endianness = DEVICE_NATIVE_ENDIAN,
 948 };
 949
 950 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 951 {
 952     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 953
 954     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 955     memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
 956                           "musicpal-flashcfg", MP_FLASHCFG_SIZE);
 957     sysbus_init_mmio(dev, &s->iomem);
 958     return 0;
 959 }
 960
 961 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
 962     .name = "mv88w8618_flashcfg",
 963     .version_id = 1,
 964     .minimum_version_id = 1,
 965     .minimum_version_id_old = 1,
 966     .fields = (VMStateField[]) {
 967         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
 968         VMSTATE_END_OF_LIST()
 969     }
 970 };
 971
 972 static SysBusDeviceInfo mv88w8618_flashcfg_info = {
 973     .init = mv88w8618_flashcfg_init,
 974     .qdev.name  = "mv88w8618_flashcfg",
 975     .qdev.size  = sizeof(mv88w8618_flashcfg_state),
 976     .qdev.vmsd  = &mv88w8618_flashcfg_vmsd,
 977 };
 978
 979 /* Misc register offsets */
 980 #define MP_MISC_BOARD_REVISION  0x18
 981
 982 #define MP_BOARD_REVISION       0x31
 983
 984 static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
 985                                    unsigned size)
 986 {
 987     switch (offset) {
 988     case MP_MISC_BOARD_REVISION:
 989         return MP_BOARD_REVISION;
 990
 991     default:
 992         return 0;
 993     }
 994 }
 995
 996 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
 997                                 uint64_t value, unsigned size)
 998 {
 999 }
1000
1001 static const MemoryRegionOps musicpal_misc_ops = {
1002     .read = musicpal_misc_read,
1003     .write = musicpal_misc_write,
1004     .endianness = DEVICE_NATIVE_ENDIAN,
1005 };
1006
1007 static void musicpal_misc_init(SysBusDevice *dev)
1008 {
1009     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1010
1011     memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
1012                           "musicpal-misc", MP_MISC_SIZE);
1013     sysbus_add_memory(dev, MP_MISC_BASE, iomem);
1014 }
1015
1016 /* WLAN register offsets */
1017 #define MP_WLAN_MAGIC1          0x11c
1018 #define MP_WLAN_MAGIC2          0x124
1019
1020 static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
1021                                     unsigned size)
1022 {
1023     switch (offset) {
1024     /* Workaround to allow loading the binary-only wlandrv.ko crap
1025      * from the original Freecom firmware. */
1026     case MP_WLAN_MAGIC1:
1027         return ~3;
1028     case MP_WLAN_MAGIC2:
1029         return -1;
1030
1031     default:
1032         return 0;
1033     }
1034 }
1035
1036 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1037                                  uint64_t value, unsigned size)
1038 {
1039 }
1040
1041 static const MemoryRegionOps mv88w8618_wlan_ops = {
1042     .read = mv88w8618_wlan_read,
1043     .write =mv88w8618_wlan_write,
1044     .endianness = DEVICE_NATIVE_ENDIAN,
1045 };
1046
1047 static int mv88w8618_wlan_init(SysBusDevice *dev)
1048 {
1049     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1050
1051     memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
1052                           "musicpal-wlan", MP_WLAN_SIZE);
1053     sysbus_init_mmio(dev, iomem);
1054     return 0;
1055 }
1056
1057 /* GPIO register offsets */
1058 #define MP_GPIO_OE_LO           0x008
1059 #define MP_GPIO_OUT_LO          0x00c
1060 #define MP_GPIO_IN_LO           0x010
1061 #define MP_GPIO_IER_LO          0x014
1062 #define MP_GPIO_IMR_LO          0x018
1063 #define MP_GPIO_ISR_LO          0x020
1064 #define MP_GPIO_OE_HI           0x508
1065 #define MP_GPIO_OUT_HI          0x50c
1066 #define MP_GPIO_IN_HI           0x510
1067 #define MP_GPIO_IER_HI          0x514
1068 #define MP_GPIO_IMR_HI          0x518
1069 #define MP_GPIO_ISR_HI          0x520
1070
1071 /* GPIO bits & masks */
1072 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1073 #define MP_GPIO_I2C_DATA_BIT    29
1074 #define MP_GPIO_I2C_CLOCK_BIT   30
1075
1076 /* LCD brightness bits in GPIO_OE_HI */
1077 #define MP_OE_LCD_BRIGHTNESS    0x0007
1078
1079 typedef struct musicpal_gpio_state {
1080     SysBusDevice busdev;
1081     MemoryRegion iomem;
1082     uint32_t lcd_brightness;
1083     uint32_t out_state;
1084     uint32_t in_state;
1085     uint32_t ier;
1086     uint32_t imr;
1087     uint32_t isr;
1088     qemu_irq irq;
1089     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1090 } musicpal_gpio_state;
1091
1092 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1093     int i;
1094     uint32_t brightness;
1095
1096     /* compute brightness ratio */
1097     switch (s->lcd_brightness) {
1098     case 0x00000007:
1099         brightness = 0;
1100         break;
1101
1102     case 0x00020000:
1103         brightness = 1;
1104         break;
1105
1106     case 0x00020001:
1107         brightness = 2;
1108         break;
1109
1110     case 0x00040000:
1111         brightness = 3;
1112         break;
1113
1114     case 0x00010006:
1115         brightness = 4;
1116         break;
1117
1118     case 0x00020005:
1119         brightness = 5;
1120         break;
1121
1122     case 0x00040003:
1123         brightness = 6;
1124         break;
1125
1126     case 0x00030004:
1127     default:
1128         brightness = 7;
1129     }
1130
1131     /* set lcd brightness GPIOs  */
1132     for (i = 0; i <= 2; i++) {
1133         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1134     }
1135 }
1136
1137 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1138 {
1139     musicpal_gpio_state *s = opaque;
1140     uint32_t mask = 1 << pin;
1141     uint32_t delta = level << pin;
1142     uint32_t old = s->in_state & mask;
1143
1144     s->in_state &= ~mask;
1145     s->in_state |= delta;
1146
1147     if ((old ^ delta) &&
1148         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1149         s->isr = mask;
1150         qemu_irq_raise(s->irq);
1151     }
1152 }
1153
1154 static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
1155                                    unsigned size)
1156 {
1157     musicpal_gpio_state *s = opaque;
1158
1159     switch (offset) {
1160     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1161         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1162
1163     case MP_GPIO_OUT_LO:
1164         return s->out_state & 0xFFFF;
1165     case MP_GPIO_OUT_HI:
1166         return s->out_state >> 16;
1167
1168     case MP_GPIO_IN_LO:
1169         return s->in_state & 0xFFFF;
1170     case MP_GPIO_IN_HI:
1171         return s->in_state >> 16;
1172
1173     case MP_GPIO_IER_LO:
1174         return s->ier & 0xFFFF;
1175     case MP_GPIO_IER_HI:
1176         return s->ier >> 16;
1177
1178     case MP_GPIO_IMR_LO:
1179         return s->imr & 0xFFFF;
1180     case MP_GPIO_IMR_HI:
1181         return s->imr >> 16;
1182
1183     case MP_GPIO_ISR_LO:
1184         return s->isr & 0xFFFF;
1185     case MP_GPIO_ISR_HI:
1186         return s->isr >> 16;
1187
1188     default:
1189         return 0;
1190     }
1191 }
1192
1193 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1194                                 uint64_t value, unsigned size)
1195 {
1196     musicpal_gpio_state *s = opaque;
1197     switch (offset) {
1198     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1199         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1200                          (value & MP_OE_LCD_BRIGHTNESS);
1201         musicpal_gpio_brightness_update(s);
1202         break;
1203
1204     case MP_GPIO_OUT_LO:
1205         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1206         break;
1207     case MP_GPIO_OUT_HI:
1208         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1209         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1210                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1211         musicpal_gpio_brightness_update(s);
1212         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1213         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1214         break;
1215
1216     case MP_GPIO_IER_LO:
1217         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1218         break;
1219     case MP_GPIO_IER_HI:
1220         s->ier = (s->ier & 0xFFFF) | (value << 16);
1221         break;
1222
1223     case MP_GPIO_IMR_LO:
1224         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1225         break;
1226     case MP_GPIO_IMR_HI:
1227         s->imr = (s->imr & 0xFFFF) | (value << 16);
1228         break;
1229     }
1230 }
1231
1232 static const MemoryRegionOps musicpal_gpio_ops = {
1233     .read = musicpal_gpio_read,
1234     .write = musicpal_gpio_write,
1235     .endianness = DEVICE_NATIVE_ENDIAN,
1236 };
1237
1238 static void musicpal_gpio_reset(DeviceState *d)
1239 {
1240     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1241                                          sysbus_from_qdev(d));
1242
1243     s->lcd_brightness = 0;
1244     s->out_state = 0;
1245     s->in_state = 0xffffffff;
1246     s->ier = 0;
1247     s->imr = 0;
1248     s->isr = 0;
1249 }
1250
1251 static int musicpal_gpio_init(SysBusDevice *dev)
1252 {
1253     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1254
1255     sysbus_init_irq(dev, &s->irq);
1256
1257     memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
1258                           "musicpal-gpio", MP_GPIO_SIZE);
1259     sysbus_init_mmio(dev, &s->iomem);
1260
1261     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1262
1263     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1264
1265     return 0;
1266 }
1267
1268 static const VMStateDescription musicpal_gpio_vmsd = {
1269     .name = "musicpal_gpio",
1270     .version_id = 1,
1271     .minimum_version_id = 1,
1272     .minimum_version_id_old = 1,
1273     .fields = (VMStateField[]) {
1274         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1275         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1276         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1277         VMSTATE_UINT32(ier, musicpal_gpio_state),
1278         VMSTATE_UINT32(imr, musicpal_gpio_state),
1279         VMSTATE_UINT32(isr, musicpal_gpio_state),
1280         VMSTATE_END_OF_LIST()
1281     }
1282 };
1283
1284 static SysBusDeviceInfo musicpal_gpio_info = {
1285     .init = musicpal_gpio_init,
1286     .qdev.name  = "musicpal_gpio",
1287     .qdev.size  = sizeof(musicpal_gpio_state),
1288     .qdev.reset = musicpal_gpio_reset,
1289     .qdev.vmsd  = &musicpal_gpio_vmsd,
1290 };
1291
1292 /* Keyboard codes & masks */
1293 #define KEY_RELEASED            0x80
1294 #define KEY_CODE                0x7f
1295
1296 #define KEYCODE_TAB             0x0f
1297 #define KEYCODE_ENTER           0x1c
1298 #define KEYCODE_F               0x21
1299 #define KEYCODE_M               0x32
1300
1301 #define KEYCODE_EXTENDED        0xe0
1302 #define KEYCODE_UP              0x48
1303 #define KEYCODE_DOWN            0x50
1304 #define KEYCODE_LEFT            0x4b
1305 #define KEYCODE_RIGHT           0x4d
1306
1307 #define MP_KEY_WHEEL_VOL       (1 << 0)
1308 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1309 #define MP_KEY_WHEEL_NAV       (1 << 2)
1310 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1311 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1312 #define MP_KEY_BTN_MENU        (1 << 5)
1313 #define MP_KEY_BTN_VOLUME      (1 << 6)
1314 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1315
1316 typedef struct musicpal_key_state {
1317     SysBusDevice busdev;
1318     MemoryRegion iomem;
1319     uint32_t kbd_extended;
1320     uint32_t pressed_keys;
1321     qemu_irq out[8];
1322 } musicpal_key_state;
1323
1324 static void musicpal_key_event(void *opaque, int keycode)
1325 {
1326     musicpal_key_state *s = opaque;
1327     uint32_t event = 0;
1328     int i;
1329
1330     if (keycode == KEYCODE_EXTENDED) {
1331         s->kbd_extended = 1;
1332         return;
1333     }
1334
1335     if (s->kbd_extended) {
1336         switch (keycode & KEY_CODE) {
1337         case KEYCODE_UP:
1338             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1339             break;
1340
1341         case KEYCODE_DOWN:
1342             event = MP_KEY_WHEEL_NAV;
1343             break;
1344
1345         case KEYCODE_LEFT:
1346             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1347             break;
1348
1349         case KEYCODE_RIGHT:
1350             event = MP_KEY_WHEEL_VOL;
1351             break;
1352         }
1353     } else {
1354         switch (keycode & KEY_CODE) {
1355         case KEYCODE_F:
1356             event = MP_KEY_BTN_FAVORITS;
1357             break;
1358
1359         case KEYCODE_TAB:
1360             event = MP_KEY_BTN_VOLUME;
1361             break;
1362
1363         case KEYCODE_ENTER:
1364             event = MP_KEY_BTN_NAVIGATION;
1365             break;
1366
1367         case KEYCODE_M:
1368             event = MP_KEY_BTN_MENU;
1369             break;
1370         }
1371         /* Do not repeat already pressed buttons */
1372         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1373             event = 0;
1374         }
1375     }
1376
1377     if (event) {
1378         /* Raise GPIO pin first if repeating a key */
1379         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1380             for (i = 0; i <= 7; i++) {
1381                 if (event & (1 << i)) {
1382                     qemu_set_irq(s->out[i], 1);
1383                 }
1384             }
1385         }
1386         for (i = 0; i <= 7; i++) {
1387             if (event & (1 << i)) {
1388                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1389             }
1390         }
1391         if (keycode & KEY_RELEASED) {
1392             s->pressed_keys &= ~event;
1393         } else {
1394             s->pressed_keys |= event;
1395         }
1396     }
1397
1398     s->kbd_extended = 0;
1399 }
1400
1401 static int musicpal_key_init(SysBusDevice *dev)
1402 {
1403     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1404
1405     memory_region_init(&s->iomem, "dummy", 0);
1406     sysbus_init_mmio(dev, &s->iomem);
1407
1408     s->kbd_extended = 0;
1409     s->pressed_keys = 0;
1410
1411     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1412
1413     qemu_add_kbd_event_handler(musicpal_key_event, s);
1414
1415     return 0;
1416 }
1417
1418 static const VMStateDescription musicpal_key_vmsd = {
1419     .name = "musicpal_key",
1420     .version_id = 1,
1421     .minimum_version_id = 1,
1422     .minimum_version_id_old = 1,
1423     .fields = (VMStateField[]) {
1424         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1425         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1426         VMSTATE_END_OF_LIST()
1427     }
1428 };
1429
1430 static SysBusDeviceInfo musicpal_key_info = {
1431     .init = musicpal_key_init,
1432     .qdev.name  = "musicpal_key",
1433     .qdev.size  = sizeof(musicpal_key_state),
1434     .qdev.vmsd  = &musicpal_key_vmsd,
1435 };
1436
1437 static struct arm_boot_info musicpal_binfo = {
1438     .loader_start = 0x0,
1439     .board_id = 0x20e,
1440 };
1441
1442 static void musicpal_init(ram_addr_t ram_size,
1443                const char *boot_device,
1444                const char *kernel_filename, const char *kernel_cmdline,
1445                const char *initrd_filename, const char *cpu_model)
1446 {
1447     CPUState *env;
1448     qemu_irq *cpu_pic;
1449     qemu_irq pic[32];
1450     DeviceState *dev;
1451     DeviceState *i2c_dev;
1452     DeviceState *lcd_dev;
1453     DeviceState *key_dev;
1454     DeviceState *wm8750_dev;
1455     SysBusDevice *s;
1456     i2c_bus *i2c;
1457     int i;
1458     unsigned long flash_size;
1459     DriveInfo *dinfo;
1460     MemoryRegion *address_space_mem = get_system_memory();
1461     MemoryRegion *ram = g_new(MemoryRegion, 1);
1462     MemoryRegion *sram = g_new(MemoryRegion, 1);
1463
1464     if (!cpu_model) {
1465         cpu_model = "arm926";
1466     }
1467     env = cpu_init(cpu_model);
1468     if (!env) {
1469         fprintf(stderr, "Unable to find CPU definition\n");
1470         exit(1);
1471     }
1472     cpu_pic = arm_pic_init_cpu(env);
1473
1474     /* For now we use a fixed - the original - RAM size */
1475     memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
1476     memory_region_add_subregion(address_space_mem, 0, ram);
1477
1478     memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE);
1479     memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
1480
1481     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1482                                cpu_pic[ARM_PIC_CPU_IRQ]);
1483     for (i = 0; i < 32; i++) {
1484         pic[i] = qdev_get_gpio_in(dev, i);
1485     }
1486     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1487                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1488                           pic[MP_TIMER4_IRQ], NULL);
1489
1490     if (serial_hds[0]) {
1491         serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1492                        1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
1493     }
1494     if (serial_hds[1]) {
1495         serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1496                        1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
1497     }
1498
1499     /* Register flash */
1500     dinfo = drive_get(IF_PFLASH, 0, 0);
1501     if (dinfo) {
1502         flash_size = bdrv_getlength(dinfo->bdrv);
1503         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1504             flash_size != 32*1024*1024) {
1505             fprintf(stderr, "Invalid flash image size\n");
1506             exit(1);
1507         }
1508
1509         /*
1510          * The original U-Boot accesses the flash at 0xFE000000 instead of
1511          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1512          * image is smaller than 32 MB.
1513          */
1514 #ifdef TARGET_WORDS_BIGENDIAN
1515         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1516                               "musicpal.flash", flash_size,
1517                               dinfo->bdrv, 0x10000,
1518                               (flash_size + 0xffff) >> 16,
1519                               MP_FLASH_SIZE_MAX / flash_size,
1520                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1521                               0x5555, 0x2AAA, 1);
1522 #else
1523         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1524                               "musicpal.flash", flash_size,
1525                               dinfo->bdrv, 0x10000,
1526                               (flash_size + 0xffff) >> 16,
1527                               MP_FLASH_SIZE_MAX / flash_size,
1528                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1529                               0x5555, 0x2AAA, 0);
1530 #endif
1531
1532     }
1533     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1534
1535     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1536     dev = qdev_create(NULL, "mv88w8618_eth");
1537     qdev_set_nic_properties(dev, &nd_table[0]);
1538     qdev_init_nofail(dev);
1539     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1540     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1541
1542     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1543
1544     musicpal_misc_init(sysbus_from_qdev(dev));
1545
1546     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1547     i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1548     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1549
1550     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1551     key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
1552
1553     /* I2C read data */
1554     qdev_connect_gpio_out(i2c_dev, 0,
1555                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1556     /* I2C data */
1557     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1558     /* I2C clock */
1559     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1560
1561     for (i = 0; i < 3; i++) {
1562         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1563     }
1564     for (i = 0; i < 4; i++) {
1565         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1566     }
1567     for (i = 4; i < 8; i++) {
1568         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1569     }
1570
1571     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1572     dev = qdev_create(NULL, "mv88w8618_audio");
1573     s = sysbus_from_qdev(dev);
1574     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1575     qdev_init_nofail(dev);
1576     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1577     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1578
1579     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1580     musicpal_binfo.kernel_filename = kernel_filename;
1581     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1582     musicpal_binfo.initrd_filename = initrd_filename;
1583     arm_load_kernel(env, &musicpal_binfo);
1584 }
1585
1586 static QEMUMachine musicpal_machine = {
1587     .name = "musicpal",
1588     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1589     .init = musicpal_init,
1590 };
1591
1592 static void musicpal_machine_init(void)
1593 {
1594     qemu_register_machine(&musicpal_machine);
1595 }
1596
1597 machine_init(musicpal_machine_init);
1598
1599 static void musicpal_register_devices(void)
1600 {
1601     sysbus_register_withprop(&mv88w8618_pic_info);
1602     sysbus_register_withprop(&mv88w8618_pit_info);
1603     sysbus_register_withprop(&mv88w8618_flashcfg_info);
1604     sysbus_register_withprop(&mv88w8618_eth_info);
1605     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1606                         mv88w8618_wlan_init);
1607     sysbus_register_withprop(&musicpal_lcd_info);
1608     sysbus_register_withprop(&musicpal_gpio_info);
1609     sysbus_register_withprop(&musicpal_key_info);
1610 }
1611
1612 device_init(musicpal_register_devices)