hw/spapr_pci.c

   1 /*
   2  * QEMU sPAPR PCI host originated from Uninorth PCI host
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
   5  * Copyright (C) 2011 David Gibson, IBM Corporation.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "hw/spapr.h"
  29 #include "hw/spapr_pci.h"
  30 #include "exec-memory.h"
  31 #include <libfdt.h>
  32
  33 #include "hw/pci_internals.h"
  34
  35 static const uint32_t bars[] = {
  36     PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
  37     PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
  38     PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
  39     /*, PCI_ROM_ADDRESS*/
  40 };
  41
  42 static PCIDevice *find_dev(sPAPREnvironment *spapr,
  43                            uint64_t buid, uint32_t config_addr)
  44 {
  45     DeviceState *qdev;
  46     int devfn = (config_addr >> 8) & 0xFF;
  47     sPAPRPHBState *phb;
  48
  49     QLIST_FOREACH(phb, &spapr->phbs, list) {
  50         if (phb->buid != buid) {
  51             continue;
  52         }
  53
  54         QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
  55             PCIDevice *dev = (PCIDevice *)qdev;
  56             if (dev->devfn == devfn) {
  57                 return dev;
  58             }
  59         }
  60     }
  61
  62     return NULL;
  63 }
  64
  65 static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
  66                                      uint32_t token, uint32_t nargs,
  67                                      target_ulong args,
  68                                      uint32_t nret, target_ulong rets)
  69 {
  70     uint32_t val, size, addr;
  71     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
  72     PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
  73
  74     if (!dev) {
  75         rtas_st(rets, 0, -1);
  76         return;
  77     }
  78     size = rtas_ld(args, 3);
  79     addr = rtas_ld(args, 0) & 0xFF;
  80     val = pci_default_read_config(dev, addr, size);
  81     rtas_st(rets, 0, 0);
  82     rtas_st(rets, 1, val);
  83 }
  84
  85 static void rtas_read_pci_config(sPAPREnvironment *spapr,
  86                                  uint32_t token, uint32_t nargs,
  87                                  target_ulong args,
  88                                  uint32_t nret, target_ulong rets)
  89 {
  90     uint32_t val, size, addr;
  91     PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
  92
  93     if (!dev) {
  94         rtas_st(rets, 0, -1);
  95         return;
  96     }
  97     size = rtas_ld(args, 1);
  98     addr = rtas_ld(args, 0) & 0xFF;
  99     val = pci_default_read_config(dev, addr, size);
 100     rtas_st(rets, 0, 0);
 101     rtas_st(rets, 1, val);
 102 }
 103
 104 static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
 105                                       uint32_t token, uint32_t nargs,
 106                                       target_ulong args,
 107                                       uint32_t nret, target_ulong rets)
 108 {
 109     uint32_t val, size, addr;
 110     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 111     PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
 112
 113     if (!dev) {
 114         rtas_st(rets, 0, -1);
 115         return;
 116     }
 117     val = rtas_ld(args, 4);
 118     size = rtas_ld(args, 3);
 119     addr = rtas_ld(args, 0) & 0xFF;
 120     pci_default_write_config(dev, addr, val, size);
 121     rtas_st(rets, 0, 0);
 122 }
 123
 124 static void rtas_write_pci_config(sPAPREnvironment *spapr,
 125                                   uint32_t token, uint32_t nargs,
 126                                   target_ulong args,
 127                                   uint32_t nret, target_ulong rets)
 128 {
 129     uint32_t val, size, addr;
 130     PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
 131
 132     if (!dev) {
 133         rtas_st(rets, 0, -1);
 134         return;
 135     }
 136     val = rtas_ld(args, 2);
 137     size = rtas_ld(args, 1);
 138     addr = rtas_ld(args, 0) & 0xFF;
 139     pci_default_write_config(dev, addr, val, size);
 140     rtas_st(rets, 0, 0);
 141 }
 142
 143 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
 144 {
 145     /*
 146      * Here we need to convert pci_dev + irq_num to some unique value
 147      * which is less than number of IRQs on the specific bus (now it
 148      * is 16).  At the moment irq_num == device_id (number of the
 149      * slot?)
 150      * FIXME: we should swizzle in fn and irq_num
 151      */
 152     return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
 153 }
 154
 155 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
 156 {
 157     /*
 158      * Here we use the number returned by pci_spapr_map_irq to find a
 159      * corresponding qemu_irq.
 160      */
 161     sPAPRPHBState *phb = opaque;
 162
 163     qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
 164 }
 165
 166 static int spapr_phb_init(SysBusDevice *s)
 167 {
 168     sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
 169     int i;
 170
 171     /* Initialize the LSI table */
 172     for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
 173         qemu_irq qirq;
 174         uint32_t num;
 175
 176         qirq = spapr_allocate_irq(0, &num);
 177         if (!qirq) {
 178             return -1;
 179         }
 180
 181         phb->lsi_table[i].dt_irq = num;
 182         phb->lsi_table[i].qirq = qirq;
 183     }
 184
 185     return 0;
 186 }
 187
 188 static int spapr_main_pci_host_init(PCIDevice *d)
 189 {
 190     return 0;
 191 }
 192
 193 static PCIDeviceInfo spapr_main_pci_host_info = {
 194     .qdev.name = "spapr-pci-host-bridge",
 195     .qdev.size = sizeof(PCIDevice),
 196     .init      = spapr_main_pci_host_init,
 197 };
 198
 199 static void spapr_register_devices(void)
 200 {
 201     sysbus_register_dev("spapr-pci-host-bridge", sizeof(sPAPRPHBState),
 202                         spapr_phb_init);
 203     pci_qdev_register(&spapr_main_pci_host_info);
 204 }
 205
 206 device_init(spapr_register_devices)
 207
 208 static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
 209                               unsigned size)
 210 {
 211     switch (size) {
 212     case 1:
 213         return cpu_inb(addr);
 214     case 2:
 215         return cpu_inw(addr);
 216     case 4:
 217         return cpu_inl(addr);
 218     }
 219     assert(0);
 220 }
 221
 222 static void spapr_io_write(void *opaque, target_phys_addr_t addr,
 223                            uint64_t data, unsigned size)
 224 {
 225     switch (size) {
 226     case 1:
 227         cpu_outb(addr, data);
 228         return;
 229     case 2:
 230         cpu_outw(addr, data);
 231         return;
 232     case 4:
 233         cpu_outl(addr, data);
 234         return;
 235     }
 236     assert(0);
 237 }
 238
 239 static MemoryRegionOps spapr_io_ops = {
 240     .endianness = DEVICE_LITTLE_ENDIAN,
 241     .read = spapr_io_read,
 242     .write = spapr_io_write
 243 };
 244
 245 void spapr_create_phb(sPAPREnvironment *spapr,
 246                       const char *busname, uint64_t buid,
 247                       uint64_t mem_win_addr, uint64_t mem_win_size,
 248                       uint64_t io_win_addr)
 249 {
 250     DeviceState *dev;
 251     SysBusDevice *s;
 252     sPAPRPHBState *phb;
 253     PCIBus *bus;
 254     char namebuf[strlen(busname)+11];
 255
 256     dev = qdev_create(NULL, "spapr-pci-host-bridge");
 257     qdev_init_nofail(dev);
 258     s = sysbus_from_qdev(dev);
 259     phb = FROM_SYSBUS(sPAPRPHBState, s);
 260
 261     phb->mem_win_addr = mem_win_addr;
 262
 263     sprintf(namebuf, "%s-mem", busname);
 264     memory_region_init(&phb->memspace, namebuf, INT64_MAX);
 265
 266     sprintf(namebuf, "%s-memwindow", busname);
 267     memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
 268                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
 269     memory_region_add_subregion(get_system_memory(), mem_win_addr,
 270                                 &phb->memwindow);
 271
 272     phb->io_win_addr = io_win_addr;
 273
 274     /* On ppc, we only have MMIO no specific IO space from the CPU
 275      * perspective.  In theory we ought to be able to embed the PCI IO
 276      * memory region direction in the system memory space.  However,
 277      * if any of the IO BAR subregions use the old_portio mechanism,
 278      * that won't be processed properly unless accessed from the
 279      * system io address space.  This hack to bounce things via
 280      * system_io works around the problem until all the users of
 281      * old_portion are updated */
 282     sprintf(namebuf, "%s-io", busname);
 283     memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
 284     /* FIXME: fix to support multiple PHBs */
 285     memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
 286
 287     sprintf(namebuf, "%s-iowindow", busname);
 288     memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
 289                           namebuf, SPAPR_PCI_IO_WIN_SIZE);
 290     memory_region_add_subregion(get_system_memory(), io_win_addr,
 291                                 &phb->iowindow);
 292
 293     phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
 294                                                  pci_spapr_set_irq,
 295                                                  pci_spapr_map_irq,
 296                                                  phb,
 297                                                  &phb->memspace, &phb->iospace,
 298                                                  PCI_DEVFN(0, 0),
 299                                                  SPAPR_PCI_NUM_LSI);
 300
 301     spapr_rtas_register("read-pci-config", rtas_read_pci_config);
 302     spapr_rtas_register("write-pci-config", rtas_write_pci_config);
 303     spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
 304     spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
 305
 306     QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
 307
 308     /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
 309 }
 310
 311 /* Macros to operate with address in OF binding to PCI */
 312 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
 313 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
 314 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
 315 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
 316 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
 317 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
 318 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
 319 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
 320 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
 321
 322 static uint32_t regtype_to_ss(uint8_t type)
 323 {
 324     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 325         return 3;
 326     }
 327     if (type == PCI_BASE_ADDRESS_SPACE_IO) {
 328         return 1;
 329     }
 330     return 2;
 331 }
 332
 333 int spapr_populate_pci_devices(sPAPRPHBState *phb,
 334                                uint32_t xics_phandle,
 335                                void *fdt)
 336 {
 337     PCIBus *bus = phb->host_state.bus;
 338     int bus_off, node_off = 0, devid, fn, i, n, devices;
 339     DeviceState *qdev;
 340     char nodename[256];
 341     struct {
 342         uint32_t hi;
 343         uint64_t addr;
 344         uint64_t size;
 345     } __attribute__((packed)) reg[PCI_NUM_REGIONS + 1],
 346           assigned_addresses[PCI_NUM_REGIONS];
 347     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
 348     struct {
 349         uint32_t hi;
 350         uint64_t child;
 351         uint64_t parent;
 352         uint64_t size;
 353     } __attribute__((packed)) ranges[] = {
 354         {
 355             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
 356             cpu_to_be64(phb->io_win_addr),
 357             cpu_to_be64(memory_region_size(&phb->iospace)),
 358         },
 359         {
 360             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
 361             cpu_to_be64(phb->mem_win_addr),
 362             cpu_to_be64(memory_region_size(&phb->memwindow)),
 363         },
 364     };
 365     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
 366     uint32_t interrupt_map_mask[] = {
 367         cpu_to_be32(b_ddddd(-1)|b_fff(-1)), 0x0, 0x0, 0x0};
 368     uint32_t interrupt_map[bus->nirq][7];
 369
 370     /* Start populating the FDT */
 371     sprintf(nodename, "pci@%" PRIx64, phb->buid);
 372     bus_off = fdt_add_subnode(fdt, 0, nodename);
 373     if (bus_off < 0) {
 374         return bus_off;
 375     }
 376
 377 #define _FDT(exp) \
 378     do { \
 379         int ret = (exp);                                           \
 380         if (ret < 0) {                                             \
 381             return ret;                                            \
 382         }                                                          \
 383     } while (0)
 384
 385     /* Write PHB properties */
 386     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
 387     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
 388     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
 389     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
 390     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
 391     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
 392     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
 393     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
 394     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
 395     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
 396                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
 397
 398     /* Populate PCI devices and allocate IRQs */
 399     devices = 0;
 400     QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
 401         PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
 402         int irq_index = pci_spapr_map_irq(dev, 0);
 403         uint32_t *irqmap = interrupt_map[devices];
 404         uint8_t *config = dev->config;
 405
 406         devid = dev->devfn >> 3;
 407         fn = dev->devfn & 7;
 408
 409         sprintf(nodename, "pci@%u,%u", devid, fn);
 410
 411         /* Allocate interrupt from the map */
 412         if (devid > bus->nirq)  {
 413             printf("Unexpected behaviour in spapr_populate_pci_devices,"
 414                     "wrong devid %u\n", devid);
 415             exit(-1);
 416         }
 417         irqmap[0] = cpu_to_be32(b_ddddd(devid)|b_fff(fn));
 418         irqmap[1] = 0;
 419         irqmap[2] = 0;
 420         irqmap[3] = 0;
 421         irqmap[4] = cpu_to_be32(xics_phandle);
 422         irqmap[5] = cpu_to_be32(phb->lsi_table[irq_index].dt_irq);
 423         irqmap[6] = cpu_to_be32(0x8);
 424
 425         /* Add node to FDT */
 426         node_off = fdt_add_subnode(fdt, bus_off, nodename);
 427         if (node_off < 0) {
 428             return node_off;
 429         }
 430
 431         _FDT(fdt_setprop_cell(fdt, node_off, "vendor-id",
 432                               pci_get_word(&config[PCI_VENDOR_ID])));
 433         _FDT(fdt_setprop_cell(fdt, node_off, "device-id",
 434                               pci_get_word(&config[PCI_DEVICE_ID])));
 435         _FDT(fdt_setprop_cell(fdt, node_off, "revision-id",
 436                               pci_get_byte(&config[PCI_REVISION_ID])));
 437         _FDT(fdt_setprop_cell(fdt, node_off, "class-code",
 438                               pci_get_long(&config[PCI_CLASS_REVISION]) >> 8));
 439         _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-id",
 440                               pci_get_word(&config[PCI_SUBSYSTEM_ID])));
 441         _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-vendor-id",
 442                               pci_get_word(&config[PCI_SUBSYSTEM_VENDOR_ID])));
 443
 444         /* Config space region comes first */
 445         reg[0].hi = cpu_to_be32(
 446             b_n(0) |
 447             b_p(0) |
 448             b_t(0) |
 449             b_ss(0/*config*/) |
 450             b_bbbbbbbb(0) |
 451             b_ddddd(devid) |
 452             b_fff(fn));
 453         reg[0].addr = 0;
 454         reg[0].size = 0;
 455
 456         n = 0;
 457         for (i = 0; i < ARRAY_SIZE(bars); ++i) {
 458             if (0 == dev->io_regions[i].size) {
 459                 continue;
 460             }
 461
 462             reg[n+1].hi = cpu_to_be32(
 463                 b_n(0) |
 464                 b_p(0) |
 465                 b_t(0) |
 466                 b_ss(regtype_to_ss(dev->io_regions[i].type)) |
 467                 b_bbbbbbbb(0) |
 468                 b_ddddd(devid) |
 469                 b_fff(fn) |
 470                 b_rrrrrrrr(bars[i]));
 471             reg[n+1].addr = 0;
 472             reg[n+1].size = cpu_to_be64(dev->io_regions[i].size);
 473
 474             assigned_addresses[n].hi = cpu_to_be32(
 475                 b_n(1) |
 476                 b_p(0) |
 477                 b_t(0) |
 478                 b_ss(regtype_to_ss(dev->io_regions[i].type)) |
 479                 b_bbbbbbbb(0) |
 480                 b_ddddd(devid) |
 481                 b_fff(fn) |
 482                 b_rrrrrrrr(bars[i]));
 483
 484             /*
 485              * Writing zeroes to assigned_addresses causes the guest kernel to
 486              * reassign BARs
 487              */
 488             assigned_addresses[n].addr = cpu_to_be64(dev->io_regions[i].addr);
 489             assigned_addresses[n].size = reg[n+1].size;
 490
 491             ++n;
 492         }
 493         _FDT(fdt_setprop(fdt, node_off, "reg", reg, sizeof(reg[0])*(n+1)));
 494         _FDT(fdt_setprop(fdt, node_off, "assigned-addresses",
 495                          assigned_addresses,
 496                          sizeof(assigned_addresses[0])*(n)));
 497         _FDT(fdt_setprop_cell(fdt, node_off, "interrupts",
 498                               pci_get_byte(&config[PCI_INTERRUPT_PIN])));
 499
 500         ++devices;
 501     }
 502
 503     /* Write interrupt map */
 504     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
 505                      devices * sizeof(interrupt_map[0])));
 506
 507     return 0;
 508 }