hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/i386/pc.h>
  27 #include <hw/pci/pci.h>
  28 #include <hw/isa/isa.h>
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/dma.h"
  31 #include "qemu/error-report.h"
  32 #include <hw/ide/pci.h>
  33
  34 #define BMDMA_PAGE_SIZE 4096
  35
  36 #define BM_MIGRATION_COMPAT_STATUS_BITS \
  37         (IDE_RETRY_DMA | IDE_RETRY_PIO | \
  38         IDE_RETRY_READ | IDE_RETRY_FLUSH)
  39
  40 static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
  41                             BlockCompletionFunc *dma_cb)
  42 {
  43     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  44
  45     bm->dma_cb = dma_cb;
  46     bm->cur_prd_last = 0;
  47     bm->cur_prd_addr = 0;
  48     bm->cur_prd_len = 0;
  49
  50     if (bm->status & BM_STATUS_DMAING) {
  51         bm->dma_cb(bmdma_active_if(bm), 0);
  52     }
  53 }
  54
  55 /**
  56  * Return the number of bytes successfully prepared.
  57  * -1 on error.
  58  */
  59 static int32_t bmdma_prepare_buf(IDEDMA *dma, int is_write)
  60 {
  61     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  62     IDEState *s = bmdma_active_if(bm);
  63     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
  64     struct {
  65         uint32_t addr;
  66         uint32_t size;
  67     } prd;
  68     int l, len;
  69
  70     pci_dma_sglist_init(&s->sg, pci_dev,
  71                         s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
  72     s->io_buffer_size = 0;
  73     for(;;) {
  74         if (bm->cur_prd_len == 0) {
  75             /* end of table (with a fail safe of one page) */
  76             if (bm->cur_prd_last ||
  77                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
  78                 return s->io_buffer_size;
  79             }
  80             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
  81             bm->cur_addr += 8;
  82             prd.addr = le32_to_cpu(prd.addr);
  83             prd.size = le32_to_cpu(prd.size);
  84             len = prd.size & 0xfffe;
  85             if (len == 0)
  86                 len = 0x10000;
  87             bm->cur_prd_len = len;
  88             bm->cur_prd_addr = prd.addr;
  89             bm->cur_prd_last = (prd.size & 0x80000000);
  90         }
  91         l = bm->cur_prd_len;
  92         if (l > 0) {
  93             qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
  94
  95             /* Note: We limit the max transfer to be 2GiB.
  96              * This should accommodate the largest ATA transaction
  97              * for LBA48 (65,536 sectors) and 32K sector sizes. */
  98             if (s->sg.size > INT32_MAX) {
  99                 error_report("IDE: sglist describes more than 2GiB.");
 100                 break;
 101             }
 102             bm->cur_prd_addr += l;
 103             bm->cur_prd_len -= l;
 104             s->io_buffer_size += l;
 105         }
 106     }
 107
 108     qemu_sglist_destroy(&s->sg);
 109     s->io_buffer_size = 0;
 110     return -1;
 111 }
 112
 113 /* return 0 if buffer completed */
 114 static int bmdma_rw_buf(IDEDMA *dma, int is_write)
 115 {
 116     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 117     IDEState *s = bmdma_active_if(bm);
 118     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 119     struct {
 120         uint32_t addr;
 121         uint32_t size;
 122     } prd;
 123     int l, len;
 124
 125     for(;;) {
 126         l = s->io_buffer_size - s->io_buffer_index;
 127         if (l <= 0)
 128             break;
 129         if (bm->cur_prd_len == 0) {
 130             /* end of table (with a fail safe of one page) */
 131             if (bm->cur_prd_last ||
 132                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 133                 return 0;
 134             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
 135             bm->cur_addr += 8;
 136             prd.addr = le32_to_cpu(prd.addr);
 137             prd.size = le32_to_cpu(prd.size);
 138             len = prd.size & 0xfffe;
 139             if (len == 0)
 140                 len = 0x10000;
 141             bm->cur_prd_len = len;
 142             bm->cur_prd_addr = prd.addr;
 143             bm->cur_prd_last = (prd.size & 0x80000000);
 144         }
 145         if (l > bm->cur_prd_len)
 146             l = bm->cur_prd_len;
 147         if (l > 0) {
 148             if (is_write) {
 149                 pci_dma_write(pci_dev, bm->cur_prd_addr,
 150                               s->io_buffer + s->io_buffer_index, l);
 151             } else {
 152                 pci_dma_read(pci_dev, bm->cur_prd_addr,
 153                              s->io_buffer + s->io_buffer_index, l);
 154             }
 155             bm->cur_prd_addr += l;
 156             bm->cur_prd_len -= l;
 157             s->io_buffer_index += l;
 158         }
 159     }
 160     return 1;
 161 }
 162
 163 static void bmdma_set_inactive(IDEDMA *dma, bool more)
 164 {
 165     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 166
 167     bm->dma_cb = NULL;
 168     if (more) {
 169         bm->status |= BM_STATUS_DMAING;
 170     } else {
 171         bm->status &= ~BM_STATUS_DMAING;
 172     }
 173 }
 174
 175 static void bmdma_restart_dma(IDEDMA *dma)
 176 {
 177     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 178
 179     bm->cur_addr = bm->addr;
 180 }
 181
 182 static void bmdma_cancel(BMDMAState *bm)
 183 {
 184     if (bm->status & BM_STATUS_DMAING) {
 185         /* cancel DMA request */
 186         bmdma_set_inactive(&bm->dma, false);
 187     }
 188 }
 189
 190 static void bmdma_reset(IDEDMA *dma)
 191 {
 192     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 193
 194 #ifdef DEBUG_IDE
 195     printf("ide: dma_reset\n");
 196 #endif
 197     bmdma_cancel(bm);
 198     bm->cmd = 0;
 199     bm->status = 0;
 200     bm->addr = 0;
 201     bm->cur_addr = 0;
 202     bm->cur_prd_last = 0;
 203     bm->cur_prd_addr = 0;
 204     bm->cur_prd_len = 0;
 205 }
 206
 207 static void bmdma_irq(void *opaque, int n, int level)
 208 {
 209     BMDMAState *bm = opaque;
 210
 211     if (!level) {
 212         /* pass through lower */
 213         qemu_set_irq(bm->irq, level);
 214         return;
 215     }
 216
 217     bm->status |= BM_STATUS_INT;
 218
 219     /* trigger the real irq */
 220     qemu_set_irq(bm->irq, level);
 221 }
 222
 223 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
 224 {
 225 #ifdef DEBUG_IDE
 226     printf("%s: 0x%08x\n", __func__, val);
 227 #endif
 228
 229     /* Ignore writes to SSBM if it keeps the old value */
 230     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 231         if (!(val & BM_CMD_START)) {
 232             /*
 233              * We can't cancel Scatter Gather DMA in the middle of the
 234              * operation or a partial (not full) DMA transfer would reach
 235              * the storage so we wait for completion instead (we beahve
 236              * like if the DMA was completed by the time the guest trying
 237              * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
 238              * set).
 239              *
 240              * In the future we'll be able to safely cancel the I/O if the
 241              * whole DMA operation will be submitted to disk with a single
 242              * aio operation with preadv/pwritev.
 243              */
 244             if (bm->bus->dma->aiocb) {
 245                 blk_drain_all();
 246                 assert(bm->bus->dma->aiocb == NULL);
 247             }
 248             bm->status &= ~BM_STATUS_DMAING;
 249         } else {
 250             bm->cur_addr = bm->addr;
 251             if (!(bm->status & BM_STATUS_DMAING)) {
 252                 bm->status |= BM_STATUS_DMAING;
 253                 /* start dma transfer if possible */
 254                 if (bm->dma_cb)
 255                     bm->dma_cb(bmdma_active_if(bm), 0);
 256             }
 257         }
 258     }
 259
 260     bm->cmd = val & 0x09;
 261 }
 262
 263 static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
 264                                 unsigned width)
 265 {
 266     BMDMAState *bm = opaque;
 267     uint32_t mask = (1ULL << (width * 8)) - 1;
 268     uint64_t data;
 269
 270     data = (bm->addr >> (addr * 8)) & mask;
 271 #ifdef DEBUG_IDE
 272     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 273 #endif
 274     return data;
 275 }
 276
 277 static void bmdma_addr_write(void *opaque, hwaddr addr,
 278                              uint64_t data, unsigned width)
 279 {
 280     BMDMAState *bm = opaque;
 281     int shift = addr * 8;
 282     uint32_t mask = (1ULL << (width * 8)) - 1;
 283
 284 #ifdef DEBUG_IDE
 285     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 286 #endif
 287     bm->addr &= ~(mask << shift);
 288     bm->addr |= ((data & mask) << shift) & ~3;
 289 }
 290
 291 MemoryRegionOps bmdma_addr_ioport_ops = {
 292     .read = bmdma_addr_read,
 293     .write = bmdma_addr_write,
 294     .endianness = DEVICE_LITTLE_ENDIAN,
 295 };
 296
 297 static bool ide_bmdma_current_needed(void *opaque)
 298 {
 299     BMDMAState *bm = opaque;
 300
 301     return (bm->cur_prd_len != 0);
 302 }
 303
 304 static bool ide_bmdma_status_needed(void *opaque)
 305 {
 306     BMDMAState *bm = opaque;
 307
 308     /* Older versions abused some bits in the status register for internal
 309      * error state. If any of these bits are set, we must add a subsection to
 310      * transfer the real status register */
 311     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 312
 313     return ((bm->status & abused_bits) != 0);
 314 }
 315
 316 static void ide_bmdma_pre_save(void *opaque)
 317 {
 318     BMDMAState *bm = opaque;
 319     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 320
 321     bm->migration_retry_unit = bm->bus->retry_unit;
 322     bm->migration_retry_sector_num = bm->bus->retry_sector_num;
 323     bm->migration_retry_nsector = bm->bus->retry_nsector;
 324     bm->migration_compat_status =
 325         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 326 }
 327
 328 /* This function accesses bm->bus->error_status which is loaded only after
 329  * BMDMA itself. This is why the function is called from ide_pci_post_load
 330  * instead of being registered with VMState where it would run too early. */
 331 static int ide_bmdma_post_load(void *opaque, int version_id)
 332 {
 333     BMDMAState *bm = opaque;
 334     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 335
 336     if (bm->status == 0) {
 337         bm->status = bm->migration_compat_status & ~abused_bits;
 338         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 339     }
 340     if (bm->bus->error_status) {
 341         bm->bus->retry_sector_num = bm->migration_retry_sector_num;
 342         bm->bus->retry_nsector = bm->migration_retry_nsector;
 343         bm->bus->retry_unit = bm->migration_retry_unit;
 344     }
 345
 346     return 0;
 347 }
 348
 349 static const VMStateDescription vmstate_bmdma_current = {
 350     .name = "ide bmdma_current",
 351     .version_id = 1,
 352     .minimum_version_id = 1,
 353     .fields = (VMStateField[]) {
 354         VMSTATE_UINT32(cur_addr, BMDMAState),
 355         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 356         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 357         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 358         VMSTATE_END_OF_LIST()
 359     }
 360 };
 361
 362 static const VMStateDescription vmstate_bmdma_status = {
 363     .name ="ide bmdma/status",
 364     .version_id = 1,
 365     .minimum_version_id = 1,
 366     .fields = (VMStateField[]) {
 367         VMSTATE_UINT8(status, BMDMAState),
 368         VMSTATE_END_OF_LIST()
 369     }
 370 };
 371
 372 static const VMStateDescription vmstate_bmdma = {
 373     .name = "ide bmdma",
 374     .version_id = 3,
 375     .minimum_version_id = 0,
 376     .pre_save  = ide_bmdma_pre_save,
 377     .fields = (VMStateField[]) {
 378         VMSTATE_UINT8(cmd, BMDMAState),
 379         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 380         VMSTATE_UINT32(addr, BMDMAState),
 381         VMSTATE_INT64(migration_retry_sector_num, BMDMAState),
 382         VMSTATE_UINT32(migration_retry_nsector, BMDMAState),
 383         VMSTATE_UINT8(migration_retry_unit, BMDMAState),
 384         VMSTATE_END_OF_LIST()
 385     },
 386     .subsections = (VMStateSubsection []) {
 387         {
 388             .vmsd = &vmstate_bmdma_current,
 389             .needed = ide_bmdma_current_needed,
 390         }, {
 391             .vmsd = &vmstate_bmdma_status,
 392             .needed = ide_bmdma_status_needed,
 393         }, {
 394             /* empty */
 395         }
 396     }
 397 };
 398
 399 static int ide_pci_post_load(void *opaque, int version_id)
 400 {
 401     PCIIDEState *d = opaque;
 402     int i;
 403
 404     for(i = 0; i < 2; i++) {
 405         /* current versions always store 0/1, but older version
 406            stored bigger values. We only need last bit */
 407         d->bmdma[i].migration_retry_unit &= 1;
 408         ide_bmdma_post_load(&d->bmdma[i], -1);
 409     }
 410
 411     return 0;
 412 }
 413
 414 const VMStateDescription vmstate_ide_pci = {
 415     .name = "ide",
 416     .version_id = 3,
 417     .minimum_version_id = 0,
 418     .post_load = ide_pci_post_load,
 419     .fields = (VMStateField[]) {
 420         VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
 421         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 422                              vmstate_bmdma, BMDMAState),
 423         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 424         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 425         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 426         VMSTATE_END_OF_LIST()
 427     }
 428 };
 429
 430 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 431 {
 432     PCIIDEState *d = PCI_IDE(dev);
 433     static const int bus[4]  = { 0, 0, 1, 1 };
 434     static const int unit[4] = { 0, 1, 0, 1 };
 435     int i;
 436
 437     for (i = 0; i < 4; i++) {
 438         if (hd_table[i] == NULL)
 439             continue;
 440         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
 441     }
 442 }
 443
 444 static const struct IDEDMAOps bmdma_ops = {
 445     .start_dma = bmdma_start_dma,
 446     .prepare_buf = bmdma_prepare_buf,
 447     .rw_buf = bmdma_rw_buf,
 448     .restart_dma = bmdma_restart_dma,
 449     .set_inactive = bmdma_set_inactive,
 450     .reset = bmdma_reset,
 451 };
 452
 453 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
 454 {
 455     qemu_irq *irq;
 456
 457     if (bus->dma == &bm->dma) {
 458         return;
 459     }
 460
 461     bm->dma.ops = &bmdma_ops;
 462     bus->dma = &bm->dma;
 463     bm->irq = bus->irq;
 464     irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
 465     bus->irq = *irq;
 466     bm->pci_dev = d;
 467 }
 468
 469 static const TypeInfo pci_ide_type_info = {
 470     .name = TYPE_PCI_IDE,
 471     .parent = TYPE_PCI_DEVICE,
 472     .instance_size = sizeof(PCIIDEState),
 473     .abstract = true,
 474 };
 475
 476 static void pci_ide_register_types(void)
 477 {
 478     type_register_static(&pci_ide_type_info);
 479 }
 480
 481 type_init(pci_ide_register_types)