hw/intc/gic_internal.h

   1 /*
   2  * ARM GIC support - internal interfaces
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef QEMU_ARM_GIC_INTERNAL_H
  22 #define QEMU_ARM_GIC_INTERNAL_H
  23
  24 #include "hw/intc/arm_gic.h"
  25
  26 #define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
  27
  28 /* The NVIC has 16 internal vectors.  However these are not exposed
  29    through the normal GIC interface.  */
  30 #define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
  31
  32 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
  33 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
  34 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
  35 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
  36 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
  37 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
  38 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
  39 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
  40 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
  41 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
  42 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
  43 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level |= (cm)
  44 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
  45 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
  46 #define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
  47 #define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = false
  48 #define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
  49 #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ?            \
  50                                     s->priority1[irq][cpu] :            \
  51                                     s->priority2[(irq) - GIC_INTERNAL])
  52 #define GIC_TARGET(irq) s->irq_target[irq]
  53 #define GIC_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &= ~(cm))
  54 #define GIC_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm))
  55 #define GIC_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != 0)
  56
  57 #define GICD_CTLR_EN_GRP0 (1U << 0)
  58 #define GICD_CTLR_EN_GRP1 (1U << 1)
  59
  60 #define GICC_CTLR_EN_GRP0    (1U << 0)
  61 #define GICC_CTLR_EN_GRP1    (1U << 1)
  62 #define GICC_CTLR_ACK_CTL    (1U << 2)
  63 #define GICC_CTLR_FIQ_EN     (1U << 3)
  64 #define GICC_CTLR_CBPR       (1U << 4) /* GICv1: SBPR */
  65 #define GICC_CTLR_EOIMODE    (1U << 9)
  66 #define GICC_CTLR_EOIMODE_NS (1U << 10)
  67
  68 /* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
  69  * GICv2 and GICv2 with security extensions:
  70  */
  71 #define GICC_CTLR_V1_MASK    0x1
  72 #define GICC_CTLR_V1_S_MASK  0x1f
  73 #define GICC_CTLR_V2_MASK    0x21f
  74 #define GICC_CTLR_V2_S_MASK  0x61f
  75
  76 /* The special cases for the revision property: */
  77 #define REV_11MPCORE 0
  78 #define REV_NVIC 0xffffffff
  79
  80 void gic_set_pending_private(GICState *s, int cpu, int irq);
  81 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
  82 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
  83 void gic_update(GICState *s);
  84 void gic_init_irqs_and_distributor(GICState *s);
  85 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
  86                       MemTxAttrs attrs);
  87
  88 static inline bool gic_test_pending(GICState *s, int irq, int cm)
  89 {
  90     if (s->revision == REV_NVIC || s->revision == REV_11MPCORE) {
  91         return s->irq_state[irq].pending & cm;
  92     } else {
  93         /* Edge-triggered interrupts are marked pending on a rising edge, but
  94          * level-triggered interrupts are either considered pending when the
  95          * level is active or if software has explicitly written to
  96          * GICD_ISPENDR to set the state pending.
  97          */
  98         return (s->irq_state[irq].pending & cm) ||
  99             (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm));
 100     }
 101 }
 102
 103 #endif /* !QEMU_ARM_GIC_INTERNAL_H */