hw/pci-bridge/xio3130_downstream.c

   1 /*
   2  * x3130_downstream.c
   3  * TI X3130 pci express downstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "hw/pci/pci_ids.h"
  23 #include "hw/pci/msi.h"
  24 #include "hw/pci/pcie.h"
  25 #include "xio3130_downstream.h"
  26
  27 #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
  28 #define XIO3130_REVISION                0x1
  29 #define XIO3130_MSI_OFFSET              0x70
  30 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  31 #define XIO3130_MSI_NR_VECTOR           1
  32 #define XIO3130_SSVID_OFFSET            0x80
  33 #define XIO3130_SSVID_SVID              0
  34 #define XIO3130_SSVID_SSID              0
  35 #define XIO3130_EXP_OFFSET              0x90
  36 #define XIO3130_AER_OFFSET              0x100
  37
  38 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
  39                                          uint32_t val, int len)
  40 {
  41     pci_bridge_write_config(d, address, val, len);
  42     pcie_cap_flr_write_config(d, address, val, len);
  43     pcie_cap_slot_write_config(d, address, val, len);
  44     pcie_aer_write_config(d, address, val, len);
  45 }
  46
  47 static void xio3130_downstream_reset(DeviceState *qdev)
  48 {
  49     PCIDevice *d = PCI_DEVICE(qdev);
  50
  51     pcie_cap_deverr_reset(d);
  52     pcie_cap_slot_reset(d);
  53     pcie_cap_arifwd_reset(d);
  54     pci_bridge_reset(qdev);
  55 }
  56
  57 static int xio3130_downstream_initfn(PCIDevice *d)
  58 {
  59     PCIEPort *p = PCIE_PORT(d);
  60     PCIESlot *s = PCIE_SLOT(d);
  61     int rc;
  62
  63     rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
  64     if (rc < 0) {
  65         return rc;
  66     }
  67
  68     pcie_port_init_reg(d);
  69
  70     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  71                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  72                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  73     if (rc < 0) {
  74         goto err_bridge;
  75     }
  76     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  77                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  78     if (rc < 0) {
  79         goto err_bridge;
  80     }
  81     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
  82                        p->port);
  83     if (rc < 0) {
  84         goto err_msi;
  85     }
  86     pcie_cap_flr_init(d);
  87     pcie_cap_deverr_init(d);
  88     pcie_cap_slot_init(d, s->slot);
  89     pcie_chassis_create(s->chassis);
  90     rc = pcie_chassis_add_slot(s);
  91     if (rc < 0) {
  92         goto err_pcie_cap;
  93     }
  94     pcie_cap_arifwd_init(d);
  95     rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
  96     if (rc < 0) {
  97         goto err;
  98     }
  99
 100     return 0;
 101
 102 err:
 103     pcie_chassis_del_slot(s);
 104 err_pcie_cap:
 105     pcie_cap_exit(d);
 106 err_msi:
 107     msi_uninit(d);
 108 err_bridge:
 109     pci_bridge_exitfn(d);
 110     return rc;
 111 }
 112
 113 static void xio3130_downstream_exitfn(PCIDevice *d)
 114 {
 115     PCIESlot *s = PCIE_SLOT(d);
 116
 117     pcie_aer_exit(d);
 118     pcie_chassis_del_slot(s);
 119     pcie_cap_exit(d);
 120     msi_uninit(d);
 121     pci_bridge_exitfn(d);
 122 }
 123
 124 PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
 125                                   const char *bus_name, pci_map_irq_fn map_irq,
 126                                   uint8_t port, uint8_t chassis,
 127                                   uint16_t slot)
 128 {
 129     PCIDevice *d;
 130     PCIBridge *br;
 131     DeviceState *qdev;
 132
 133     d = pci_create_multifunction(bus, devfn, multifunction,
 134                                  "xio3130-downstream");
 135     if (!d) {
 136         return NULL;
 137     }
 138     br = PCI_BRIDGE(d);
 139
 140     qdev = DEVICE(d);
 141     pci_bridge_map_irq(br, bus_name, map_irq);
 142     qdev_prop_set_uint8(qdev, "port", port);
 143     qdev_prop_set_uint8(qdev, "chassis", chassis);
 144     qdev_prop_set_uint16(qdev, "slot", slot);
 145     qdev_init_nofail(qdev);
 146
 147     return PCIE_SLOT(d);
 148 }
 149
 150 static Property xio3130_downstream_props[] = {
 151     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
 152                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
 153     DEFINE_PROP_END_OF_LIST()
 154 };
 155
 156 static const VMStateDescription vmstate_xio3130_downstream = {
 157     .name = "xio3130-express-downstream-port",
 158     .version_id = 1,
 159     .minimum_version_id = 1,
 160     .post_load = pcie_cap_slot_post_load,
 161     .fields = (VMStateField[]) {
 162         VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 163         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 164                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 165         VMSTATE_END_OF_LIST()
 166     }
 167 };
 168
 169 static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
 170 {
 171     DeviceClass *dc = DEVICE_CLASS(klass);
 172     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 173
 174     k->is_express = 1;
 175     k->is_bridge = 1;
 176     k->config_write = xio3130_downstream_write_config;
 177     k->init = xio3130_downstream_initfn;
 178     k->exit = xio3130_downstream_exitfn;
 179     k->vendor_id = PCI_VENDOR_ID_TI;
 180     k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
 181     k->revision = XIO3130_REVISION;
 182     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 183     dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
 184     dc->reset = xio3130_downstream_reset;
 185     dc->vmsd = &vmstate_xio3130_downstream;
 186     dc->props = xio3130_downstream_props;
 187 }
 188
 189 static const TypeInfo xio3130_downstream_info = {
 190     .name          = "xio3130-downstream",
 191     .parent        = TYPE_PCIE_SLOT,
 192     .class_init    = xio3130_downstream_class_init,
 193 };
 194
 195 static void xio3130_downstream_register_types(void)
 196 {
 197     type_register_static(&xio3130_downstream_info);
 198 }
 199
 200 type_init(xio3130_downstream_register_types)
 201
 202 /*
 203  * Local variables:
 204  *  c-indent-level: 4
 205  *  c-basic-offset: 4
 206  *  tab-width: 8
 207  *  indent-tab-mode: nil
 208  * End:
 209  */