hw/timer/hpet.c

   1 /*
   2  *  High Precision Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw/hw.h"
  28 #include "hw/i386/pc.h"
  29 #include "ui/console.h"
  30 #include "qemu/timer.h"
  31 #include "hw/timer/hpet.h"
  32 #include "hw/sysbus.h"
  33 #include "hw/timer/mc146818rtc.h"
  34 #include "hw/timer/i8254.h"
  35
  36 //#define HPET_DEBUG
  37 #ifdef HPET_DEBUG
  38 #define DPRINTF printf
  39 #else
  40 #define DPRINTF(...)
  41 #endif
  42
  43 #define HPET_MSI_SUPPORT        0
  44
  45 #define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET)
  46
  47 struct HPETState;
  48 typedef struct HPETTimer {  /* timers */
  49     uint8_t tn;             /*timer number*/
  50     QEMUTimer *qemu_timer;
  51     struct HPETState *state;
  52     /* Memory-mapped, software visible timer registers */
  53     uint64_t config;        /* configuration/cap */
  54     uint64_t cmp;           /* comparator */
  55     uint64_t fsb;           /* FSB route */
  56     /* Hidden register state */
  57     uint64_t period;        /* Last value written to comparator */
  58     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  59                              * mode. Next pop will be actual timer expiration.
  60                              */
  61 } HPETTimer;
  62
  63 typedef struct HPETState {
  64     /*< private >*/
  65     SysBusDevice parent_obj;
  66     /*< public >*/
  67
  68     MemoryRegion iomem;
  69     uint64_t hpet_offset;
  70     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  71     uint32_t flags;
  72     uint8_t rtc_irq_level;
  73     qemu_irq pit_enabled;
  74     uint8_t num_timers;
  75     uint32_t intcap;
  76     HPETTimer timer[HPET_MAX_TIMERS];
  77
  78     /* Memory-mapped, software visible registers */
  79     uint64_t capability;        /* capabilities */
  80     uint64_t config;            /* configuration */
  81     uint64_t isr;               /* interrupt status reg */
  82     uint64_t hpet_counter;      /* main counter */
  83     uint8_t  hpet_id;           /* instance id */
  84 } HPETState;
  85
  86 static uint32_t hpet_in_legacy_mode(HPETState *s)
  87 {
  88     return s->config & HPET_CFG_LEGACY;
  89 }
  90
  91 static uint32_t timer_int_route(struct HPETTimer *timer)
  92 {
  93     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  94 }
  95
  96 static uint32_t timer_fsb_route(HPETTimer *t)
  97 {
  98     return t->config & HPET_TN_FSB_ENABLE;
  99 }
 100
 101 static uint32_t hpet_enabled(HPETState *s)
 102 {
 103     return s->config & HPET_CFG_ENABLE;
 104 }
 105
 106 static uint32_t timer_is_periodic(HPETTimer *t)
 107 {
 108     return t->config & HPET_TN_PERIODIC;
 109 }
 110
 111 static uint32_t timer_enabled(HPETTimer *t)
 112 {
 113     return t->config & HPET_TN_ENABLE;
 114 }
 115
 116 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 117 {
 118     return ((int32_t)(b) - (int32_t)(a) < 0);
 119 }
 120
 121 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 122 {
 123     return ((int64_t)(b) - (int64_t)(a) < 0);
 124 }
 125
 126 static uint64_t ticks_to_ns(uint64_t value)
 127 {
 128     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 129 }
 130
 131 static uint64_t ns_to_ticks(uint64_t value)
 132 {
 133     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 134 }
 135
 136 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 137 {
 138     new &= mask;
 139     new |= old & ~mask;
 140     return new;
 141 }
 142
 143 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 144 {
 145     return (!(old & mask) && (new & mask));
 146 }
 147
 148 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 149 {
 150     return ((old & mask) && !(new & mask));
 151 }
 152
 153 static uint64_t hpet_get_ticks(HPETState *s)
 154 {
 155     return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset);
 156 }
 157
 158 /*
 159  * calculate diff between comparator value and current ticks
 160  */
 161 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 162 {
 163
 164     if (t->config & HPET_TN_32BIT) {
 165         uint32_t diff, cmp;
 166
 167         cmp = (uint32_t)t->cmp;
 168         diff = cmp - (uint32_t)current;
 169         diff = (int32_t)diff > 0 ? diff : (uint32_t)1;
 170         return (uint64_t)diff;
 171     } else {
 172         uint64_t diff, cmp;
 173
 174         cmp = t->cmp;
 175         diff = cmp - current;
 176         diff = (int64_t)diff > 0 ? diff : (uint64_t)1;
 177         return diff;
 178     }
 179 }
 180
 181 static void update_irq(struct HPETTimer *timer, int set)
 182 {
 183     uint64_t mask;
 184     HPETState *s;
 185     int route;
 186
 187     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 188         /* if LegacyReplacementRoute bit is set, HPET specification requires
 189          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 190          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 191          */
 192         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 193     } else {
 194         route = timer_int_route(timer);
 195     }
 196     s = timer->state;
 197     mask = 1 << timer->tn;
 198     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 199         s->isr &= ~mask;
 200         if (!timer_fsb_route(timer)) {
 201             /* fold the ICH PIRQ# pin's internal inversion logic into hpet */
 202             if (route >= ISA_NUM_IRQS) {
 203                 qemu_irq_raise(s->irqs[route]);
 204             } else {
 205                 qemu_irq_lower(s->irqs[route]);
 206             }
 207         }
 208     } else if (timer_fsb_route(timer)) {
 209         address_space_stl_le(&address_space_memory, timer->fsb >> 32,
 210                              timer->fsb & 0xffffffff, MEMTXATTRS_UNSPECIFIED,
 211                              NULL);
 212     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 213         s->isr |= mask;
 214         /* fold the ICH PIRQ# pin's internal inversion logic into hpet */
 215         if (route >= ISA_NUM_IRQS) {
 216             qemu_irq_lower(s->irqs[route]);
 217         } else {
 218             qemu_irq_raise(s->irqs[route]);
 219         }
 220     } else {
 221         s->isr &= ~mask;
 222         qemu_irq_pulse(s->irqs[route]);
 223     }
 224 }
 225
 226 static void hpet_pre_save(void *opaque)
 227 {
 228     HPETState *s = opaque;
 229
 230     /* save current counter value */
 231     s->hpet_counter = hpet_get_ticks(s);
 232 }
 233
 234 static int hpet_pre_load(void *opaque)
 235 {
 236     HPETState *s = opaque;
 237
 238     /* version 1 only supports 3, later versions will load the actual value */
 239     s->num_timers = HPET_MIN_TIMERS;
 240     return 0;
 241 }
 242
 243 static bool hpet_validate_num_timers(void *opaque, int version_id)
 244 {
 245     HPETState *s = opaque;
 246
 247     if (s->num_timers < HPET_MIN_TIMERS) {
 248         return false;
 249     } else if (s->num_timers > HPET_MAX_TIMERS) {
 250         return false;
 251     }
 252     return true;
 253 }
 254
 255 static int hpet_post_load(void *opaque, int version_id)
 256 {
 257     HPETState *s = opaque;
 258
 259     /* Recalculate the offset between the main counter and guest time */
 260     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 261
 262     /* Push number of timers into capability returned via HPET_ID */
 263     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 264     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 265     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 266
 267     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 268     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 269     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 270         s->flags |= 1 << HPET_MSI_SUPPORT;
 271     }
 272     return 0;
 273 }
 274
 275 static bool hpet_rtc_irq_level_needed(void *opaque)
 276 {
 277     HPETState *s = opaque;
 278
 279     return s->rtc_irq_level != 0;
 280 }
 281
 282 static const VMStateDescription vmstate_hpet_rtc_irq_level = {
 283     .name = "hpet/rtc_irq_level",
 284     .version_id = 1,
 285     .minimum_version_id = 1,
 286     .fields = (VMStateField[]) {
 287         VMSTATE_UINT8(rtc_irq_level, HPETState),
 288         VMSTATE_END_OF_LIST()
 289     }
 290 };
 291
 292 static const VMStateDescription vmstate_hpet_timer = {
 293     .name = "hpet_timer",
 294     .version_id = 1,
 295     .minimum_version_id = 1,
 296     .fields = (VMStateField[]) {
 297         VMSTATE_UINT8(tn, HPETTimer),
 298         VMSTATE_UINT64(config, HPETTimer),
 299         VMSTATE_UINT64(cmp, HPETTimer),
 300         VMSTATE_UINT64(fsb, HPETTimer),
 301         VMSTATE_UINT64(period, HPETTimer),
 302         VMSTATE_UINT8(wrap_flag, HPETTimer),
 303         VMSTATE_TIMER_PTR(qemu_timer, HPETTimer),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 static const VMStateDescription vmstate_hpet = {
 309     .name = "hpet",
 310     .version_id = 2,
 311     .minimum_version_id = 1,
 312     .pre_save = hpet_pre_save,
 313     .pre_load = hpet_pre_load,
 314     .post_load = hpet_post_load,
 315     .fields = (VMStateField[]) {
 316         VMSTATE_UINT64(config, HPETState),
 317         VMSTATE_UINT64(isr, HPETState),
 318         VMSTATE_UINT64(hpet_counter, HPETState),
 319         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 320         VMSTATE_VALIDATE("num_timers in range", hpet_validate_num_timers),
 321         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 322                                     vmstate_hpet_timer, HPETTimer),
 323         VMSTATE_END_OF_LIST()
 324     },
 325     .subsections = (VMStateSubsection[]) {
 326         {
 327             .vmsd = &vmstate_hpet_rtc_irq_level,
 328             .needed = hpet_rtc_irq_level_needed,
 329         }, {
 330             /* empty */
 331         }
 332     }
 333 };
 334
 335 /*
 336  * timer expiration callback
 337  */
 338 static void hpet_timer(void *opaque)
 339 {
 340     HPETTimer *t = opaque;
 341     uint64_t diff;
 342
 343     uint64_t period = t->period;
 344     uint64_t cur_tick = hpet_get_ticks(t->state);
 345
 346     if (timer_is_periodic(t) && period != 0) {
 347         if (t->config & HPET_TN_32BIT) {
 348             while (hpet_time_after(cur_tick, t->cmp)) {
 349                 t->cmp = (uint32_t)(t->cmp + t->period);
 350             }
 351         } else {
 352             while (hpet_time_after64(cur_tick, t->cmp)) {
 353                 t->cmp += period;
 354             }
 355         }
 356         diff = hpet_calculate_diff(t, cur_tick);
 357         timer_mod(t->qemu_timer,
 358                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
 359     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 360         if (t->wrap_flag) {
 361             diff = hpet_calculate_diff(t, cur_tick);
 362             timer_mod(t->qemu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 363                            (int64_t)ticks_to_ns(diff));
 364             t->wrap_flag = 0;
 365         }
 366     }
 367     update_irq(t, 1);
 368 }
 369
 370 static void hpet_set_timer(HPETTimer *t)
 371 {
 372     uint64_t diff;
 373     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 374     uint64_t cur_tick = hpet_get_ticks(t->state);
 375
 376     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 377     t->wrap_flag = 0;
 378     diff = hpet_calculate_diff(t, cur_tick);
 379
 380     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 381      * counter wraps in addition to an interrupt with comparator match.
 382      */
 383     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 384         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 385         if (wrap_diff < (uint32_t)diff) {
 386             diff = wrap_diff;
 387             t->wrap_flag = 1;
 388         }
 389     }
 390     timer_mod(t->qemu_timer,
 391                    qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
 392 }
 393
 394 static void hpet_del_timer(HPETTimer *t)
 395 {
 396     timer_del(t->qemu_timer);
 397     update_irq(t, 0);
 398 }
 399
 400 #ifdef HPET_DEBUG
 401 static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
 402 {
 403     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 404     return 0;
 405 }
 406
 407 static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
 408 {
 409     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 410     return 0;
 411 }
 412 #endif
 413
 414 static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
 415                               unsigned size)
 416 {
 417     HPETState *s = opaque;
 418     uint64_t cur_tick, index;
 419
 420     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 421     index = addr;
 422     /*address range of all TN regs*/
 423     if (index >= 0x100 && index <= 0x3ff) {
 424         uint8_t timer_id = (addr - 0x100) / 0x20;
 425         HPETTimer *timer = &s->timer[timer_id];
 426
 427         if (timer_id > s->num_timers) {
 428             DPRINTF("qemu: timer id out of range\n");
 429             return 0;
 430         }
 431
 432         switch ((addr - 0x100) % 0x20) {
 433         case HPET_TN_CFG:
 434             return timer->config;
 435         case HPET_TN_CFG + 4: // Interrupt capabilities
 436             return timer->config >> 32;
 437         case HPET_TN_CMP: // comparator register
 438             return timer->cmp;
 439         case HPET_TN_CMP + 4:
 440             return timer->cmp >> 32;
 441         case HPET_TN_ROUTE:
 442             return timer->fsb;
 443         case HPET_TN_ROUTE + 4:
 444             return timer->fsb >> 32;
 445         default:
 446             DPRINTF("qemu: invalid hpet_ram_readl\n");
 447             break;
 448         }
 449     } else {
 450         switch (index) {
 451         case HPET_ID:
 452             return s->capability;
 453         case HPET_PERIOD:
 454             return s->capability >> 32;
 455         case HPET_CFG:
 456             return s->config;
 457         case HPET_CFG + 4:
 458             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
 459             return 0;
 460         case HPET_COUNTER:
 461             if (hpet_enabled(s)) {
 462                 cur_tick = hpet_get_ticks(s);
 463             } else {
 464                 cur_tick = s->hpet_counter;
 465             }
 466             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 467             return cur_tick;
 468         case HPET_COUNTER + 4:
 469             if (hpet_enabled(s)) {
 470                 cur_tick = hpet_get_ticks(s);
 471             } else {
 472                 cur_tick = s->hpet_counter;
 473             }
 474             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 475             return cur_tick >> 32;
 476         case HPET_STATUS:
 477             return s->isr;
 478         default:
 479             DPRINTF("qemu: invalid hpet_ram_readl\n");
 480             break;
 481         }
 482     }
 483     return 0;
 484 }
 485
 486 static void hpet_ram_write(void *opaque, hwaddr addr,
 487                            uint64_t value, unsigned size)
 488 {
 489     int i;
 490     HPETState *s = opaque;
 491     uint64_t old_val, new_val, val, index;
 492
 493     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 494     index = addr;
 495     old_val = hpet_ram_read(opaque, addr, 4);
 496     new_val = value;
 497
 498     /*address range of all TN regs*/
 499     if (index >= 0x100 && index <= 0x3ff) {
 500         uint8_t timer_id = (addr - 0x100) / 0x20;
 501         HPETTimer *timer = &s->timer[timer_id];
 502
 503         DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
 504         if (timer_id > s->num_timers) {
 505             DPRINTF("qemu: timer id out of range\n");
 506             return;
 507         }
 508         switch ((addr - 0x100) % 0x20) {
 509         case HPET_TN_CFG:
 510             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 511             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 512                 update_irq(timer, 0);
 513             }
 514             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 515             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 516             if (new_val & HPET_TN_32BIT) {
 517                 timer->cmp = (uint32_t)timer->cmp;
 518                 timer->period = (uint32_t)timer->period;
 519             }
 520             if (activating_bit(old_val, new_val, HPET_TN_ENABLE) &&
 521                 hpet_enabled(s)) {
 522                 hpet_set_timer(timer);
 523             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 524                 hpet_del_timer(timer);
 525             }
 526             break;
 527         case HPET_TN_CFG + 4: // Interrupt capabilities
 528             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 529             break;
 530         case HPET_TN_CMP: // comparator register
 531             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
 532             if (timer->config & HPET_TN_32BIT) {
 533                 new_val = (uint32_t)new_val;
 534             }
 535             if (!timer_is_periodic(timer)
 536                 || (timer->config & HPET_TN_SETVAL)) {
 537                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 538             }
 539             if (timer_is_periodic(timer)) {
 540                 /*
 541                  * FIXME: Clamp period to reasonable min value?
 542                  * Clamp period to reasonable max value
 543                  */
 544                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 545                 timer->period =
 546                     (timer->period & 0xffffffff00000000ULL) | new_val;
 547             }
 548             timer->config &= ~HPET_TN_SETVAL;
 549             if (hpet_enabled(s)) {
 550                 hpet_set_timer(timer);
 551             }
 552             break;
 553         case HPET_TN_CMP + 4: // comparator register high order
 554             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 555             if (!timer_is_periodic(timer)
 556                 || (timer->config & HPET_TN_SETVAL)) {
 557                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 558             } else {
 559                 /*
 560                  * FIXME: Clamp period to reasonable min value?
 561                  * Clamp period to reasonable max value
 562                  */
 563                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 564                 timer->period =
 565                     (timer->period & 0xffffffffULL) | new_val << 32;
 566                 }
 567                 timer->config &= ~HPET_TN_SETVAL;
 568                 if (hpet_enabled(s)) {
 569                     hpet_set_timer(timer);
 570                 }
 571                 break;
 572         case HPET_TN_ROUTE:
 573             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 574             break;
 575         case HPET_TN_ROUTE + 4:
 576             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 577             break;
 578         default:
 579             DPRINTF("qemu: invalid hpet_ram_writel\n");
 580             break;
 581         }
 582         return;
 583     } else {
 584         switch (index) {
 585         case HPET_ID:
 586             return;
 587         case HPET_CFG:
 588             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 589             s->config = (s->config & 0xffffffff00000000ULL) | val;
 590             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 591                 /* Enable main counter and interrupt generation. */
 592                 s->hpet_offset =
 593                     ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 594                 for (i = 0; i < s->num_timers; i++) {
 595                     if ((&s->timer[i])->cmp != ~0ULL) {
 596                         hpet_set_timer(&s->timer[i]);
 597                     }
 598                 }
 599             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 600                 /* Halt main counter and disable interrupt generation. */
 601                 s->hpet_counter = hpet_get_ticks(s);
 602                 for (i = 0; i < s->num_timers; i++) {
 603                     hpet_del_timer(&s->timer[i]);
 604                 }
 605             }
 606             /* i8254 and RTC output pins are disabled
 607              * when HPET is in legacy mode */
 608             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 609                 qemu_set_irq(s->pit_enabled, 0);
 610                 qemu_irq_lower(s->irqs[0]);
 611                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 612             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 613                 qemu_irq_lower(s->irqs[0]);
 614                 qemu_set_irq(s->pit_enabled, 1);
 615                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 616             }
 617             break;
 618         case HPET_CFG + 4:
 619             DPRINTF("qemu: invalid HPET_CFG+4 write\n");
 620             break;
 621         case HPET_STATUS:
 622             val = new_val & s->isr;
 623             for (i = 0; i < s->num_timers; i++) {
 624                 if (val & (1 << i)) {
 625                     update_irq(&s->timer[i], 0);
 626                 }
 627             }
 628             break;
 629         case HPET_COUNTER:
 630             if (hpet_enabled(s)) {
 631                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 632             }
 633             s->hpet_counter =
 634                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 635             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 636                     value, s->hpet_counter);
 637             break;
 638         case HPET_COUNTER + 4:
 639             if (hpet_enabled(s)) {
 640                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 641             }
 642             s->hpet_counter =
 643                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 644             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 645                     value, s->hpet_counter);
 646             break;
 647         default:
 648             DPRINTF("qemu: invalid hpet_ram_writel\n");
 649             break;
 650         }
 651     }
 652 }
 653
 654 static const MemoryRegionOps hpet_ram_ops = {
 655     .read = hpet_ram_read,
 656     .write = hpet_ram_write,
 657     .valid = {
 658         .min_access_size = 4,
 659         .max_access_size = 4,
 660     },
 661     .endianness = DEVICE_NATIVE_ENDIAN,
 662 };
 663
 664 static void hpet_reset(DeviceState *d)
 665 {
 666     HPETState *s = HPET(d);
 667     SysBusDevice *sbd = SYS_BUS_DEVICE(d);
 668     int i;
 669
 670     for (i = 0; i < s->num_timers; i++) {
 671         HPETTimer *timer = &s->timer[i];
 672
 673         hpet_del_timer(timer);
 674         timer->cmp = ~0ULL;
 675         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 676         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 677             timer->config |= HPET_TN_FSB_CAP;
 678         }
 679         /* advertise availability of ioapic int */
 680         timer->config |=  (uint64_t)s->intcap << 32;
 681         timer->period = 0ULL;
 682         timer->wrap_flag = 0;
 683     }
 684
 685     qemu_set_irq(s->pit_enabled, 1);
 686     s->hpet_counter = 0ULL;
 687     s->hpet_offset = 0ULL;
 688     s->config = 0ULL;
 689     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 690     hpet_cfg.hpet[s->hpet_id].address = sbd->mmio[0].addr;
 691
 692     /* to document that the RTC lowers its output on reset as well */
 693     s->rtc_irq_level = 0;
 694 }
 695
 696 static void hpet_handle_legacy_irq(void *opaque, int n, int level)
 697 {
 698     HPETState *s = HPET(opaque);
 699
 700     if (n == HPET_LEGACY_PIT_INT) {
 701         if (!hpet_in_legacy_mode(s)) {
 702             qemu_set_irq(s->irqs[0], level);
 703         }
 704     } else {
 705         s->rtc_irq_level = level;
 706         if (!hpet_in_legacy_mode(s)) {
 707             qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 708         }
 709     }
 710 }
 711
 712 static void hpet_init(Object *obj)
 713 {
 714     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 715     HPETState *s = HPET(obj);
 716
 717     /* HPET Area */
 718     memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", 0x400);
 719     sysbus_init_mmio(sbd, &s->iomem);
 720 }
 721
 722 static void hpet_realize(DeviceState *dev, Error **errp)
 723 {
 724     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 725     HPETState *s = HPET(dev);
 726     int i;
 727     HPETTimer *timer;
 728
 729     if (!s->intcap) {
 730         error_printf("Hpet's intcap not initialized.\n");
 731     }
 732     if (hpet_cfg.count == UINT8_MAX) {
 733         /* first instance */
 734         hpet_cfg.count = 0;
 735     }
 736
 737     if (hpet_cfg.count == 8) {
 738         error_setg(errp, "Only 8 instances of HPET is allowed");
 739         return;
 740     }
 741
 742     s->hpet_id = hpet_cfg.count++;
 743
 744     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 745         sysbus_init_irq(sbd, &s->irqs[i]);
 746     }
 747
 748     if (s->num_timers < HPET_MIN_TIMERS) {
 749         s->num_timers = HPET_MIN_TIMERS;
 750     } else if (s->num_timers > HPET_MAX_TIMERS) {
 751         s->num_timers = HPET_MAX_TIMERS;
 752     }
 753     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 754         timer = &s->timer[i];
 755         timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
 756         timer->tn = i;
 757         timer->state = s;
 758     }
 759
 760     /* 64-bit main counter; LegacyReplacementRoute. */
 761     s->capability = 0x8086a001ULL;
 762     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 763     s->capability |= ((HPET_CLK_PERIOD) << 32);
 764
 765     qdev_init_gpio_in(dev, hpet_handle_legacy_irq, 2);
 766     qdev_init_gpio_out(dev, &s->pit_enabled, 1);
 767 }
 768
 769 static Property hpet_device_properties[] = {
 770     DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 771     DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 772     DEFINE_PROP_UINT32(HPET_INTCAP, HPETState, intcap, 0),
 773     DEFINE_PROP_END_OF_LIST(),
 774 };
 775
 776 static void hpet_device_class_init(ObjectClass *klass, void *data)
 777 {
 778     DeviceClass *dc = DEVICE_CLASS(klass);
 779
 780     dc->realize = hpet_realize;
 781     dc->reset = hpet_reset;
 782     dc->vmsd = &vmstate_hpet;
 783     dc->props = hpet_device_properties;
 784 }
 785
 786 static const TypeInfo hpet_device_info = {
 787     .name          = TYPE_HPET,
 788     .parent        = TYPE_SYS_BUS_DEVICE,
 789     .instance_size = sizeof(HPETState),
 790     .instance_init = hpet_init,
 791     .class_init    = hpet_device_class_init,
 792 };
 793
 794 static void hpet_register_types(void)
 795 {
 796     type_register_static(&hpet_device_info);
 797 }
 798
 799 type_init(hpet_register_types)