hw/versatilepb.c

   1 /*
   2  * ARM Versatile Platform/Application Baseboard System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "arm-misc.h"
  12 #include "primecell.h"
  13 #include "devices.h"
  14 #include "net.h"
  15 #include "sysemu.h"
  16 #include "pci.h"
  17 #include "usb-ohci.h"
  18 #include "boards.h"
  19 #include "blockdev.h"
  20
  21 /* Primary interrupt controller.  */
  22
  23 typedef struct vpb_sic_state
  24 {
  25   SysBusDevice busdev;
  26   uint32_t level;
  27   uint32_t mask;
  28   uint32_t pic_enable;
  29   qemu_irq parent[32];
  30   int irq;
  31 } vpb_sic_state;
  32
  33 static const VMStateDescription vmstate_vpb_sic = {
  34     .name = "versatilepb_sic",
  35     .version_id = 1,
  36     .minimum_version_id = 1,
  37     .fields = (VMStateField[]) {
  38         VMSTATE_UINT32(level, vpb_sic_state),
  39         VMSTATE_UINT32(mask, vpb_sic_state),
  40         VMSTATE_UINT32(pic_enable, vpb_sic_state),
  41         VMSTATE_END_OF_LIST()
  42     }
  43 };
  44
  45 static void vpb_sic_update(vpb_sic_state *s)
  46 {
  47     uint32_t flags;
  48
  49     flags = s->level & s->mask;
  50     qemu_set_irq(s->parent[s->irq], flags != 0);
  51 }
  52
  53 static void vpb_sic_update_pic(vpb_sic_state *s)
  54 {
  55     int i;
  56     uint32_t mask;
  57
  58     for (i = 21; i <= 30; i++) {
  59         mask = 1u << i;
  60         if (!(s->pic_enable & mask))
  61             continue;
  62         qemu_set_irq(s->parent[i], (s->level & mask) != 0);
  63     }
  64 }
  65
  66 static void vpb_sic_set_irq(void *opaque, int irq, int level)
  67 {
  68     vpb_sic_state *s = (vpb_sic_state *)opaque;
  69     if (level)
  70         s->level |= 1u << irq;
  71     else
  72         s->level &= ~(1u << irq);
  73     if (s->pic_enable & (1u << irq))
  74         qemu_set_irq(s->parent[irq], level);
  75     vpb_sic_update(s);
  76 }
  77
  78 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
  79 {
  80     vpb_sic_state *s = (vpb_sic_state *)opaque;
  81
  82     switch (offset >> 2) {
  83     case 0: /* STATUS */
  84         return s->level & s->mask;
  85     case 1: /* RAWSTAT */
  86         return s->level;
  87     case 2: /* ENABLE */
  88         return s->mask;
  89     case 4: /* SOFTINT */
  90         return s->level & 1;
  91     case 8: /* PICENABLE */
  92         return s->pic_enable;
  93     default:
  94         printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
  95         return 0;
  96     }
  97 }
  98
  99 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
 100                           uint32_t value)
 101 {
 102     vpb_sic_state *s = (vpb_sic_state *)opaque;
 103
 104     switch (offset >> 2) {
 105     case 2: /* ENSET */
 106         s->mask |= value;
 107         break;
 108     case 3: /* ENCLR */
 109         s->mask &= ~value;
 110         break;
 111     case 4: /* SOFTINTSET */
 112         if (value)
 113             s->mask |= 1;
 114         break;
 115     case 5: /* SOFTINTCLR */
 116         if (value)
 117             s->mask &= ~1u;
 118         break;
 119     case 8: /* PICENSET */
 120         s->pic_enable |= (value & 0x7fe00000);
 121         vpb_sic_update_pic(s);
 122         break;
 123     case 9: /* PICENCLR */
 124         s->pic_enable &= ~value;
 125         vpb_sic_update_pic(s);
 126         break;
 127     default:
 128         printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
 129         return;
 130     }
 131     vpb_sic_update(s);
 132 }
 133
 134 static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
 135    vpb_sic_read,
 136    vpb_sic_read,
 137    vpb_sic_read
 138 };
 139
 140 static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
 141    vpb_sic_write,
 142    vpb_sic_write,
 143    vpb_sic_write
 144 };
 145
 146 static int vpb_sic_init(SysBusDevice *dev)
 147 {
 148     vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
 149     int iomemtype;
 150     int i;
 151
 152     qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
 153     for (i = 0; i < 32; i++) {
 154         sysbus_init_irq(dev, &s->parent[i]);
 155     }
 156     s->irq = 31;
 157     iomemtype = cpu_register_io_memory(vpb_sic_readfn,
 158                                        vpb_sic_writefn, s,
 159                                        DEVICE_NATIVE_ENDIAN);
 160     sysbus_init_mmio(dev, 0x1000, iomemtype);
 161     return 0;
 162 }
 163
 164 /* Board init.  */
 165
 166 /* The AB and PB boards both use the same core, just with different
 167    peripherans and expansion busses.  For now we emulate a subset of the
 168    PB peripherals and just change the board ID.  */
 169
 170 static struct arm_boot_info versatile_binfo;
 171
 172 static void versatile_init(ram_addr_t ram_size,
 173                      const char *boot_device,
 174                      const char *kernel_filename, const char *kernel_cmdline,
 175                      const char *initrd_filename, const char *cpu_model,
 176                      int board_id)
 177 {
 178     CPUState *env;
 179     ram_addr_t ram_offset;
 180     qemu_irq *cpu_pic;
 181     qemu_irq pic[32];
 182     qemu_irq sic[32];
 183     DeviceState *dev, *sysctl;
 184     SysBusDevice *busdev;
 185     DeviceState *pl041;
 186     PCIBus *pci_bus;
 187     NICInfo *nd;
 188     int n;
 189     int done_smc = 0;
 190
 191     if (!cpu_model)
 192         cpu_model = "arm926";
 193     env = cpu_init(cpu_model);
 194     if (!env) {
 195         fprintf(stderr, "Unable to find CPU definition\n");
 196         exit(1);
 197     }
 198     ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
 199     /* ??? RAM should repeat to fill physical memory space.  */
 200     /* SDRAM at address zero.  */
 201     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 202
 203     sysctl = qdev_create(NULL, "realview_sysctl");
 204     qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
 205     qdev_init_nofail(sysctl);
 206     qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
 207     sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
 208
 209     cpu_pic = arm_pic_init_cpu(env);
 210     dev = sysbus_create_varargs("pl190", 0x10140000,
 211                                 cpu_pic[0], cpu_pic[1], NULL);
 212     for (n = 0; n < 32; n++) {
 213         pic[n] = qdev_get_gpio_in(dev, n);
 214     }
 215     dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
 216     for (n = 0; n < 32; n++) {
 217         sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
 218         sic[n] = qdev_get_gpio_in(dev, n);
 219     }
 220
 221     sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
 222     sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
 223
 224     dev = qdev_create(NULL, "versatile_pci");
 225     busdev = sysbus_from_qdev(dev);
 226     qdev_init_nofail(dev);
 227     sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
 228     sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
 229     sysbus_connect_irq(busdev, 0, sic[27]);
 230     sysbus_connect_irq(busdev, 1, sic[28]);
 231     sysbus_connect_irq(busdev, 2, sic[29]);
 232     sysbus_connect_irq(busdev, 3, sic[30]);
 233     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 234
 235     /* The Versatile PCI bridge does not provide access to PCI IO space,
 236        so many of the qemu PCI devices are not useable.  */
 237     for(n = 0; n < nb_nics; n++) {
 238         nd = &nd_table[n];
 239
 240         if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
 241             smc91c111_init(nd, 0x10010000, sic[25]);
 242             done_smc = 1;
 243         } else {
 244             pci_nic_init_nofail(nd, "rtl8139", NULL);
 245         }
 246     }
 247     if (usb_enabled) {
 248         usb_ohci_init_pci(pci_bus, -1);
 249     }
 250     n = drive_get_max_bus(IF_SCSI);
 251     while (n >= 0) {
 252         pci_create_simple(pci_bus, -1, "lsi53c895a");
 253         n--;
 254     }
 255
 256     sysbus_create_simple("pl011", 0x101f1000, pic[12]);
 257     sysbus_create_simple("pl011", 0x101f2000, pic[13]);
 258     sysbus_create_simple("pl011", 0x101f3000, pic[14]);
 259     sysbus_create_simple("pl011", 0x10009000, sic[6]);
 260
 261     sysbus_create_simple("pl080", 0x10130000, pic[17]);
 262     sysbus_create_simple("sp804", 0x101e2000, pic[4]);
 263     sysbus_create_simple("sp804", 0x101e3000, pic[5]);
 264
 265     /* The versatile/PB actually has a modified Color LCD controller
 266        that includes hardware cursor support from the PL111.  */
 267     dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
 268     /* Wire up the mux control signals from the SYS_CLCD register */
 269     qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
 270
 271     sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
 272     sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
 273
 274     /* Add PL031 Real Time Clock. */
 275     sysbus_create_simple("pl031", 0x101e8000, pic[10]);
 276
 277     /* Add PL041 AACI Interface to the LM4549 codec */
 278     pl041 = qdev_create(NULL, "pl041");
 279     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 280     qdev_init_nofail(pl041);
 281     sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
 282     sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);
 283
 284     /* Memory map for Versatile/PB:  */
 285     /* 0x10000000 System registers.  */
 286     /* 0x10001000 PCI controller config registers.  */
 287     /* 0x10002000 Serial bus interface.  */
 288     /*  0x10003000 Secondary interrupt controller.  */
 289     /* 0x10004000 AACI (audio).  */
 290     /*  0x10005000 MMCI0.  */
 291     /*  0x10006000 KMI0 (keyboard).  */
 292     /*  0x10007000 KMI1 (mouse).  */
 293     /* 0x10008000 Character LCD Interface.  */
 294     /*  0x10009000 UART3.  */
 295     /* 0x1000a000 Smart card 1.  */
 296     /*  0x1000b000 MMCI1.  */
 297     /*  0x10010000 Ethernet.  */
 298     /* 0x10020000 USB.  */
 299     /* 0x10100000 SSMC.  */
 300     /* 0x10110000 MPMC.  */
 301     /*  0x10120000 CLCD Controller.  */
 302     /*  0x10130000 DMA Controller.  */
 303     /*  0x10140000 Vectored interrupt controller.  */
 304     /* 0x101d0000 AHB Monitor Interface.  */
 305     /* 0x101e0000 System Controller.  */
 306     /* 0x101e1000 Watchdog Interface.  */
 307     /* 0x101e2000 Timer 0/1.  */
 308     /* 0x101e3000 Timer 2/3.  */
 309     /* 0x101e4000 GPIO port 0.  */
 310     /* 0x101e5000 GPIO port 1.  */
 311     /* 0x101e6000 GPIO port 2.  */
 312     /* 0x101e7000 GPIO port 3.  */
 313     /* 0x101e8000 RTC.  */
 314     /* 0x101f0000 Smart card 0.  */
 315     /*  0x101f1000 UART0.  */
 316     /*  0x101f2000 UART1.  */
 317     /*  0x101f3000 UART2.  */
 318     /* 0x101f4000 SSPI.  */
 319
 320     versatile_binfo.ram_size = ram_size;
 321     versatile_binfo.kernel_filename = kernel_filename;
 322     versatile_binfo.kernel_cmdline = kernel_cmdline;
 323     versatile_binfo.initrd_filename = initrd_filename;
 324     versatile_binfo.board_id = board_id;
 325     arm_load_kernel(env, &versatile_binfo);
 326 }
 327
 328 static void vpb_init(ram_addr_t ram_size,
 329                      const char *boot_device,
 330                      const char *kernel_filename, const char *kernel_cmdline,
 331                      const char *initrd_filename, const char *cpu_model)
 332 {
 333     versatile_init(ram_size,
 334                    boot_device,
 335                    kernel_filename, kernel_cmdline,
 336                    initrd_filename, cpu_model, 0x183);
 337 }
 338
 339 static void vab_init(ram_addr_t ram_size,
 340                      const char *boot_device,
 341                      const char *kernel_filename, const char *kernel_cmdline,
 342                      const char *initrd_filename, const char *cpu_model)
 343 {
 344     versatile_init(ram_size,
 345                    boot_device,
 346                    kernel_filename, kernel_cmdline,
 347                    initrd_filename, cpu_model, 0x25e);
 348 }
 349
 350 static QEMUMachine versatilepb_machine = {
 351     .name = "versatilepb",
 352     .desc = "ARM Versatile/PB (ARM926EJ-S)",
 353     .init = vpb_init,
 354     .use_scsi = 1,
 355 };
 356
 357 static QEMUMachine versatileab_machine = {
 358     .name = "versatileab",
 359     .desc = "ARM Versatile/AB (ARM926EJ-S)",
 360     .init = vab_init,
 361     .use_scsi = 1,
 362 };
 363
 364 static void versatile_machine_init(void)
 365 {
 366     qemu_register_machine(&versatilepb_machine);
 367     qemu_register_machine(&versatileab_machine);
 368 }
 369
 370 machine_init(versatile_machine_init);
 371
 372 static SysBusDeviceInfo vpb_sic_info = {
 373     .init = vpb_sic_init,
 374     .qdev.name = "versatilepb_sic",
 375     .qdev.size = sizeof(vpb_sic_state),
 376     .qdev.vmsd = &vmstate_vpb_sic,
 377     .qdev.no_user = 1,
 378 };
 379
 380 static void versatilepb_register_devices(void)
 381 {
 382     sysbus_register_withprop(&vpb_sic_info);
 383 }
 384
 385 device_init(versatilepb_register_devices)