hw/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sparc32_dma.h"
  26 #include "sun4m.h"
  27
  28 /* debug DMA */
  29 //#define DEBUG_DMA
  30
  31 /*
  32  * This is the DMA controller part of chip STP2000 (Master I/O), also
  33  * produced as NCR89C100. See
  34  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  35  * and
  36  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  37  */
  38
  39 #ifdef DEBUG_DMA
  40 #define DPRINTF(fmt, args...) \
  41 do { printf("DMA: " fmt , ##args); } while (0)
  42 #else
  43 #define DPRINTF(fmt, args...)
  44 #endif
  45
  46 #define DMA_REGS 4
  47 #define DMA_SIZE (4 * sizeof(uint32_t))
  48
  49 #define DMA_VER 0xa0000000
  50 #define DMA_INTR 1
  51 #define DMA_INTREN 0x10
  52 #define DMA_WRITE_MEM 0x100
  53 #define DMA_LOADED 0x04000000
  54 #define DMA_DRAIN_FIFO 0x40
  55 #define DMA_RESET 0x80
  56
  57 typedef struct DMAState DMAState;
  58
  59 struct DMAState {
  60     uint32_t dmaregs[DMA_REGS];
  61     qemu_irq irq;
  62     void *iommu;
  63     qemu_irq dev_reset;
  64 };
  65
  66 /* Note: on sparc, the lance 16 bit bus is swapped */
  67 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
  68                        uint8_t *buf, int len, int do_bswap)
  69 {
  70     DMAState *s = opaque;
  71     int i;
  72
  73     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
  74             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  75     addr |= s->dmaregs[3];
  76     if (do_bswap) {
  77         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  78     } else {
  79         addr &= ~1;
  80         len &= ~1;
  81         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  82         for(i = 0; i < len; i += 2) {
  83             bswap16s((uint16_t *)(buf + i));
  84         }
  85     }
  86 }
  87
  88 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
  89                         uint8_t *buf, int len, int do_bswap)
  90 {
  91     DMAState *s = opaque;
  92     int l, i;
  93     uint16_t tmp_buf[32];
  94
  95     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
  96             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  97     addr |= s->dmaregs[3];
  98     if (do_bswap) {
  99         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 100     } else {
 101         addr &= ~1;
 102         len &= ~1;
 103         while (len > 0) {
 104             l = len;
 105             if (l > sizeof(tmp_buf))
 106                 l = sizeof(tmp_buf);
 107             for(i = 0; i < l; i += 2) {
 108                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 109             }
 110             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 111             len -= l;
 112             buf += l;
 113             addr += l;
 114         }
 115     }
 116 }
 117
 118 static void dma_set_irq(void *opaque, int irq, int level)
 119 {
 120     DMAState *s = opaque;
 121     if (level) {
 122         DPRINTF("Raise IRQ\n");
 123         s->dmaregs[0] |= DMA_INTR;
 124         qemu_irq_raise(s->irq);
 125     } else {
 126         s->dmaregs[0] &= ~DMA_INTR;
 127         DPRINTF("Lower IRQ\n");
 128         qemu_irq_lower(s->irq);
 129     }
 130 }
 131
 132 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 133 {
 134     DMAState *s = opaque;
 135
 136     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
 137             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 138     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 139     s->dmaregs[0] |= DMA_INTR;
 140     s->dmaregs[1] += len;
 141 }
 142
 143 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 144 {
 145     DMAState *s = opaque;
 146
 147     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
 148             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 149     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 150     s->dmaregs[0] |= DMA_INTR;
 151     s->dmaregs[1] += len;
 152 }
 153
 154 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
 155 {
 156     DMAState *s = opaque;
 157     uint32_t saddr;
 158
 159     saddr = addr >> 2;
 160     DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
 161             s->dmaregs[saddr]);
 162
 163     return s->dmaregs[saddr];
 164 }
 165
 166 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 167 {
 168     DMAState *s = opaque;
 169     uint32_t saddr;
 170
 171     saddr = addr >> 2;
 172     DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
 173             s->dmaregs[saddr], val);
 174     switch (saddr) {
 175     case 0:
 176         if (!(val & DMA_INTREN)) {
 177             DPRINTF("Lower IRQ\n");
 178             qemu_irq_lower(s->irq);
 179         }
 180         if (val & DMA_RESET) {
 181             qemu_irq_raise(s->dev_reset);
 182             qemu_irq_lower(s->dev_reset);
 183         } else if (val & DMA_DRAIN_FIFO) {
 184             val &= ~DMA_DRAIN_FIFO;
 185         } else if (val == 0)
 186             val = DMA_DRAIN_FIFO;
 187         val &= 0x0fffffff;
 188         val |= DMA_VER;
 189         break;
 190     case 1:
 191         s->dmaregs[0] |= DMA_LOADED;
 192         break;
 193     default:
 194         break;
 195     }
 196     s->dmaregs[saddr] = val;
 197 }
 198
 199 static CPUReadMemoryFunc *dma_mem_read[3] = {
 200     NULL,
 201     NULL,
 202     dma_mem_readl,
 203 };
 204
 205 static CPUWriteMemoryFunc *dma_mem_write[3] = {
 206     NULL,
 207     NULL,
 208     dma_mem_writel,
 209 };
 210
 211 static void dma_reset(void *opaque)
 212 {
 213     DMAState *s = opaque;
 214
 215     memset(s->dmaregs, 0, DMA_SIZE);
 216     s->dmaregs[0] = DMA_VER;
 217 }
 218
 219 static void dma_save(QEMUFile *f, void *opaque)
 220 {
 221     DMAState *s = opaque;
 222     unsigned int i;
 223
 224     for (i = 0; i < DMA_REGS; i++)
 225         qemu_put_be32s(f, &s->dmaregs[i]);
 226 }
 227
 228 static int dma_load(QEMUFile *f, void *opaque, int version_id)
 229 {
 230     DMAState *s = opaque;
 231     unsigned int i;
 232
 233     if (version_id != 2)
 234         return -EINVAL;
 235     for (i = 0; i < DMA_REGS; i++)
 236         qemu_get_be32s(f, &s->dmaregs[i]);
 237
 238     return 0;
 239 }
 240
 241 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
 242                        void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
 243 {
 244     DMAState *s;
 245     int dma_io_memory;
 246
 247     s = qemu_mallocz(sizeof(DMAState));
 248     if (!s)
 249         return NULL;
 250
 251     s->irq = parent_irq;
 252     s->iommu = iommu;
 253
 254     dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
 255     cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
 256
 257     register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
 258     qemu_register_reset(dma_reset, s);
 259     *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
 260
 261     *reset = &s->dev_reset;
 262
 263     return s;
 264 }