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sh4/r2d: update pci, usb and kernel management
[qemu/sh4.git] / target-ppc / translate.c
blobaa85ba74c778e6d133ea8044f21d56854bd75ca3
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44 //#define OPTIMIZE_FPRF_UPDATE
45
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 #if !defined(TARGET_PPC64)
53 + 10*4 + 22*5 /* SPE GPRh */
54 #endif
55 + 10*4 + 22*5 /* FPR */
56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
58 static TCGv cpu_gpr[32];
59 #if !defined(TARGET_PPC64)
60 static TCGv cpu_gprh[32];
61 #endif
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_msr;
67 static TCGv cpu_ctr;
68 static TCGv cpu_lr;
69 static TCGv cpu_xer;
70 static TCGv cpu_reserve;
71 static TCGv_i32 cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 static int done_init = 0;
81
82 if (done_init)
83 return;
84
85 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
86
87 p = cpu_reg_names;
88
89 for (i = 0; i < 8; i++) {
90 sprintf(p, "crf%d", i);
91 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
92 offsetof(CPUState, crf[i]), p);
93 p += 5;
94 }
95
96 for (i = 0; i < 32; i++) {
97 sprintf(p, "r%d", i);
98 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
99 offsetof(CPUState, gpr[i]), p);
100 p += (i < 10) ? 3 : 4;
101 #if !defined(TARGET_PPC64)
102 sprintf(p, "r%dH", i);
103 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
104 offsetof(CPUState, gprh[i]), p);
105 p += (i < 10) ? 4 : 5;
106 #endif
107
108 sprintf(p, "fp%d", i);
109 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
110 offsetof(CPUState, fpr[i]), p);
111 p += (i < 10) ? 4 : 5;
112
113 sprintf(p, "avr%dH", i);
114 #ifdef WORDS_BIGENDIAN
115 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
116 offsetof(CPUState, avr[i].u64[0]), p);
117 #else
118 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
119 offsetof(CPUState, avr[i].u64[1]), p);
120 #endif
121 p += (i < 10) ? 6 : 7;
122
123 sprintf(p, "avr%dL", i);
124 #ifdef WORDS_BIGENDIAN
125 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
126 offsetof(CPUState, avr[i].u64[1]), p);
127 #else
128 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
129 offsetof(CPUState, avr[i].u64[0]), p);
130 #endif
131 p += (i < 10) ? 6 : 7;
132 }
133
134 cpu_nip = tcg_global_mem_new(TCG_AREG0,
135 offsetof(CPUState, nip), "nip");
136
137 cpu_msr = tcg_global_mem_new(TCG_AREG0,
138 offsetof(CPUState, msr), "msr");
139
140 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
141 offsetof(CPUState, ctr), "ctr");
142
143 cpu_lr = tcg_global_mem_new(TCG_AREG0,
144 offsetof(CPUState, lr), "lr");
145
146 cpu_xer = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUState, xer), "xer");
148
149 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUState, reserve), "reserve");
151
152 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
153 offsetof(CPUState, fpscr), "fpscr");
154
155 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
156 offsetof(CPUState, access_type), "access_type");
157
158 /* register helpers */
159 #define GEN_HELPER 2
160 #include "helper.h"
161
162 done_init = 1;
163 }
164
165 #if defined(OPTIMIZE_FPRF_UPDATE)
166 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
167 static uint16_t **gen_fprf_ptr;
168 #endif
169
170 /* internal defines */
171 typedef struct DisasContext {
172 struct TranslationBlock *tb;
173 target_ulong nip;
174 uint32_t opcode;
175 uint32_t exception;
176 /* Routine used to access memory */
177 int mem_idx;
178 int access_type;
179 /* Translation flags */
180 int le_mode;
181 #if defined(TARGET_PPC64)
182 int sf_mode;
183 #endif
184 int fpu_enabled;
185 int altivec_enabled;
186 int spe_enabled;
187 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
188 int singlestep_enabled;
189 } DisasContext;
190
191 struct opc_handler_t {
192 /* invalid bits */
193 uint32_t inval;
194 /* instruction type */
195 uint64_t type;
196 /* handler */
197 void (*handler)(DisasContext *ctx);
198 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
199 const char *oname;
200 #endif
201 #if defined(DO_PPC_STATISTICS)
202 uint64_t count;
203 #endif
204 };
205
206 static always_inline void gen_reset_fpstatus (void)
207 {
208 #ifdef CONFIG_SOFTFLOAT
209 gen_op_reset_fpstatus();
210 #endif
211 }
212
213 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
214 {
215 TCGv_i32 t0 = tcg_temp_new_i32();
216
217 if (set_fprf != 0) {
218 /* This case might be optimized later */
219 #if defined(OPTIMIZE_FPRF_UPDATE)
220 *gen_fprf_ptr++ = gen_opc_ptr;
221 #endif
222 tcg_gen_movi_i32(t0, 1);
223 gen_helper_compute_fprf(t0, arg, t0);
224 if (unlikely(set_rc)) {
225 tcg_gen_mov_i32(cpu_crf[1], t0);
226 }
227 gen_helper_float_check_status();
228 } else if (unlikely(set_rc)) {
229 /* We always need to compute fpcc */
230 tcg_gen_movi_i32(t0, 0);
231 gen_helper_compute_fprf(t0, arg, t0);
232 tcg_gen_mov_i32(cpu_crf[1], t0);
233 if (set_fprf)
234 gen_helper_float_check_status();
235 }
236
237 tcg_temp_free_i32(t0);
238 }
239
240 static always_inline void gen_optimize_fprf (void)
241 {
242 #if defined(OPTIMIZE_FPRF_UPDATE)
243 uint16_t **ptr;
244
245 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
246 *ptr = INDEX_op_nop1;
247 gen_fprf_ptr = gen_fprf_buf;
248 #endif
249 }
250
251 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
252 {
253 if (ctx->access_type != access_type) {
254 tcg_gen_movi_i32(cpu_access_type, access_type);
255 ctx->access_type = access_type;
256 }
257 }
258
259 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
260 {
261 #if defined(TARGET_PPC64)
262 if (ctx->sf_mode)
263 tcg_gen_movi_tl(cpu_nip, nip);
264 else
265 #endif
266 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
267 }
268
269 #define GEN_EXCP(ctx, excp, error) \
270 do { \
271 TCGv_i32 t0 = tcg_const_i32(excp); \
272 TCGv_i32 t1 = tcg_const_i32(error); \
273 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
274 gen_update_nip(ctx, (ctx)->nip); \
275 } \
276 gen_helper_raise_exception_err(t0, t1); \
277 tcg_temp_free_i32(t0); \
278 tcg_temp_free_i32(t1); \
279 ctx->exception = (excp); \
280 } while (0)
281
282 #define GEN_EXCP_INVAL(ctx) \
283 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
284 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
285
286 #define GEN_EXCP_PRIVOPC(ctx) \
287 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
288 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
289
290 #define GEN_EXCP_PRIVREG(ctx) \
291 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
292 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
293
294 #define GEN_EXCP_NO_FP(ctx) \
295 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
296
297 #define GEN_EXCP_NO_AP(ctx) \
298 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
299
300 #define GEN_EXCP_NO_VR(ctx) \
301 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
302
303 /* Stop translation */
304 static always_inline void GEN_STOP (DisasContext *ctx)
305 {
306 gen_update_nip(ctx, ctx->nip);
307 ctx->exception = POWERPC_EXCP_STOP;
308 }
309
310 /* No need to update nip here, as execution flow will change */
311 static always_inline void GEN_SYNC (DisasContext *ctx)
312 {
313 ctx->exception = POWERPC_EXCP_SYNC;
314 }
315
316 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
317 static void gen_##name (DisasContext *ctx); \
318 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
319 static void gen_##name (DisasContext *ctx)
320
321 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
322 static void gen_##name (DisasContext *ctx); \
323 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
324 static void gen_##name (DisasContext *ctx)
325
326 typedef struct opcode_t {
327 unsigned char opc1, opc2, opc3;
328 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
329 unsigned char pad[5];
330 #else
331 unsigned char pad[1];
332 #endif
333 opc_handler_t handler;
334 const char *oname;
335 } opcode_t;
336
337 /*****************************************************************************/
338 /*** Instruction decoding ***/
339 #define EXTRACT_HELPER(name, shift, nb) \
340 static always_inline uint32_t name (uint32_t opcode) \
341 { \
342 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
343 }
344
345 #define EXTRACT_SHELPER(name, shift, nb) \
346 static always_inline int32_t name (uint32_t opcode) \
347 { \
348 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
349 }
350
351 /* Opcode part 1 */
352 EXTRACT_HELPER(opc1, 26, 6);
353 /* Opcode part 2 */
354 EXTRACT_HELPER(opc2, 1, 5);
355 /* Opcode part 3 */
356 EXTRACT_HELPER(opc3, 6, 5);
357 /* Update Cr0 flags */
358 EXTRACT_HELPER(Rc, 0, 1);
359 /* Destination */
360 EXTRACT_HELPER(rD, 21, 5);
361 /* Source */
362 EXTRACT_HELPER(rS, 21, 5);
363 /* First operand */
364 EXTRACT_HELPER(rA, 16, 5);
365 /* Second operand */
366 EXTRACT_HELPER(rB, 11, 5);
367 /* Third operand */
368 EXTRACT_HELPER(rC, 6, 5);
369 /*** Get CRn ***/
370 EXTRACT_HELPER(crfD, 23, 3);
371 EXTRACT_HELPER(crfS, 18, 3);
372 EXTRACT_HELPER(crbD, 21, 5);
373 EXTRACT_HELPER(crbA, 16, 5);
374 EXTRACT_HELPER(crbB, 11, 5);
375 /* SPR / TBL */
376 EXTRACT_HELPER(_SPR, 11, 10);
377 static always_inline uint32_t SPR (uint32_t opcode)
378 {
379 uint32_t sprn = _SPR(opcode);
380
381 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
382 }
383 /*** Get constants ***/
384 EXTRACT_HELPER(IMM, 12, 8);
385 /* 16 bits signed immediate value */
386 EXTRACT_SHELPER(SIMM, 0, 16);
387 /* 16 bits unsigned immediate value */
388 EXTRACT_HELPER(UIMM, 0, 16);
389 /* Bit count */
390 EXTRACT_HELPER(NB, 11, 5);
391 /* Shift count */
392 EXTRACT_HELPER(SH, 11, 5);
393 /* Mask start */
394 EXTRACT_HELPER(MB, 6, 5);
395 /* Mask end */
396 EXTRACT_HELPER(ME, 1, 5);
397 /* Trap operand */
398 EXTRACT_HELPER(TO, 21, 5);
399
400 EXTRACT_HELPER(CRM, 12, 8);
401 EXTRACT_HELPER(FM, 17, 8);
402 EXTRACT_HELPER(SR, 16, 4);
403 EXTRACT_HELPER(FPIMM, 12, 4);
404
405 /*** Jump target decoding ***/
406 /* Displacement */
407 EXTRACT_SHELPER(d, 0, 16);
408 /* Immediate address */
409 static always_inline target_ulong LI (uint32_t opcode)
410 {
411 return (opcode >> 0) & 0x03FFFFFC;
412 }
413
414 static always_inline uint32_t BD (uint32_t opcode)
415 {
416 return (opcode >> 0) & 0xFFFC;
417 }
418
419 EXTRACT_HELPER(BO, 21, 5);
420 EXTRACT_HELPER(BI, 16, 5);
421 /* Absolute/relative address */
422 EXTRACT_HELPER(AA, 1, 1);
423 /* Link */
424 EXTRACT_HELPER(LK, 0, 1);
425
426 /* Create a mask between <start> and <end> bits */
427 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
428 {
429 target_ulong ret;
430
431 #if defined(TARGET_PPC64)
432 if (likely(start == 0)) {
433 ret = UINT64_MAX << (63 - end);
434 } else if (likely(end == 63)) {
435 ret = UINT64_MAX >> start;
436 }
437 #else
438 if (likely(start == 0)) {
439 ret = UINT32_MAX << (31 - end);
440 } else if (likely(end == 31)) {
441 ret = UINT32_MAX >> start;
442 }
443 #endif
444 else {
445 ret = (((target_ulong)(-1ULL)) >> (start)) ^
446 (((target_ulong)(-1ULL) >> (end)) >> 1);
447 if (unlikely(start > end))
448 return ~ret;
449 }
450
451 return ret;
452 }
453
454 /*****************************************************************************/
455 /* PowerPC Instructions types definitions */
456 enum {
457 PPC_NONE = 0x0000000000000000ULL,
458 /* PowerPC base instructions set */
459 PPC_INSNS_BASE = 0x0000000000000001ULL,
460 /* integer operations instructions */
461 #define PPC_INTEGER PPC_INSNS_BASE
462 /* flow control instructions */
463 #define PPC_FLOW PPC_INSNS_BASE
464 /* virtual memory instructions */
465 #define PPC_MEM PPC_INSNS_BASE
466 /* ld/st with reservation instructions */
467 #define PPC_RES PPC_INSNS_BASE
468 /* spr/msr access instructions */
469 #define PPC_MISC PPC_INSNS_BASE
470 /* Deprecated instruction sets */
471 /* Original POWER instruction set */
472 PPC_POWER = 0x0000000000000002ULL,
473 /* POWER2 instruction set extension */
474 PPC_POWER2 = 0x0000000000000004ULL,
475 /* Power RTC support */
476 PPC_POWER_RTC = 0x0000000000000008ULL,
477 /* Power-to-PowerPC bridge (601) */
478 PPC_POWER_BR = 0x0000000000000010ULL,
479 /* 64 bits PowerPC instruction set */
480 PPC_64B = 0x0000000000000020ULL,
481 /* New 64 bits extensions (PowerPC 2.0x) */
482 PPC_64BX = 0x0000000000000040ULL,
483 /* 64 bits hypervisor extensions */
484 PPC_64H = 0x0000000000000080ULL,
485 /* New wait instruction (PowerPC 2.0x) */
486 PPC_WAIT = 0x0000000000000100ULL,
487 /* Time base mftb instruction */
488 PPC_MFTB = 0x0000000000000200ULL,
489
490 /* Fixed-point unit extensions */
491 /* PowerPC 602 specific */
492 PPC_602_SPEC = 0x0000000000000400ULL,
493 /* isel instruction */
494 PPC_ISEL = 0x0000000000000800ULL,
495 /* popcntb instruction */
496 PPC_POPCNTB = 0x0000000000001000ULL,
497 /* string load / store */
498 PPC_STRING = 0x0000000000002000ULL,
499
500 /* Floating-point unit extensions */
501 /* Optional floating point instructions */
502 PPC_FLOAT = 0x0000000000010000ULL,
503 /* New floating-point extensions (PowerPC 2.0x) */
504 PPC_FLOAT_EXT = 0x0000000000020000ULL,
505 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
506 PPC_FLOAT_FRES = 0x0000000000080000ULL,
507 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
508 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
509 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
510 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
511
512 /* Vector/SIMD extensions */
513 /* Altivec support */
514 PPC_ALTIVEC = 0x0000000001000000ULL,
515 /* PowerPC 2.03 SPE extension */
516 PPC_SPE = 0x0000000002000000ULL,
517 /* PowerPC 2.03 SPE floating-point extension */
518 PPC_SPEFPU = 0x0000000004000000ULL,
519
520 /* Optional memory control instructions */
521 PPC_MEM_TLBIA = 0x0000000010000000ULL,
522 PPC_MEM_TLBIE = 0x0000000020000000ULL,
523 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
524 /* sync instruction */
525 PPC_MEM_SYNC = 0x0000000080000000ULL,
526 /* eieio instruction */
527 PPC_MEM_EIEIO = 0x0000000100000000ULL,
528
529 /* Cache control instructions */
530 PPC_CACHE = 0x0000000200000000ULL,
531 /* icbi instruction */
532 PPC_CACHE_ICBI = 0x0000000400000000ULL,
533 /* dcbz instruction with fixed cache line size */
534 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
535 /* dcbz instruction with tunable cache line size */
536 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
537 /* dcba instruction */
538 PPC_CACHE_DCBA = 0x0000002000000000ULL,
539 /* Freescale cache locking instructions */
540 PPC_CACHE_LOCK = 0x0000004000000000ULL,
541
542 /* MMU related extensions */
543 /* external control instructions */
544 PPC_EXTERN = 0x0000010000000000ULL,
545 /* segment register access instructions */
546 PPC_SEGMENT = 0x0000020000000000ULL,
547 /* PowerPC 6xx TLB management instructions */
548 PPC_6xx_TLB = 0x0000040000000000ULL,
549 /* PowerPC 74xx TLB management instructions */
550 PPC_74xx_TLB = 0x0000080000000000ULL,
551 /* PowerPC 40x TLB management instructions */
552 PPC_40x_TLB = 0x0000100000000000ULL,
553 /* segment register access instructions for PowerPC 64 "bridge" */
554 PPC_SEGMENT_64B = 0x0000200000000000ULL,
555 /* SLB management */
556 PPC_SLBI = 0x0000400000000000ULL,
557
558 /* Embedded PowerPC dedicated instructions */
559 PPC_WRTEE = 0x0001000000000000ULL,
560 /* PowerPC 40x exception model */
561 PPC_40x_EXCP = 0x0002000000000000ULL,
562 /* PowerPC 405 Mac instructions */
563 PPC_405_MAC = 0x0004000000000000ULL,
564 /* PowerPC 440 specific instructions */
565 PPC_440_SPEC = 0x0008000000000000ULL,
566 /* BookE (embedded) PowerPC specification */
567 PPC_BOOKE = 0x0010000000000000ULL,
568 /* mfapidi instruction */
569 PPC_MFAPIDI = 0x0020000000000000ULL,
570 /* tlbiva instruction */
571 PPC_TLBIVA = 0x0040000000000000ULL,
572 /* tlbivax instruction */
573 PPC_TLBIVAX = 0x0080000000000000ULL,
574 /* PowerPC 4xx dedicated instructions */
575 PPC_4xx_COMMON = 0x0100000000000000ULL,
576 /* PowerPC 40x ibct instructions */
577 PPC_40x_ICBT = 0x0200000000000000ULL,
578 /* rfmci is not implemented in all BookE PowerPC */
579 PPC_RFMCI = 0x0400000000000000ULL,
580 /* rfdi instruction */
581 PPC_RFDI = 0x0800000000000000ULL,
582 /* DCR accesses */
583 PPC_DCR = 0x1000000000000000ULL,
584 /* DCR extended accesse */
585 PPC_DCRX = 0x2000000000000000ULL,
586 /* user-mode DCR access, implemented in PowerPC 460 */
587 PPC_DCRUX = 0x4000000000000000ULL,
588 };
589
590 /*****************************************************************************/
591 /* PowerPC instructions table */
592 #if HOST_LONG_BITS == 64
593 #define OPC_ALIGN 8
594 #else
595 #define OPC_ALIGN 4
596 #endif
597 #if defined(__APPLE__)
598 #define OPCODES_SECTION \
599 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
600 #else
601 #define OPCODES_SECTION \
602 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
603 #endif
604
605 #if defined(DO_PPC_STATISTICS)
606 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
607 OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 .oname = stringify(name), \
617 }, \
618 .oname = stringify(name), \
619 }
620 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
621 OPCODES_SECTION opcode_t opc_##name = { \
622 .opc1 = op1, \
623 .opc2 = op2, \
624 .opc3 = op3, \
625 .pad = { 0, }, \
626 .handler = { \
627 .inval = invl, \
628 .type = _typ, \
629 .handler = &gen_##name, \
630 .oname = onam, \
631 }, \
632 .oname = onam, \
633 }
634 #else
635 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
636 OPCODES_SECTION opcode_t opc_##name = { \
637 .opc1 = op1, \
638 .opc2 = op2, \
639 .opc3 = op3, \
640 .pad = { 0, }, \
641 .handler = { \
642 .inval = invl, \
643 .type = _typ, \
644 .handler = &gen_##name, \
645 }, \
646 .oname = stringify(name), \
647 }
648 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
649 OPCODES_SECTION opcode_t opc_##name = { \
650 .opc1 = op1, \
651 .opc2 = op2, \
652 .opc3 = op3, \
653 .pad = { 0, }, \
654 .handler = { \
655 .inval = invl, \
656 .type = _typ, \
657 .handler = &gen_##name, \
658 }, \
659 .oname = onam, \
660 }
661 #endif
662
663 #define GEN_OPCODE_MARK(name) \
664 OPCODES_SECTION opcode_t opc_##name = { \
665 .opc1 = 0xFF, \
666 .opc2 = 0xFF, \
667 .opc3 = 0xFF, \
668 .pad = { 0, }, \
669 .handler = { \
670 .inval = 0x00000000, \
671 .type = 0x00, \
672 .handler = NULL, \
673 }, \
674 .oname = stringify(name), \
675 }
676
677 /* SPR load/store helpers */
678 static always_inline void gen_load_spr(TCGv t, int reg)
679 {
680 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
681 }
682
683 static always_inline void gen_store_spr(int reg, TCGv t)
684 {
685 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
686 }
687
688 /* Start opcode list */
689 GEN_OPCODE_MARK(start);
690
691 /* Invalid instruction */
692 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
693 {
694 GEN_EXCP_INVAL(ctx);
695 }
696
697 static opc_handler_t invalid_handler = {
698 .inval = 0xFFFFFFFF,
699 .type = PPC_NONE,
700 .handler = gen_invalid,
701 };
702
703 /*** Integer comparison ***/
704
705 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
706 {
707 int l1, l2, l3;
708
709 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
710 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
711 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
712
713 l1 = gen_new_label();
714 l2 = gen_new_label();
715 l3 = gen_new_label();
716 if (s) {
717 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
718 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
719 } else {
720 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
722 }
723 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
724 tcg_gen_br(l3);
725 gen_set_label(l1);
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
727 tcg_gen_br(l3);
728 gen_set_label(l2);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
730 gen_set_label(l3);
731 }
732
733 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
734 {
735 TCGv t0 = tcg_const_local_tl(arg1);
736 gen_op_cmp(arg0, t0, s, crf);
737 tcg_temp_free(t0);
738 }
739
740 #if defined(TARGET_PPC64)
741 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
742 {
743 TCGv t0, t1;
744 t0 = tcg_temp_local_new();
745 t1 = tcg_temp_local_new();
746 if (s) {
747 tcg_gen_ext32s_tl(t0, arg0);
748 tcg_gen_ext32s_tl(t1, arg1);
749 } else {
750 tcg_gen_ext32u_tl(t0, arg0);
751 tcg_gen_ext32u_tl(t1, arg1);
752 }
753 gen_op_cmp(t0, t1, s, crf);
754 tcg_temp_free(t1);
755 tcg_temp_free(t0);
756 }
757
758 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
759 {
760 TCGv t0 = tcg_const_local_tl(arg1);
761 gen_op_cmp32(arg0, t0, s, crf);
762 tcg_temp_free(t0);
763 }
764 #endif
765
766 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
767 {
768 #if defined(TARGET_PPC64)
769 if (!(ctx->sf_mode))
770 gen_op_cmpi32(reg, 0, 1, 0);
771 else
772 #endif
773 gen_op_cmpi(reg, 0, 1, 0);
774 }
775
776 /* cmp */
777 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
778 {
779 #if defined(TARGET_PPC64)
780 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
781 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
782 1, crfD(ctx->opcode));
783 else
784 #endif
785 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 }
788
789 /* cmpi */
790 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
791 {
792 #if defined(TARGET_PPC64)
793 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
794 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
795 1, crfD(ctx->opcode));
796 else
797 #endif
798 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 }
801
802 /* cmpl */
803 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
804 {
805 #if defined(TARGET_PPC64)
806 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
807 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
808 0, crfD(ctx->opcode));
809 else
810 #endif
811 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 }
814
815 /* cmpli */
816 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
817 {
818 #if defined(TARGET_PPC64)
819 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
820 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
821 0, crfD(ctx->opcode));
822 else
823 #endif
824 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 }
827
828 /* isel (PowerPC 2.03 specification) */
829 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
830 {
831 int l1, l2;
832 uint32_t bi = rC(ctx->opcode);
833 uint32_t mask;
834 TCGv_i32 t0;
835
836 l1 = gen_new_label();
837 l2 = gen_new_label();
838
839 mask = 1 << (3 - (bi & 0x03));
840 t0 = tcg_temp_new_i32();
841 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
842 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
843 if (rA(ctx->opcode) == 0)
844 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
845 else
846 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
847 tcg_gen_br(l2);
848 gen_set_label(l1);
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
850 gen_set_label(l2);
851 tcg_temp_free_i32(t0);
852 }
853
854 /*** Integer arithmetic ***/
855
856 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
857 {
858 int l1;
859 TCGv t0;
860
861 l1 = gen_new_label();
862 /* Start with XER OV disabled, the most likely case */
863 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
864 t0 = tcg_temp_local_new();
865 tcg_gen_xor_tl(t0, arg0, arg1);
866 #if defined(TARGET_PPC64)
867 if (!ctx->sf_mode)
868 tcg_gen_ext32s_tl(t0, t0);
869 #endif
870 if (sub)
871 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
872 else
873 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
874 tcg_gen_xor_tl(t0, arg1, arg2);
875 #if defined(TARGET_PPC64)
876 if (!ctx->sf_mode)
877 tcg_gen_ext32s_tl(t0, t0);
878 #endif
879 if (sub)
880 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
881 else
882 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
883 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
884 gen_set_label(l1);
885 tcg_temp_free(t0);
886 }
887
888 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
889 {
890 int l1 = gen_new_label();
891
892 #if defined(TARGET_PPC64)
893 if (!(ctx->sf_mode)) {
894 TCGv t0, t1;
895 t0 = tcg_temp_new();
896 t1 = tcg_temp_new();
897
898 tcg_gen_ext32u_tl(t0, arg1);
899 tcg_gen_ext32u_tl(t1, arg2);
900 if (sub) {
901 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
902 } else {
903 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
904 }
905 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
906 gen_set_label(l1);
907 tcg_temp_free(t0);
908 tcg_temp_free(t1);
909 } else
910 #endif
911 {
912 if (sub) {
913 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
914 } else {
915 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
916 }
917 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
918 gen_set_label(l1);
919 }
920 }
921
922 /* Common add function */
923 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
924 int add_ca, int compute_ca, int compute_ov)
925 {
926 TCGv t0, t1;
927
928 if ((!compute_ca && !compute_ov) ||
929 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
930 t0 = ret;
931 } else {
932 t0 = tcg_temp_local_new();
933 }
934
935 if (add_ca) {
936 t1 = tcg_temp_local_new();
937 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
938 tcg_gen_shri_tl(t1, t1, XER_CA);
939 }
940
941 if (compute_ca && compute_ov) {
942 /* Start with XER CA and OV disabled, the most likely case */
943 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
944 } else if (compute_ca) {
945 /* Start with XER CA disabled, the most likely case */
946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
947 } else if (compute_ov) {
948 /* Start with XER OV disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
950 }
951
952 tcg_gen_add_tl(t0, arg1, arg2);
953
954 if (compute_ca) {
955 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
956 }
957 if (add_ca) {
958 tcg_gen_add_tl(t0, t0, t1);
959 gen_op_arith_compute_ca(ctx, t0, t1, 0);
960 tcg_temp_free(t1);
961 }
962 if (compute_ov) {
963 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
964 }
965
966 if (unlikely(Rc(ctx->opcode) != 0))
967 gen_set_Rc0(ctx, t0);
968
969 if (!TCGV_EQUAL(t0, ret)) {
970 tcg_gen_mov_tl(ret, t0);
971 tcg_temp_free(t0);
972 }
973 }
974 /* Add functions with two operands */
975 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
976 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
977 { \
978 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
979 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
980 add_ca, compute_ca, compute_ov); \
981 }
982 /* Add functions with one operand and one immediate */
983 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
984 add_ca, compute_ca, compute_ov) \
985 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
986 { \
987 TCGv t0 = tcg_const_local_tl(const_val); \
988 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
989 cpu_gpr[rA(ctx->opcode)], t0, \
990 add_ca, compute_ca, compute_ov); \
991 tcg_temp_free(t0); \
992 }
993
994 /* add add. addo addo. */
995 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
996 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
997 /* addc addc. addco addco. */
998 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
999 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1000 /* adde adde. addeo addeo. */
1001 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1002 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1003 /* addme addme. addmeo addmeo. */
1004 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1005 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1006 /* addze addze. addzeo addzeo.*/
1007 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1008 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1009 /* addi */
1010 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1011 {
1012 target_long simm = SIMM(ctx->opcode);
1013
1014 if (rA(ctx->opcode) == 0) {
1015 /* li case */
1016 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1017 } else {
1018 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1019 }
1020 }
1021 /* addic addic.*/
1022 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1023 int compute_Rc0)
1024 {
1025 target_long simm = SIMM(ctx->opcode);
1026
1027 /* Start with XER CA and OV disabled, the most likely case */
1028 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1029
1030 if (likely(simm != 0)) {
1031 TCGv t0 = tcg_temp_local_new();
1032 tcg_gen_addi_tl(t0, arg1, simm);
1033 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1034 tcg_gen_mov_tl(ret, t0);
1035 tcg_temp_free(t0);
1036 } else {
1037 tcg_gen_mov_tl(ret, arg1);
1038 }
1039 if (compute_Rc0) {
1040 gen_set_Rc0(ctx, ret);
1041 }
1042 }
1043 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044 {
1045 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1046 }
1047 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1048 {
1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1050 }
1051 /* addis */
1052 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1053 {
1054 target_long simm = SIMM(ctx->opcode);
1055
1056 if (rA(ctx->opcode) == 0) {
1057 /* lis case */
1058 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1059 } else {
1060 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1061 }
1062 }
1063
1064 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1065 int sign, int compute_ov)
1066 {
1067 int l1 = gen_new_label();
1068 int l2 = gen_new_label();
1069 TCGv_i32 t0 = tcg_temp_local_new_i32();
1070 TCGv_i32 t1 = tcg_temp_local_new_i32();
1071
1072 tcg_gen_trunc_tl_i32(t0, arg1);
1073 tcg_gen_trunc_tl_i32(t1, arg2);
1074 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1075 if (sign) {
1076 int l3 = gen_new_label();
1077 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1079 gen_set_label(l3);
1080 tcg_gen_div_i32(t0, t0, t1);
1081 } else {
1082 tcg_gen_divu_i32(t0, t0, t1);
1083 }
1084 if (compute_ov) {
1085 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1086 }
1087 tcg_gen_br(l2);
1088 gen_set_label(l1);
1089 if (sign) {
1090 tcg_gen_sari_i32(t0, t0, 31);
1091 } else {
1092 tcg_gen_movi_i32(t0, 0);
1093 }
1094 if (compute_ov) {
1095 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1096 }
1097 gen_set_label(l2);
1098 tcg_gen_extu_i32_tl(ret, t0);
1099 tcg_temp_free_i32(t0);
1100 tcg_temp_free_i32(t1);
1101 if (unlikely(Rc(ctx->opcode) != 0))
1102 gen_set_Rc0(ctx, ret);
1103 }
1104 /* Div functions */
1105 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1106 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1107 { \
1108 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1109 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1110 sign, compute_ov); \
1111 }
1112 /* divwu divwu. divwuo divwuo. */
1113 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1114 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1115 /* divw divw. divwo divwo. */
1116 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1117 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1118 #if defined(TARGET_PPC64)
1119 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1120 int sign, int compute_ov)
1121 {
1122 int l1 = gen_new_label();
1123 int l2 = gen_new_label();
1124
1125 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1126 if (sign) {
1127 int l3 = gen_new_label();
1128 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1130 gen_set_label(l3);
1131 tcg_gen_div_i64(ret, arg1, arg2);
1132 } else {
1133 tcg_gen_divu_i64(ret, arg1, arg2);
1134 }
1135 if (compute_ov) {
1136 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1137 }
1138 tcg_gen_br(l2);
1139 gen_set_label(l1);
1140 if (sign) {
1141 tcg_gen_sari_i64(ret, arg1, 63);
1142 } else {
1143 tcg_gen_movi_i64(ret, 0);
1144 }
1145 if (compute_ov) {
1146 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1147 }
1148 gen_set_label(l2);
1149 if (unlikely(Rc(ctx->opcode) != 0))
1150 gen_set_Rc0(ctx, ret);
1151 }
1152 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1153 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1154 { \
1155 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1156 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1157 sign, compute_ov); \
1158 }
1159 /* divwu divwu. divwuo divwuo. */
1160 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1161 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1162 /* divw divw. divwo divwo. */
1163 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1164 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1165 #endif
1166
1167 /* mulhw mulhw. */
1168 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1169 {
1170 TCGv_i64 t0, t1;
1171
1172 t0 = tcg_temp_new_i64();
1173 t1 = tcg_temp_new_i64();
1174 #if defined(TARGET_PPC64)
1175 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1176 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1177 tcg_gen_mul_i64(t0, t0, t1);
1178 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1179 #else
1180 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1181 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1182 tcg_gen_mul_i64(t0, t0, t1);
1183 tcg_gen_shri_i64(t0, t0, 32);
1184 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1185 #endif
1186 tcg_temp_free_i64(t0);
1187 tcg_temp_free_i64(t1);
1188 if (unlikely(Rc(ctx->opcode) != 0))
1189 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1190 }
1191 /* mulhwu mulhwu. */
1192 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1193 {
1194 TCGv_i64 t0, t1;
1195
1196 t0 = tcg_temp_new_i64();
1197 t1 = tcg_temp_new_i64();
1198 #if defined(TARGET_PPC64)
1199 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1200 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1201 tcg_gen_mul_i64(t0, t0, t1);
1202 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1203 #else
1204 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1205 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1206 tcg_gen_mul_i64(t0, t0, t1);
1207 tcg_gen_shri_i64(t0, t0, 32);
1208 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1209 #endif
1210 tcg_temp_free_i64(t0);
1211 tcg_temp_free_i64(t1);
1212 if (unlikely(Rc(ctx->opcode) != 0))
1213 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1214 }
1215 /* mullw mullw. */
1216 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1217 {
1218 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1219 cpu_gpr[rB(ctx->opcode)]);
1220 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1221 if (unlikely(Rc(ctx->opcode) != 0))
1222 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1223 }
1224 /* mullwo mullwo. */
1225 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1226 {
1227 int l1;
1228 TCGv_i64 t0, t1;
1229
1230 t0 = tcg_temp_new_i64();
1231 t1 = tcg_temp_new_i64();
1232 l1 = gen_new_label();
1233 /* Start with XER OV disabled, the most likely case */
1234 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1235 #if defined(TARGET_PPC64)
1236 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1237 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1238 #else
1239 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1240 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1241 #endif
1242 tcg_gen_mul_i64(t0, t0, t1);
1243 #if defined(TARGET_PPC64)
1244 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1245 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1246 #else
1247 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1248 tcg_gen_ext32s_i64(t1, t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1250 #endif
1251 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1252 gen_set_label(l1);
1253 tcg_temp_free_i64(t0);
1254 tcg_temp_free_i64(t1);
1255 if (unlikely(Rc(ctx->opcode) != 0))
1256 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1257 }
1258 /* mulli */
1259 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1260 {
1261 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1262 SIMM(ctx->opcode));
1263 }
1264 #if defined(TARGET_PPC64)
1265 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1266 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1267 { \
1268 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1269 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1270 if (unlikely(Rc(ctx->opcode) != 0)) \
1271 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1272 }
1273 /* mulhd mulhd. */
1274 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1275 /* mulhdu mulhdu. */
1276 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1277 /* mulld mulld. */
1278 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1279 {
1280 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1281 cpu_gpr[rB(ctx->opcode)]);
1282 if (unlikely(Rc(ctx->opcode) != 0))
1283 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1284 }
1285 /* mulldo mulldo. */
1286 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1287 #endif
1288
1289 /* neg neg. nego nego. */
1290 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1291 {
1292 int l1 = gen_new_label();
1293 int l2 = gen_new_label();
1294 TCGv t0 = tcg_temp_local_new();
1295 #if defined(TARGET_PPC64)
1296 if (ctx->sf_mode) {
1297 tcg_gen_mov_tl(t0, arg1);
1298 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1299 } else
1300 #endif
1301 {
1302 tcg_gen_ext32s_tl(t0, arg1);
1303 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1304 }
1305 tcg_gen_neg_tl(ret, arg1);
1306 if (ov_check) {
1307 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1308 }
1309 tcg_gen_br(l2);
1310 gen_set_label(l1);
1311 tcg_gen_mov_tl(ret, t0);
1312 if (ov_check) {
1313 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1314 }
1315 gen_set_label(l2);
1316 tcg_temp_free(t0);
1317 if (unlikely(Rc(ctx->opcode) != 0))
1318 gen_set_Rc0(ctx, ret);
1319 }
1320 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1321 {
1322 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1323 }
1324 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1325 {
1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1327 }
1328
1329 /* Common subf function */
1330 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1331 int add_ca, int compute_ca, int compute_ov)
1332 {
1333 TCGv t0, t1;
1334
1335 if ((!compute_ca && !compute_ov) ||
1336 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1337 t0 = ret;
1338 } else {
1339 t0 = tcg_temp_local_new();
1340 }
1341
1342 if (add_ca) {
1343 t1 = tcg_temp_local_new();
1344 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1345 tcg_gen_shri_tl(t1, t1, XER_CA);
1346 }
1347
1348 if (compute_ca && compute_ov) {
1349 /* Start with XER CA and OV disabled, the most likely case */
1350 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1351 } else if (compute_ca) {
1352 /* Start with XER CA disabled, the most likely case */
1353 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1354 } else if (compute_ov) {
1355 /* Start with XER OV disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1357 }
1358
1359 if (add_ca) {
1360 tcg_gen_not_tl(t0, arg1);
1361 tcg_gen_add_tl(t0, t0, arg2);
1362 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1363 tcg_gen_add_tl(t0, t0, t1);
1364 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1365 tcg_temp_free(t1);
1366 } else {
1367 tcg_gen_sub_tl(t0, arg2, arg1);
1368 if (compute_ca) {
1369 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1370 }
1371 }
1372 if (compute_ov) {
1373 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1374 }
1375
1376 if (unlikely(Rc(ctx->opcode) != 0))
1377 gen_set_Rc0(ctx, t0);
1378
1379 if (!TCGV_EQUAL(t0, ret)) {
1380 tcg_gen_mov_tl(ret, t0);
1381 tcg_temp_free(t0);
1382 }
1383 }
1384 /* Sub functions with Two operands functions */
1385 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1386 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1387 { \
1388 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1389 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1390 add_ca, compute_ca, compute_ov); \
1391 }
1392 /* Sub functions with one operand and one immediate */
1393 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1394 add_ca, compute_ca, compute_ov) \
1395 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1396 { \
1397 TCGv t0 = tcg_const_local_tl(const_val); \
1398 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1399 cpu_gpr[rA(ctx->opcode)], t0, \
1400 add_ca, compute_ca, compute_ov); \
1401 tcg_temp_free(t0); \
1402 }
1403 /* subf subf. subfo subfo. */
1404 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1405 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1406 /* subfc subfc. subfco subfco. */
1407 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1408 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1409 /* subfe subfe. subfeo subfo. */
1410 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1411 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1412 /* subfme subfme. subfmeo subfmeo. */
1413 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1414 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1415 /* subfze subfze. subfzeo subfzeo.*/
1416 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1417 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1418 /* subfic */
1419 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1420 {
1421 /* Start with XER CA and OV disabled, the most likely case */
1422 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1423 TCGv t0 = tcg_temp_local_new();
1424 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1425 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1426 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1427 tcg_temp_free(t1);
1428 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1429 tcg_temp_free(t0);
1430 }
1431
1432 /*** Integer logical ***/
1433 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1434 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1435 { \
1436 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1437 cpu_gpr[rB(ctx->opcode)]); \
1438 if (unlikely(Rc(ctx->opcode) != 0)) \
1439 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1440 }
1441
1442 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1443 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1444 { \
1445 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1446 if (unlikely(Rc(ctx->opcode) != 0)) \
1447 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1448 }
1449
1450 /* and & and. */
1451 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1452 /* andc & andc. */
1453 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1454 /* andi. */
1455 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1456 {
1457 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1458 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1459 }
1460 /* andis. */
1461 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1462 {
1463 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1464 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1465 }
1466 /* cntlzw */
1467 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1468 {
1469 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1470 if (unlikely(Rc(ctx->opcode) != 0))
1471 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1472 }
1473 /* eqv & eqv. */
1474 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1475 /* extsb & extsb. */
1476 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1477 /* extsh & extsh. */
1478 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1479 /* nand & nand. */
1480 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1481 /* nor & nor. */
1482 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1483 /* or & or. */
1484 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1485 {
1486 int rs, ra, rb;
1487
1488 rs = rS(ctx->opcode);
1489 ra = rA(ctx->opcode);
1490 rb = rB(ctx->opcode);
1491 /* Optimisation for mr. ri case */
1492 if (rs != ra || rs != rb) {
1493 if (rs != rb)
1494 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1495 else
1496 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1497 if (unlikely(Rc(ctx->opcode) != 0))
1498 gen_set_Rc0(ctx, cpu_gpr[ra]);
1499 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1500 gen_set_Rc0(ctx, cpu_gpr[rs]);
1501 #if defined(TARGET_PPC64)
1502 } else {
1503 int prio = 0;
1504
1505 switch (rs) {
1506 case 1:
1507 /* Set process priority to low */
1508 prio = 2;
1509 break;
1510 case 6:
1511 /* Set process priority to medium-low */
1512 prio = 3;
1513 break;
1514 case 2:
1515 /* Set process priority to normal */
1516 prio = 4;
1517 break;
1518 #if !defined(CONFIG_USER_ONLY)
1519 case 31:
1520 if (ctx->mem_idx > 0) {
1521 /* Set process priority to very low */
1522 prio = 1;
1523 }
1524 break;
1525 case 5:
1526 if (ctx->mem_idx > 0) {
1527 /* Set process priority to medium-hight */
1528 prio = 5;
1529 }
1530 break;
1531 case 3:
1532 if (ctx->mem_idx > 0) {
1533 /* Set process priority to high */
1534 prio = 6;
1535 }
1536 break;
1537 case 7:
1538 if (ctx->mem_idx > 1) {
1539 /* Set process priority to very high */
1540 prio = 7;
1541 }
1542 break;
1543 #endif
1544 default:
1545 /* nop */
1546 break;
1547 }
1548 if (prio) {
1549 TCGv t0 = tcg_temp_new();
1550 gen_load_spr(t0, SPR_PPR);
1551 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1552 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1553 gen_store_spr(SPR_PPR, t0);
1554 tcg_temp_free(t0);
1555 }
1556 #endif
1557 }
1558 }
1559 /* orc & orc. */
1560 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1561 /* xor & xor. */
1562 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1563 {
1564 /* Optimisation for "set to zero" case */
1565 if (rS(ctx->opcode) != rB(ctx->opcode))
1566 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1567 else
1568 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1569 if (unlikely(Rc(ctx->opcode) != 0))
1570 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1571 }
1572 /* ori */
1573 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1574 {
1575 target_ulong uimm = UIMM(ctx->opcode);
1576
1577 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1578 /* NOP */
1579 /* XXX: should handle special NOPs for POWER series */
1580 return;
1581 }
1582 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1583 }
1584 /* oris */
1585 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1586 {
1587 target_ulong uimm = UIMM(ctx->opcode);
1588
1589 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1590 /* NOP */
1591 return;
1592 }
1593 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1594 }
1595 /* xori */
1596 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1597 {
1598 target_ulong uimm = UIMM(ctx->opcode);
1599
1600 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1601 /* NOP */
1602 return;
1603 }
1604 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1605 }
1606 /* xoris */
1607 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1608 {
1609 target_ulong uimm = UIMM(ctx->opcode);
1610
1611 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1612 /* NOP */
1613 return;
1614 }
1615 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1616 }
1617 /* popcntb : PowerPC 2.03 specification */
1618 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1619 {
1620 #if defined(TARGET_PPC64)
1621 if (ctx->sf_mode)
1622 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1623 else
1624 #endif
1625 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 }
1627
1628 #if defined(TARGET_PPC64)
1629 /* extsw & extsw. */
1630 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1631 /* cntlzd */
1632 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1633 {
1634 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1635 if (unlikely(Rc(ctx->opcode) != 0))
1636 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1637 }
1638 #endif
1639
1640 /*** Integer rotate ***/
1641 /* rlwimi & rlwimi. */
1642 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1643 {
1644 uint32_t mb, me, sh;
1645
1646 mb = MB(ctx->opcode);
1647 me = ME(ctx->opcode);
1648 sh = SH(ctx->opcode);
1649 if (likely(sh == 0 && mb == 0 && me == 31)) {
1650 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1651 } else {
1652 target_ulong mask;
1653 TCGv t1;
1654 TCGv t0 = tcg_temp_new();
1655 #if defined(TARGET_PPC64)
1656 TCGv_i32 t2 = tcg_temp_new_i32();
1657 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1658 tcg_gen_rotli_i32(t2, t2, sh);
1659 tcg_gen_extu_i32_i64(t0, t2);
1660 tcg_temp_free_i32(t2);
1661 #else
1662 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1663 #endif
1664 #if defined(TARGET_PPC64)
1665 mb += 32;
1666 me += 32;
1667 #endif
1668 mask = MASK(mb, me);
1669 t1 = tcg_temp_new();
1670 tcg_gen_andi_tl(t0, t0, mask);
1671 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1672 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1673 tcg_temp_free(t0);
1674 tcg_temp_free(t1);
1675 }
1676 if (unlikely(Rc(ctx->opcode) != 0))
1677 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1678 }
1679 /* rlwinm & rlwinm. */
1680 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1681 {
1682 uint32_t mb, me, sh;
1683
1684 sh = SH(ctx->opcode);
1685 mb = MB(ctx->opcode);
1686 me = ME(ctx->opcode);
1687
1688 if (likely(mb == 0 && me == (31 - sh))) {
1689 if (likely(sh == 0)) {
1690 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1691 } else {
1692 TCGv t0 = tcg_temp_new();
1693 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1694 tcg_gen_shli_tl(t0, t0, sh);
1695 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1696 tcg_temp_free(t0);
1697 }
1698 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1699 TCGv t0 = tcg_temp_new();
1700 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1701 tcg_gen_shri_tl(t0, t0, mb);
1702 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1703 tcg_temp_free(t0);
1704 } else {
1705 TCGv t0 = tcg_temp_new();
1706 #if defined(TARGET_PPC64)
1707 TCGv_i32 t1 = tcg_temp_new_i32();
1708 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1709 tcg_gen_rotli_i32(t1, t1, sh);
1710 tcg_gen_extu_i32_i64(t0, t1);
1711 tcg_temp_free_i32(t1);
1712 #else
1713 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1714 #endif
1715 #if defined(TARGET_PPC64)
1716 mb += 32;
1717 me += 32;
1718 #endif
1719 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1720 tcg_temp_free(t0);
1721 }
1722 if (unlikely(Rc(ctx->opcode) != 0))
1723 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1724 }
1725 /* rlwnm & rlwnm. */
1726 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1727 {
1728 uint32_t mb, me;
1729 TCGv t0;
1730 #if defined(TARGET_PPC64)
1731 TCGv_i32 t1, t2;
1732 #endif
1733
1734 mb = MB(ctx->opcode);
1735 me = ME(ctx->opcode);
1736 t0 = tcg_temp_new();
1737 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1738 #if defined(TARGET_PPC64)
1739 t1 = tcg_temp_new_i32();
1740 t2 = tcg_temp_new_i32();
1741 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1742 tcg_gen_trunc_i64_i32(t2, t0);
1743 tcg_gen_rotl_i32(t1, t1, t2);
1744 tcg_gen_extu_i32_i64(t0, t1);
1745 tcg_temp_free_i32(t1);
1746 tcg_temp_free_i32(t2);
1747 #else
1748 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1749 #endif
1750 if (unlikely(mb != 0 || me != 31)) {
1751 #if defined(TARGET_PPC64)
1752 mb += 32;
1753 me += 32;
1754 #endif
1755 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1756 } else {
1757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1758 }
1759 tcg_temp_free(t0);
1760 if (unlikely(Rc(ctx->opcode) != 0))
1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763
1764 #if defined(TARGET_PPC64)
1765 #define GEN_PPC64_R2(name, opc1, opc2) \
1766 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1767 { \
1768 gen_##name(ctx, 0); \
1769 } \
1770 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1771 PPC_64B) \
1772 { \
1773 gen_##name(ctx, 1); \
1774 }
1775 #define GEN_PPC64_R4(name, opc1, opc2) \
1776 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1777 { \
1778 gen_##name(ctx, 0, 0); \
1779 } \
1780 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1781 PPC_64B) \
1782 { \
1783 gen_##name(ctx, 0, 1); \
1784 } \
1785 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1786 PPC_64B) \
1787 { \
1788 gen_##name(ctx, 1, 0); \
1789 } \
1790 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1791 PPC_64B) \
1792 { \
1793 gen_##name(ctx, 1, 1); \
1794 }
1795
1796 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1797 uint32_t me, uint32_t sh)
1798 {
1799 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1800 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1801 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1802 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1803 } else {
1804 TCGv t0 = tcg_temp_new();
1805 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1806 if (likely(mb == 0 && me == 63)) {
1807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1808 } else {
1809 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1810 }
1811 tcg_temp_free(t0);
1812 }
1813 if (unlikely(Rc(ctx->opcode) != 0))
1814 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1815 }
1816 /* rldicl - rldicl. */
1817 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1818 {
1819 uint32_t sh, mb;
1820
1821 sh = SH(ctx->opcode) | (shn << 5);
1822 mb = MB(ctx->opcode) | (mbn << 5);
1823 gen_rldinm(ctx, mb, 63, sh);
1824 }
1825 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1826 /* rldicr - rldicr. */
1827 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1828 {
1829 uint32_t sh, me;
1830
1831 sh = SH(ctx->opcode) | (shn << 5);
1832 me = MB(ctx->opcode) | (men << 5);
1833 gen_rldinm(ctx, 0, me, sh);
1834 }
1835 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1836 /* rldic - rldic. */
1837 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1838 {
1839 uint32_t sh, mb;
1840
1841 sh = SH(ctx->opcode) | (shn << 5);
1842 mb = MB(ctx->opcode) | (mbn << 5);
1843 gen_rldinm(ctx, mb, 63 - sh, sh);
1844 }
1845 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1846
1847 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1848 uint32_t me)
1849 {
1850 TCGv t0;
1851
1852 mb = MB(ctx->opcode);
1853 me = ME(ctx->opcode);
1854 t0 = tcg_temp_new();
1855 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1856 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1857 if (unlikely(mb != 0 || me != 63)) {
1858 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1859 } else {
1860 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1861 }
1862 tcg_temp_free(t0);
1863 if (unlikely(Rc(ctx->opcode) != 0))
1864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1865 }
1866
1867 /* rldcl - rldcl. */
1868 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1869 {
1870 uint32_t mb;
1871
1872 mb = MB(ctx->opcode) | (mbn << 5);
1873 gen_rldnm(ctx, mb, 63);
1874 }
1875 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1876 /* rldcr - rldcr. */
1877 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1878 {
1879 uint32_t me;
1880
1881 me = MB(ctx->opcode) | (men << 5);
1882 gen_rldnm(ctx, 0, me);
1883 }
1884 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1885 /* rldimi - rldimi. */
1886 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1887 {
1888 uint32_t sh, mb, me;
1889
1890 sh = SH(ctx->opcode) | (shn << 5);
1891 mb = MB(ctx->opcode) | (mbn << 5);
1892 me = 63 - sh;
1893 if (unlikely(sh == 0 && mb == 0)) {
1894 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1895 } else {
1896 TCGv t0, t1;
1897 target_ulong mask;
1898
1899 t0 = tcg_temp_new();
1900 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1901 t1 = tcg_temp_new();
1902 mask = MASK(mb, me);
1903 tcg_gen_andi_tl(t0, t0, mask);
1904 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1905 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1906 tcg_temp_free(t0);
1907 tcg_temp_free(t1);
1908 }
1909 if (unlikely(Rc(ctx->opcode) != 0))
1910 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1911 }
1912 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1913 #endif
1914
1915 /*** Integer shift ***/
1916 /* slw & slw. */
1917 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1918 {
1919 TCGv t0;
1920 int l1, l2;
1921 l1 = gen_new_label();
1922 l2 = gen_new_label();
1923
1924 t0 = tcg_temp_local_new();
1925 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1926 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1927 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1928 tcg_gen_br(l2);
1929 gen_set_label(l1);
1930 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1931 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1932 gen_set_label(l2);
1933 tcg_temp_free(t0);
1934 if (unlikely(Rc(ctx->opcode) != 0))
1935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1936 }
1937 /* sraw & sraw. */
1938 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1939 {
1940 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1941 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1942 if (unlikely(Rc(ctx->opcode) != 0))
1943 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1944 }
1945 /* srawi & srawi. */
1946 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1947 {
1948 int sh = SH(ctx->opcode);
1949 if (sh != 0) {
1950 int l1, l2;
1951 TCGv t0;
1952 l1 = gen_new_label();
1953 l2 = gen_new_label();
1954 t0 = tcg_temp_local_new();
1955 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1956 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1957 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1958 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1959 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1960 tcg_gen_br(l2);
1961 gen_set_label(l1);
1962 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1963 gen_set_label(l2);
1964 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1965 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1966 tcg_temp_free(t0);
1967 } else {
1968 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1970 }
1971 if (unlikely(Rc(ctx->opcode) != 0))
1972 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1973 }
1974 /* srw & srw. */
1975 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1976 {
1977 TCGv t0, t1;
1978 int l1, l2;
1979 l1 = gen_new_label();
1980 l2 = gen_new_label();
1981
1982 t0 = tcg_temp_local_new();
1983 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1984 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1985 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1986 tcg_gen_br(l2);
1987 gen_set_label(l1);
1988 t1 = tcg_temp_new();
1989 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1990 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1991 tcg_temp_free(t1);
1992 gen_set_label(l2);
1993 tcg_temp_free(t0);
1994 if (unlikely(Rc(ctx->opcode) != 0))
1995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1996 }
1997 #if defined(TARGET_PPC64)
1998 /* sld & sld. */
1999 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2000 {
2001 TCGv t0;
2002 int l1, l2;
2003 l1 = gen_new_label();
2004 l2 = gen_new_label();
2005
2006 t0 = tcg_temp_local_new();
2007 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2008 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2009 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2010 tcg_gen_br(l2);
2011 gen_set_label(l1);
2012 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2013 gen_set_label(l2);
2014 tcg_temp_free(t0);
2015 if (unlikely(Rc(ctx->opcode) != 0))
2016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2017 }
2018 /* srad & srad. */
2019 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2020 {
2021 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2022 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2023 if (unlikely(Rc(ctx->opcode) != 0))
2024 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2025 }
2026 /* sradi & sradi. */
2027 static always_inline void gen_sradi (DisasContext *ctx, int n)
2028 {
2029 int sh = SH(ctx->opcode) + (n << 5);
2030 if (sh != 0) {
2031 int l1, l2;
2032 TCGv t0;
2033 l1 = gen_new_label();
2034 l2 = gen_new_label();
2035 t0 = tcg_temp_local_new();
2036 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2037 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2038 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2039 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2040 tcg_gen_br(l2);
2041 gen_set_label(l1);
2042 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2043 gen_set_label(l2);
2044 tcg_temp_free(t0);
2045 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2046 } else {
2047 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2048 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2049 }
2050 if (unlikely(Rc(ctx->opcode) != 0))
2051 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2052 }
2053 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2054 {
2055 gen_sradi(ctx, 0);
2056 }
2057 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2058 {
2059 gen_sradi(ctx, 1);
2060 }
2061 /* srd & srd. */
2062 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2063 {
2064 TCGv t0;
2065 int l1, l2;
2066 l1 = gen_new_label();
2067 l2 = gen_new_label();
2068
2069 t0 = tcg_temp_local_new();
2070 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2071 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2072 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2073 tcg_gen_br(l2);
2074 gen_set_label(l1);
2075 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2076 gen_set_label(l2);
2077 tcg_temp_free(t0);
2078 if (unlikely(Rc(ctx->opcode) != 0))
2079 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2080 }
2081 #endif
2082
2083 /*** Floating-Point arithmetic ***/
2084 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2085 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2086 { \
2087 if (unlikely(!ctx->fpu_enabled)) { \
2088 GEN_EXCP_NO_FP(ctx); \
2089 return; \
2090 } \
2091 gen_reset_fpstatus(); \
2092 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2093 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2094 if (isfloat) { \
2095 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2096 } \
2097 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2098 Rc(ctx->opcode) != 0); \
2099 }
2100
2101 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2102 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2103 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2104
2105 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2106 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2107 { \
2108 if (unlikely(!ctx->fpu_enabled)) { \
2109 GEN_EXCP_NO_FP(ctx); \
2110 return; \
2111 } \
2112 gen_reset_fpstatus(); \
2113 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2114 cpu_fpr[rB(ctx->opcode)]); \
2115 if (isfloat) { \
2116 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2117 } \
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2119 set_fprf, Rc(ctx->opcode) != 0); \
2120 }
2121 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2122 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2123 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2124
2125 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2126 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2127 { \
2128 if (unlikely(!ctx->fpu_enabled)) { \
2129 GEN_EXCP_NO_FP(ctx); \
2130 return; \
2131 } \
2132 gen_reset_fpstatus(); \
2133 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2134 cpu_fpr[rC(ctx->opcode)]); \
2135 if (isfloat) { \
2136 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2137 } \
2138 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2139 set_fprf, Rc(ctx->opcode) != 0); \
2140 }
2141 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2142 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2143 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144
2145 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2146 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2147 { \
2148 if (unlikely(!ctx->fpu_enabled)) { \
2149 GEN_EXCP_NO_FP(ctx); \
2150 return; \
2151 } \
2152 gen_reset_fpstatus(); \
2153 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2154 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2155 set_fprf, Rc(ctx->opcode) != 0); \
2156 }
2157
2158 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2159 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2160 { \
2161 if (unlikely(!ctx->fpu_enabled)) { \
2162 GEN_EXCP_NO_FP(ctx); \
2163 return; \
2164 } \
2165 gen_reset_fpstatus(); \
2166 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2167 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2168 set_fprf, Rc(ctx->opcode) != 0); \
2169 }
2170
2171 /* fadd - fadds */
2172 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2173 /* fdiv - fdivs */
2174 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2175 /* fmul - fmuls */
2176 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2177
2178 /* fre */
2179 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2180
2181 /* fres */
2182 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2183
2184 /* frsqrte */
2185 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2186
2187 /* frsqrtes */
2188 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2189 {
2190 if (unlikely(!ctx->fpu_enabled)) {
2191 GEN_EXCP_NO_FP(ctx);
2192 return;
2193 }
2194 gen_reset_fpstatus();
2195 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2196 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2197 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2198 }
2199
2200 /* fsel */
2201 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2202 /* fsub - fsubs */
2203 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2204 /* Optional: */
2205 /* fsqrt */
2206 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2207 {
2208 if (unlikely(!ctx->fpu_enabled)) {
2209 GEN_EXCP_NO_FP(ctx);
2210 return;
2211 }
2212 gen_reset_fpstatus();
2213 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2214 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2215 }
2216
2217 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2218 {
2219 if (unlikely(!ctx->fpu_enabled)) {
2220 GEN_EXCP_NO_FP(ctx);
2221 return;
2222 }
2223 gen_reset_fpstatus();
2224 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2225 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2226 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2227 }
2228
2229 /*** Floating-Point multiply-and-add ***/
2230 /* fmadd - fmadds */
2231 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2232 /* fmsub - fmsubs */
2233 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2234 /* fnmadd - fnmadds */
2235 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2236 /* fnmsub - fnmsubs */
2237 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2238
2239 /*** Floating-Point round & convert ***/
2240 /* fctiw */
2241 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2242 /* fctiwz */
2243 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2244 /* frsp */
2245 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2246 #if defined(TARGET_PPC64)
2247 /* fcfid */
2248 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2249 /* fctid */
2250 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2251 /* fctidz */
2252 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2253 #endif
2254
2255 /* frin */
2256 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2257 /* friz */
2258 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2259 /* frip */
2260 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2261 /* frim */
2262 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2263
2264 /*** Floating-Point compare ***/
2265 /* fcmpo */
2266 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2267 {
2268 if (unlikely(!ctx->fpu_enabled)) {
2269 GEN_EXCP_NO_FP(ctx);
2270 return;
2271 }
2272 gen_reset_fpstatus();
2273 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2274 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2275 gen_helper_float_check_status();
2276 }
2277
2278 /* fcmpu */
2279 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2280 {
2281 if (unlikely(!ctx->fpu_enabled)) {
2282 GEN_EXCP_NO_FP(ctx);
2283 return;
2284 }
2285 gen_reset_fpstatus();
2286 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2287 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2288 gen_helper_float_check_status();
2289 }
2290
2291 /*** Floating-point move ***/
2292 /* fabs */
2293 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2294 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2295
2296 /* fmr - fmr. */
2297 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2298 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2299 {
2300 if (unlikely(!ctx->fpu_enabled)) {
2301 GEN_EXCP_NO_FP(ctx);
2302 return;
2303 }
2304 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2305 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2306 }
2307
2308 /* fnabs */
2309 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2310 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2311 /* fneg */
2312 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2313 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2314
2315 /*** Floating-Point status & ctrl register ***/
2316 /* mcrfs */
2317 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2318 {
2319 int bfa;
2320
2321 if (unlikely(!ctx->fpu_enabled)) {
2322 GEN_EXCP_NO_FP(ctx);
2323 return;
2324 }
2325 gen_optimize_fprf();
2326 bfa = 4 * (7 - crfS(ctx->opcode));
2327 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2328 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2329 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2330 }
2331
2332 /* mffs */
2333 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2334 {
2335 if (unlikely(!ctx->fpu_enabled)) {
2336 GEN_EXCP_NO_FP(ctx);
2337 return;
2338 }
2339 gen_optimize_fprf();
2340 gen_reset_fpstatus();
2341 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2342 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2343 }
2344
2345 /* mtfsb0 */
2346 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2347 {
2348 uint8_t crb;
2349
2350 if (unlikely(!ctx->fpu_enabled)) {
2351 GEN_EXCP_NO_FP(ctx);
2352 return;
2353 }
2354 crb = 32 - (crbD(ctx->opcode) >> 2);
2355 gen_optimize_fprf();
2356 gen_reset_fpstatus();
2357 if (likely(crb != 30 && crb != 29))
2358 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
2359 if (unlikely(Rc(ctx->opcode) != 0)) {
2360 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2361 }
2362 }
2363
2364 /* mtfsb1 */
2365 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2366 {
2367 uint8_t crb;
2368
2369 if (unlikely(!ctx->fpu_enabled)) {
2370 GEN_EXCP_NO_FP(ctx);
2371 return;
2372 }
2373 crb = 32 - (crbD(ctx->opcode) >> 2);
2374 gen_optimize_fprf();
2375 gen_reset_fpstatus();
2376 /* XXX: we pretend we can only do IEEE floating-point computations */
2377 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2378 TCGv_i32 t0 = tcg_const_i32(crb);
2379 gen_helper_fpscr_setbit(t0);
2380 tcg_temp_free_i32(t0);
2381 }
2382 if (unlikely(Rc(ctx->opcode) != 0)) {
2383 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2384 }
2385 /* We can raise a differed exception */
2386 gen_helper_float_check_status();
2387 }
2388
2389 /* mtfsf */
2390 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2391 {
2392 TCGv_i32 t0;
2393
2394 if (unlikely(!ctx->fpu_enabled)) {
2395 GEN_EXCP_NO_FP(ctx);
2396 return;
2397 }
2398 gen_optimize_fprf();
2399 gen_reset_fpstatus();
2400 t0 = tcg_const_i32(FM(ctx->opcode));
2401 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2402 tcg_temp_free_i32(t0);
2403 if (unlikely(Rc(ctx->opcode) != 0)) {
2404 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2405 }
2406 /* We can raise a differed exception */
2407 gen_helper_float_check_status();
2408 }
2409
2410 /* mtfsfi */
2411 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2412 {
2413 int bf, sh;
2414 TCGv_i64 t0;
2415 TCGv_i32 t1;
2416
2417 if (unlikely(!ctx->fpu_enabled)) {
2418 GEN_EXCP_NO_FP(ctx);
2419 return;
2420 }
2421 bf = crbD(ctx->opcode) >> 2;
2422 sh = 7 - bf;
2423 gen_optimize_fprf();
2424 gen_reset_fpstatus();
2425 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2426 t1 = tcg_const_i32(1 << sh);
2427 gen_helper_store_fpscr(t0, t1);
2428 tcg_temp_free_i64(t0);
2429 tcg_temp_free_i32(t1);
2430 if (unlikely(Rc(ctx->opcode) != 0)) {
2431 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2432 }
2433 /* We can raise a differed exception */
2434 gen_helper_float_check_status();
2435 }
2436
2437 /*** Addressing modes ***/
2438 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2439 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2440 {
2441 target_long simm = SIMM(ctx->opcode);
2442
2443 simm &= ~maskl;
2444 if (rA(ctx->opcode) == 0) {
2445 #if defined(TARGET_PPC64)
2446 if (!ctx->sf_mode) {
2447 tcg_gen_movi_tl(EA, (uint32_t)simm);
2448 } else
2449 #endif
2450 tcg_gen_movi_tl(EA, simm);
2451 } else if (likely(simm != 0)) {
2452 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2453 #if defined(TARGET_PPC64)
2454 if (!ctx->sf_mode) {
2455 tcg_gen_ext32u_tl(EA, EA);
2456 }
2457 #endif
2458 } else {
2459 #if defined(TARGET_PPC64)
2460 if (!ctx->sf_mode) {
2461 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2462 } else
2463 #endif
2464 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2465 }
2466 }
2467
2468 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2469 {
2470 if (rA(ctx->opcode) == 0) {
2471 #if defined(TARGET_PPC64)
2472 if (!ctx->sf_mode) {
2473 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2474 } else
2475 #endif
2476 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2477 } else {
2478 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2479 #if defined(TARGET_PPC64)
2480 if (!ctx->sf_mode) {
2481 tcg_gen_ext32u_tl(EA, EA);
2482 }
2483 #endif
2484 }
2485 }
2486
2487 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2488 {
2489 if (rA(ctx->opcode) == 0) {
2490 tcg_gen_movi_tl(EA, 0);
2491 } else {
2492 #if defined(TARGET_PPC64)
2493 if (!ctx->sf_mode) {
2494 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2495 } else
2496 #endif
2497 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2498 }
2499 }
2500
2501 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2502 {
2503 tcg_gen_addi_tl(ret, arg1, val);
2504 #if defined(TARGET_PPC64)
2505 if (!ctx->sf_mode) {
2506 tcg_gen_ext32u_tl(ret, ret);
2507 }
2508 #endif
2509 }
2510
2511 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2512 {
2513 int l1 = gen_new_label();
2514 TCGv t0 = tcg_temp_new();
2515 TCGv_i32 t1, t2;
2516 /* NIP cannot be restored if the memory exception comes from an helper */
2517 gen_update_nip(ctx, ctx->nip - 4);
2518 tcg_gen_andi_tl(t0, EA, mask);
2519 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2520 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2521 t2 = tcg_const_i32(0);
2522 gen_helper_raise_exception_err(t1, t2);
2523 tcg_temp_free_i32(t1);
2524 tcg_temp_free_i32(t2);
2525 gen_set_label(l1);
2526 tcg_temp_free(t0);
2527 }
2528
2529 /*** Integer load ***/
2530 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2531 {
2532 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2533 }
2534
2535 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2536 {
2537 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2538 }
2539
2540 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2541 {
2542 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2543 if (unlikely(ctx->le_mode)) {
2544 #if defined(TARGET_PPC64)
2545 TCGv_i32 t0 = tcg_temp_new_i32();
2546 tcg_gen_trunc_tl_i32(t0, arg1);
2547 tcg_gen_bswap16_i32(t0, t0);
2548 tcg_gen_extu_i32_tl(arg1, t0);
2549 tcg_temp_free_i32(t0);
2550 #else
2551 tcg_gen_bswap16_i32(arg1, arg1);
2552 #endif
2553 }
2554 }
2555
2556 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2557 {
2558 if (unlikely(ctx->le_mode)) {
2559 #if defined(TARGET_PPC64)
2560 TCGv_i32 t0;
2561 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2562 t0 = tcg_temp_new_i32();
2563 tcg_gen_trunc_tl_i32(t0, arg1);
2564 tcg_gen_bswap16_i32(t0, t0);
2565 tcg_gen_extu_i32_tl(arg1, t0);
2566 tcg_gen_ext16s_tl(arg1, arg1);
2567 tcg_temp_free_i32(t0);
2568 #else
2569 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2570 tcg_gen_bswap16_i32(arg1, arg1);
2571 tcg_gen_ext16s_i32(arg1, arg1);
2572 #endif
2573 } else {
2574 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2575 }
2576 }
2577
2578 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2579 {
2580 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2581 if (unlikely(ctx->le_mode)) {
2582 #if defined(TARGET_PPC64)
2583 TCGv_i32 t0 = tcg_temp_new_i32();
2584 tcg_gen_trunc_tl_i32(t0, arg1);
2585 tcg_gen_bswap_i32(t0, t0);
2586 tcg_gen_extu_i32_tl(arg1, t0);
2587 tcg_temp_free_i32(t0);
2588 #else
2589 tcg_gen_bswap_i32(arg1, arg1);
2590 #endif
2591 }
2592 }
2593
2594 #if defined(TARGET_PPC64)
2595 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2596 {
2597 if (unlikely(ctx->mem_idx)) {
2598 TCGv_i32 t0;
2599 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2600 t0 = tcg_temp_new_i32();
2601 tcg_gen_trunc_tl_i32(t0, arg1);
2602 tcg_gen_bswap_i32(t0, t0);
2603 tcg_gen_ext_i32_tl(arg1, t0);
2604 tcg_temp_free_i32(t0);
2605 } else
2606 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2607 }
2608 #endif
2609
2610 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2611 {
2612 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2613 if (unlikely(ctx->le_mode)) {
2614 tcg_gen_bswap_i64(arg1, arg1);
2615 }
2616 }
2617
2618 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2619 {
2620 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2621 }
2622
2623 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2624 {
2625 if (unlikely(ctx->le_mode)) {
2626 #if defined(TARGET_PPC64)
2627 TCGv_i32 t0;
2628 TCGv t1;
2629 t0 = tcg_temp_new_i32();
2630 tcg_gen_trunc_tl_i32(t0, arg1);
2631 tcg_gen_ext16u_i32(t0, t0);
2632 tcg_gen_bswap16_i32(t0, t0);
2633 t1 = tcg_temp_new();
2634 tcg_gen_extu_i32_tl(t1, t0);
2635 tcg_temp_free_i32(t0);
2636 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2637 tcg_temp_free(t1);
2638 #else
2639 TCGv t0 = tcg_temp_new();
2640 tcg_gen_ext16u_tl(t0, arg1);
2641 tcg_gen_bswap16_i32(t0, t0);
2642 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2643 tcg_temp_free(t0);
2644 #endif
2645 } else {
2646 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2647 }
2648 }
2649
2650 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2651 {
2652 if (unlikely(ctx->le_mode)) {
2653 #if defined(TARGET_PPC64)
2654 TCGv_i32 t0;
2655 TCGv t1;
2656 t0 = tcg_temp_new_i32();
2657 tcg_gen_trunc_tl_i32(t0, arg1);
2658 tcg_gen_bswap_i32(t0, t0);
2659 t1 = tcg_temp_new();
2660 tcg_gen_extu_i32_tl(t1, t0);
2661 tcg_temp_free_i32(t0);
2662 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2663 tcg_temp_free(t1);
2664 #else
2665 TCGv t0 = tcg_temp_new_i32();
2666 tcg_gen_bswap_i32(t0, arg1);
2667 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2668 tcg_temp_free(t0);
2669 #endif
2670 } else {
2671 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2672 }
2673 }
2674
2675 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2676 {
2677 if (unlikely(ctx->le_mode)) {
2678 TCGv_i64 t0 = tcg_temp_new_i64();
2679 tcg_gen_bswap_i64(t0, arg1);
2680 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2681 tcg_temp_free_i64(t0);
2682 } else
2683 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2684 }
2685
2686 #define GEN_LD(name, ldop, opc, type) \
2687 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2688 { \
2689 TCGv EA; \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2695 }
2696
2697 #define GEN_LDU(name, ldop, opc, type) \
2698 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2699 { \
2700 TCGv EA; \
2701 if (unlikely(rA(ctx->opcode) == 0 || \
2702 rA(ctx->opcode) == rD(ctx->opcode))) { \
2703 GEN_EXCP_INVAL(ctx); \
2704 return; \
2705 } \
2706 gen_set_access_type(ctx, ACCESS_INT); \
2707 EA = tcg_temp_new(); \
2708 if (type == PPC_64B) \
2709 gen_addr_imm_index(ctx, EA, 0x03); \
2710 else \
2711 gen_addr_imm_index(ctx, EA, 0); \
2712 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2713 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2714 tcg_temp_free(EA); \
2715 }
2716
2717 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2718 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2719 { \
2720 TCGv EA; \
2721 if (unlikely(rA(ctx->opcode) == 0 || \
2722 rA(ctx->opcode) == rD(ctx->opcode))) { \
2723 GEN_EXCP_INVAL(ctx); \
2724 return; \
2725 } \
2726 gen_set_access_type(ctx, ACCESS_INT); \
2727 EA = tcg_temp_new(); \
2728 gen_addr_reg_index(ctx, EA); \
2729 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2730 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2731 tcg_temp_free(EA); \
2732 }
2733
2734 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2735 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2736 { \
2737 TCGv EA; \
2738 gen_set_access_type(ctx, ACCESS_INT); \
2739 EA = tcg_temp_new(); \
2740 gen_addr_reg_index(ctx, EA); \
2741 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2742 tcg_temp_free(EA); \
2743 }
2744
2745 #define GEN_LDS(name, ldop, op, type) \
2746 GEN_LD(name, ldop, op | 0x20, type); \
2747 GEN_LDU(name, ldop, op | 0x21, type); \
2748 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2749 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2750
2751 /* lbz lbzu lbzux lbzx */
2752 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2753 /* lha lhau lhaux lhax */
2754 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2755 /* lhz lhzu lhzux lhzx */
2756 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2757 /* lwz lwzu lwzux lwzx */
2758 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2759 #if defined(TARGET_PPC64)
2760 /* lwaux */
2761 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2762 /* lwax */
2763 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2764 /* ldux */
2765 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2766 /* ldx */
2767 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2768 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2769 {
2770 TCGv EA;
2771 if (Rc(ctx->opcode)) {
2772 if (unlikely(rA(ctx->opcode) == 0 ||
2773 rA(ctx->opcode) == rD(ctx->opcode))) {
2774 GEN_EXCP_INVAL(ctx);
2775 return;
2776 }
2777 }
2778 gen_set_access_type(ctx, ACCESS_INT);
2779 EA = tcg_temp_new();
2780 gen_addr_imm_index(ctx, EA, 0x03);
2781 if (ctx->opcode & 0x02) {
2782 /* lwa (lwau is undefined) */
2783 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2784 } else {
2785 /* ld - ldu */
2786 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2787 }
2788 if (Rc(ctx->opcode))
2789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2790 tcg_temp_free(EA);
2791 }
2792 /* lq */
2793 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2794 {
2795 #if defined(CONFIG_USER_ONLY)
2796 GEN_EXCP_PRIVOPC(ctx);
2797 #else
2798 int ra, rd;
2799 TCGv EA;
2800
2801 /* Restore CPU state */
2802 if (unlikely(ctx->mem_idx == 0)) {
2803 GEN_EXCP_PRIVOPC(ctx);
2804 return;
2805 }
2806 ra = rA(ctx->opcode);
2807 rd = rD(ctx->opcode);
2808 if (unlikely((rd & 1) || rd == ra)) {
2809 GEN_EXCP_INVAL(ctx);
2810 return;
2811 }
2812 if (unlikely(ctx->le_mode)) {
2813 /* Little-endian mode is not handled */
2814 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2815 return;
2816 }
2817 gen_set_access_type(ctx, ACCESS_INT);
2818 EA = tcg_temp_new();
2819 gen_addr_imm_index(ctx, EA, 0x0F);
2820 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2821 gen_addr_add(ctx, EA, EA, 8);
2822 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2823 tcg_temp_free(EA);
2824 #endif
2825 }
2826 #endif
2827
2828 /*** Integer store ***/
2829 #define GEN_ST(name, stop, opc, type) \
2830 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2831 { \
2832 TCGv EA; \
2833 gen_set_access_type(ctx, ACCESS_INT); \
2834 EA = tcg_temp_new(); \
2835 gen_addr_imm_index(ctx, EA, 0); \
2836 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2837 tcg_temp_free(EA); \
2838 }
2839
2840 #define GEN_STU(name, stop, opc, type) \
2841 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2842 { \
2843 TCGv EA; \
2844 if (unlikely(rA(ctx->opcode) == 0)) { \
2845 GEN_EXCP_INVAL(ctx); \
2846 return; \
2847 } \
2848 gen_set_access_type(ctx, ACCESS_INT); \
2849 EA = tcg_temp_new(); \
2850 if (type == PPC_64B) \
2851 gen_addr_imm_index(ctx, EA, 0x03); \
2852 else \
2853 gen_addr_imm_index(ctx, EA, 0); \
2854 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2856 tcg_temp_free(EA); \
2857 }
2858
2859 #define GEN_STUX(name, stop, opc2, opc3, type) \
2860 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2861 { \
2862 TCGv EA; \
2863 if (unlikely(rA(ctx->opcode) == 0)) { \
2864 GEN_EXCP_INVAL(ctx); \
2865 return; \
2866 } \
2867 gen_set_access_type(ctx, ACCESS_INT); \
2868 EA = tcg_temp_new(); \
2869 gen_addr_reg_index(ctx, EA); \
2870 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2871 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2872 tcg_temp_free(EA); \
2873 }
2874
2875 #define GEN_STX(name, stop, opc2, opc3, type) \
2876 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2877 { \
2878 TCGv EA; \
2879 gen_set_access_type(ctx, ACCESS_INT); \
2880 EA = tcg_temp_new(); \
2881 gen_addr_reg_index(ctx, EA); \
2882 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2883 tcg_temp_free(EA); \
2884 }
2885
2886 #define GEN_STS(name, stop, op, type) \
2887 GEN_ST(name, stop, op | 0x20, type); \
2888 GEN_STU(name, stop, op | 0x21, type); \
2889 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2890 GEN_STX(name, stop, 0x17, op | 0x00, type)
2891
2892 /* stb stbu stbux stbx */
2893 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2894 /* sth sthu sthux sthx */
2895 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2896 /* stw stwu stwux stwx */
2897 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2898 #if defined(TARGET_PPC64)
2899 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2900 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2901 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2902 {
2903 int rs;
2904 TCGv EA;
2905
2906 rs = rS(ctx->opcode);
2907 if ((ctx->opcode & 0x3) == 0x2) {
2908 #if defined(CONFIG_USER_ONLY)
2909 GEN_EXCP_PRIVOPC(ctx);
2910 #else
2911 /* stq */
2912 if (unlikely(ctx->mem_idx == 0)) {
2913 GEN_EXCP_PRIVOPC(ctx);
2914 return;
2915 }
2916 if (unlikely(rs & 1)) {
2917 GEN_EXCP_INVAL(ctx);
2918 return;
2919 }
2920 if (unlikely(ctx->le_mode)) {
2921 /* Little-endian mode is not handled */
2922 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2923 return;
2924 }
2925 gen_set_access_type(ctx, ACCESS_INT);
2926 EA = tcg_temp_new();
2927 gen_addr_imm_index(ctx, EA, 0x03);
2928 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2929 gen_addr_add(ctx, EA, EA, 8);
2930 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2931 tcg_temp_free(EA);
2932 #endif
2933 } else {
2934 /* std / stdu */
2935 if (Rc(ctx->opcode)) {
2936 if (unlikely(rA(ctx->opcode) == 0)) {
2937 GEN_EXCP_INVAL(ctx);
2938 return;
2939 }
2940 }
2941 gen_set_access_type(ctx, ACCESS_INT);
2942 EA = tcg_temp_new();
2943 gen_addr_imm_index(ctx, EA, 0x03);
2944 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2945 if (Rc(ctx->opcode))
2946 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2947 tcg_temp_free(EA);
2948 }
2949 }
2950 #endif
2951 /*** Integer load and store with byte reverse ***/
2952 /* lhbrx */
2953 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2954 {
2955 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2956 if (likely(!ctx->le_mode)) {
2957 #if defined(TARGET_PPC64)
2958 TCGv_i32 t0 = tcg_temp_new_i32();
2959 tcg_gen_trunc_tl_i32(t0, arg1);
2960 tcg_gen_bswap16_i32(t0, t0);
2961 tcg_gen_extu_i32_tl(arg1, t0);
2962 tcg_temp_free_i32(t0);
2963 #else
2964 tcg_gen_bswap16_i32(arg1, arg1);
2965 #endif
2966 }
2967 }
2968 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2969
2970 /* lwbrx */
2971 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2972 {
2973 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2974 if (likely(!ctx->le_mode)) {
2975 #if defined(TARGET_PPC64)
2976 TCGv_i32 t0 = tcg_temp_new_i32();
2977 tcg_gen_trunc_tl_i32(t0, arg1);
2978 tcg_gen_bswap_i32(t0, t0);
2979 tcg_gen_extu_i32_tl(arg1, t0);
2980 tcg_temp_free_i32(t0);
2981 #else
2982 tcg_gen_bswap_i32(arg1, arg1);
2983 #endif
2984 }
2985 }
2986 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2987
2988 /* sthbrx */
2989 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2990 {
2991 if (likely(!ctx->le_mode)) {
2992 #if defined(TARGET_PPC64)
2993 TCGv_i32 t0;
2994 TCGv t1;
2995 t0 = tcg_temp_new_i32();
2996 tcg_gen_trunc_tl_i32(t0, arg1);
2997 tcg_gen_ext16u_i32(t0, t0);
2998 tcg_gen_bswap16_i32(t0, t0);
2999 t1 = tcg_temp_new();
3000 tcg_gen_extu_i32_tl(t1, t0);
3001 tcg_temp_free_i32(t0);
3002 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3003 tcg_temp_free(t1);
3004 #else
3005 TCGv t0 = tcg_temp_new();
3006 tcg_gen_ext16u_tl(t0, arg1);
3007 tcg_gen_bswap16_i32(t0, t0);
3008 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3009 tcg_temp_free(t0);
3010 #endif
3011 } else {
3012 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3013 }
3014 }
3015 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3016
3017 /* stwbrx */
3018 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3019 {
3020 if (likely(!ctx->le_mode)) {
3021 #if defined(TARGET_PPC64)
3022 TCGv_i32 t0;
3023 TCGv t1;
3024 t0 = tcg_temp_new_i32();
3025 tcg_gen_trunc_tl_i32(t0, arg1);
3026 tcg_gen_bswap_i32(t0, t0);
3027 t1 = tcg_temp_new();
3028 tcg_gen_extu_i32_tl(t1, t0);
3029 tcg_temp_free_i32(t0);
3030 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3031 tcg_temp_free(t1);
3032 #else
3033 TCGv t0 = tcg_temp_new_i32();
3034 tcg_gen_bswap_i32(t0, arg1);
3035 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3036 tcg_temp_free(t0);
3037 #endif
3038 } else {
3039 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3040 }
3041 }
3042 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3043
3044 /*** Integer load and store multiple ***/
3045 /* lmw */
3046 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3047 {
3048 TCGv t0;
3049 TCGv_i32 t1;
3050 gen_set_access_type(ctx, ACCESS_INT);
3051 /* NIP cannot be restored if the memory exception comes from an helper */
3052 gen_update_nip(ctx, ctx->nip - 4);
3053 t0 = tcg_temp_new();
3054 t1 = tcg_const_i32(rD(ctx->opcode));
3055 gen_addr_imm_index(ctx, t0, 0);
3056 gen_helper_lmw(t0, t1);
3057 tcg_temp_free(t0);
3058 tcg_temp_free_i32(t1);
3059 }
3060
3061 /* stmw */
3062 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3063 {
3064 TCGv t0;
3065 TCGv_i32 t1;
3066 gen_set_access_type(ctx, ACCESS_INT);
3067 /* NIP cannot be restored if the memory exception comes from an helper */
3068 gen_update_nip(ctx, ctx->nip - 4);
3069 t0 = tcg_temp_new();
3070 t1 = tcg_const_i32(rS(ctx->opcode));
3071 gen_addr_imm_index(ctx, t0, 0);
3072 gen_helper_stmw(t0, t1);
3073 tcg_temp_free(t0);
3074 tcg_temp_free_i32(t1);
3075 }
3076
3077 /*** Integer load and store strings ***/
3078 /* lswi */
3079 /* PowerPC32 specification says we must generate an exception if
3080 * rA is in the range of registers to be loaded.
3081 * In an other hand, IBM says this is valid, but rA won't be loaded.
3082 * For now, I'll follow the spec...
3083 */
3084 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3085 {
3086 TCGv t0;
3087 TCGv_i32 t1, t2;
3088 int nb = NB(ctx->opcode);
3089 int start = rD(ctx->opcode);
3090 int ra = rA(ctx->opcode);
3091 int nr;
3092
3093 if (nb == 0)
3094 nb = 32;
3095 nr = nb / 4;
3096 if (unlikely(((start + nr) > 32 &&
3097 start <= ra && (start + nr - 32) > ra) ||
3098 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3099 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3100 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
3101 return;
3102 }
3103 gen_set_access_type(ctx, ACCESS_INT);
3104 /* NIP cannot be restored if the memory exception comes from an helper */
3105 gen_update_nip(ctx, ctx->nip - 4);
3106 t0 = tcg_temp_new();
3107 gen_addr_register(ctx, t0);
3108 t1 = tcg_const_i32(nb);
3109 t2 = tcg_const_i32(start);
3110 gen_helper_lsw(t0, t1, t2);
3111 tcg_temp_free(t0);
3112 tcg_temp_free_i32(t1);
3113 tcg_temp_free_i32(t2);
3114 }
3115
3116 /* lswx */
3117 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3118 {
3119 TCGv t0;
3120 TCGv_i32 t1, t2, t3;
3121 gen_set_access_type(ctx, ACCESS_INT);
3122 /* NIP cannot be restored if the memory exception comes from an helper */
3123 gen_update_nip(ctx, ctx->nip - 4);
3124 t0 = tcg_temp_new();
3125 gen_addr_reg_index(ctx, t0);
3126 t1 = tcg_const_i32(rD(ctx->opcode));
3127 t2 = tcg_const_i32(rA(ctx->opcode));
3128 t3 = tcg_const_i32(rB(ctx->opcode));
3129 gen_helper_lswx(t0, t1, t2, t3);
3130 tcg_temp_free(t0);
3131 tcg_temp_free_i32(t1);
3132 tcg_temp_free_i32(t2);
3133 tcg_temp_free_i32(t3);
3134 }
3135
3136 /* stswi */
3137 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3138 {
3139 TCGv t0;
3140 TCGv_i32 t1, t2;
3141 int nb = NB(ctx->opcode);
3142 gen_set_access_type(ctx, ACCESS_INT);
3143 /* NIP cannot be restored if the memory exception comes from an helper */
3144 gen_update_nip(ctx, ctx->nip - 4);
3145 t0 = tcg_temp_new();
3146 gen_addr_register(ctx, t0);
3147 if (nb == 0)
3148 nb = 32;
3149 t1 = tcg_const_i32(nb);
3150 t2 = tcg_const_i32(rS(ctx->opcode));
3151 gen_helper_stsw(t0, t1, t2);
3152 tcg_temp_free(t0);
3153 tcg_temp_free_i32(t1);
3154 tcg_temp_free_i32(t2);
3155 }
3156
3157 /* stswx */
3158 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3159 {
3160 TCGv t0;
3161 TCGv_i32 t1, t2;
3162 gen_set_access_type(ctx, ACCESS_INT);
3163 /* NIP cannot be restored if the memory exception comes from an helper */
3164 gen_update_nip(ctx, ctx->nip - 4);
3165 t0 = tcg_temp_new();
3166 gen_addr_reg_index(ctx, t0);
3167 t1 = tcg_temp_new_i32();
3168 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3169 tcg_gen_andi_i32(t1, t1, 0x7F);
3170 t2 = tcg_const_i32(rS(ctx->opcode));
3171 gen_helper_stsw(t0, t1, t2);
3172 tcg_temp_free(t0);
3173 tcg_temp_free_i32(t1);
3174 tcg_temp_free_i32(t2);
3175 }
3176
3177 /*** Memory synchronisation ***/
3178 /* eieio */
3179 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3180 {
3181 }
3182
3183 /* isync */
3184 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3185 {
3186 GEN_STOP(ctx);
3187 }
3188
3189 /* lwarx */
3190 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3191 {
3192 TCGv t0;
3193 gen_set_access_type(ctx, ACCESS_RES);
3194 t0 = tcg_temp_local_new();
3195 gen_addr_reg_index(ctx, t0);
3196 gen_check_align(ctx, t0, 0x03);
3197 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3198 tcg_gen_mov_tl(cpu_reserve, t0);
3199 tcg_temp_free(t0);
3200 }
3201
3202 /* stwcx. */
3203 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3204 {
3205 int l1;
3206 TCGv t0;
3207 gen_set_access_type(ctx, ACCESS_RES);
3208 t0 = tcg_temp_local_new();
3209 gen_addr_reg_index(ctx, t0);
3210 gen_check_align(ctx, t0, 0x03);
3211 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3212 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3213 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3214 l1 = gen_new_label();
3215 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3216 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3217 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3218 gen_set_label(l1);
3219 tcg_gen_movi_tl(cpu_reserve, -1);
3220 tcg_temp_free(t0);
3221 }
3222
3223 #if defined(TARGET_PPC64)
3224 /* ldarx */
3225 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3226 {
3227 TCGv t0;
3228 gen_set_access_type(ctx, ACCESS_RES);
3229 t0 = tcg_temp_local_new();
3230 gen_addr_reg_index(ctx, t0);
3231 gen_check_align(ctx, t0, 0x07);
3232 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3233 tcg_gen_mov_tl(cpu_reserve, t0);
3234 tcg_temp_free(t0);
3235 }
3236
3237 /* stdcx. */
3238 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3239 {
3240 int l1;
3241 TCGv t0;
3242 gen_set_access_type(ctx, ACCESS_RES);
3243 t0 = tcg_temp_local_new();
3244 gen_addr_reg_index(ctx, t0);
3245 gen_check_align(ctx, t0, 0x07);
3246 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3247 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3248 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3249 l1 = gen_new_label();
3250 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3251 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3252 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3253 gen_set_label(l1);
3254 tcg_gen_movi_tl(cpu_reserve, -1);
3255 tcg_temp_free(t0);
3256 }
3257 #endif /* defined(TARGET_PPC64) */
3258
3259 /* sync */
3260 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3261 {
3262 }
3263
3264 /* wait */
3265 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3266 {
3267 TCGv_i32 t0 = tcg_temp_new_i32();
3268 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3269 tcg_temp_free_i32(t0);
3270 /* Stop translation, as the CPU is supposed to sleep from now */
3271 GEN_EXCP(ctx, EXCP_HLT, 1);
3272 }
3273
3274 /*** Floating-point load ***/
3275 #define GEN_LDF(name, ldop, opc, type) \
3276 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3277 { \
3278 TCGv EA; \
3279 if (unlikely(!ctx->fpu_enabled)) { \
3280 GEN_EXCP_NO_FP(ctx); \
3281 return; \
3282 } \
3283 gen_set_access_type(ctx, ACCESS_FLOAT); \
3284 EA = tcg_temp_new(); \
3285 gen_addr_imm_index(ctx, EA, 0); \
3286 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3287 tcg_temp_free(EA); \
3288 }
3289
3290 #define GEN_LDUF(name, ldop, opc, type) \
3291 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3292 { \
3293 TCGv EA; \
3294 if (unlikely(!ctx->fpu_enabled)) { \
3295 GEN_EXCP_NO_FP(ctx); \
3296 return; \
3297 } \
3298 if (unlikely(rA(ctx->opcode) == 0)) { \
3299 GEN_EXCP_INVAL(ctx); \
3300 return; \
3301 } \
3302 gen_set_access_type(ctx, ACCESS_FLOAT); \
3303 EA = tcg_temp_new(); \
3304 gen_addr_imm_index(ctx, EA, 0); \
3305 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3306 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3307 tcg_temp_free(EA); \
3308 }
3309
3310 #define GEN_LDUXF(name, ldop, opc, type) \
3311 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3312 { \
3313 TCGv EA; \
3314 if (unlikely(!ctx->fpu_enabled)) { \
3315 GEN_EXCP_NO_FP(ctx); \
3316 return; \
3317 } \
3318 if (unlikely(rA(ctx->opcode) == 0)) { \
3319 GEN_EXCP_INVAL(ctx); \
3320 return; \
3321 } \
3322 gen_set_access_type(ctx, ACCESS_FLOAT); \
3323 EA = tcg_temp_new(); \
3324 gen_addr_reg_index(ctx, EA); \
3325 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3326 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3327 tcg_temp_free(EA); \
3328 }
3329
3330 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3331 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3332 { \
3333 TCGv EA; \
3334 if (unlikely(!ctx->fpu_enabled)) { \
3335 GEN_EXCP_NO_FP(ctx); \
3336 return; \
3337 } \
3338 gen_set_access_type(ctx, ACCESS_FLOAT); \
3339 EA = tcg_temp_new(); \
3340 gen_addr_reg_index(ctx, EA); \
3341 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3342 tcg_temp_free(EA); \
3343 }
3344
3345 #define GEN_LDFS(name, ldop, op, type) \
3346 GEN_LDF(name, ldop, op | 0x20, type); \
3347 GEN_LDUF(name, ldop, op | 0x21, type); \
3348 GEN_LDUXF(name, ldop, op | 0x01, type); \
3349 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3350
3351 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3352 {
3353 TCGv t0 = tcg_temp_new();
3354 TCGv_i32 t1 = tcg_temp_new_i32();
3355 gen_qemu_ld32u(ctx, t0, arg2);
3356 tcg_gen_trunc_tl_i32(t1, t0);
3357 tcg_temp_free(t0);
3358 gen_helper_float32_to_float64(arg1, t1);
3359 tcg_temp_free_i32(t1);
3360 }
3361
3362 /* lfd lfdu lfdux lfdx */
3363 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3364 /* lfs lfsu lfsux lfsx */
3365 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3366
3367 /*** Floating-point store ***/
3368 #define GEN_STF(name, stop, opc, type) \
3369 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3370 { \
3371 TCGv EA; \
3372 if (unlikely(!ctx->fpu_enabled)) { \
3373 GEN_EXCP_NO_FP(ctx); \
3374 return; \
3375 } \
3376 gen_set_access_type(ctx, ACCESS_FLOAT); \
3377 EA = tcg_temp_new(); \
3378 gen_addr_imm_index(ctx, EA, 0); \
3379 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3380 tcg_temp_free(EA); \
3381 }
3382
3383 #define GEN_STUF(name, stop, opc, type) \
3384 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3385 { \
3386 TCGv EA; \
3387 if (unlikely(!ctx->fpu_enabled)) { \
3388 GEN_EXCP_NO_FP(ctx); \
3389 return; \
3390 } \
3391 if (unlikely(rA(ctx->opcode) == 0)) { \
3392 GEN_EXCP_INVAL(ctx); \
3393 return; \
3394 } \
3395 gen_set_access_type(ctx, ACCESS_FLOAT); \
3396 EA = tcg_temp_new(); \
3397 gen_addr_imm_index(ctx, EA, 0); \
3398 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3399 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3400 tcg_temp_free(EA); \
3401 }
3402
3403 #define GEN_STUXF(name, stop, opc, type) \
3404 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3405 { \
3406 TCGv EA; \
3407 if (unlikely(!ctx->fpu_enabled)) { \
3408 GEN_EXCP_NO_FP(ctx); \
3409 return; \
3410 } \
3411 if (unlikely(rA(ctx->opcode) == 0)) { \
3412 GEN_EXCP_INVAL(ctx); \
3413 return; \
3414 } \
3415 gen_set_access_type(ctx, ACCESS_FLOAT); \
3416 EA = tcg_temp_new(); \
3417 gen_addr_reg_index(ctx, EA); \
3418 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3419 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3420 tcg_temp_free(EA); \
3421 }
3422
3423 #define GEN_STXF(name, stop, opc2, opc3, type) \
3424 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3425 { \
3426 TCGv EA; \
3427 if (unlikely(!ctx->fpu_enabled)) { \
3428 GEN_EXCP_NO_FP(ctx); \
3429 return; \
3430 } \
3431 gen_set_access_type(ctx, ACCESS_FLOAT); \
3432 EA = tcg_temp_new(); \
3433 gen_addr_reg_index(ctx, EA); \
3434 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3435 tcg_temp_free(EA); \
3436 }
3437
3438 #define GEN_STFS(name, stop, op, type) \
3439 GEN_STF(name, stop, op | 0x20, type); \
3440 GEN_STUF(name, stop, op | 0x21, type); \
3441 GEN_STUXF(name, stop, op | 0x01, type); \
3442 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3443
3444 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3445 {
3446 TCGv_i32 t0 = tcg_temp_new_i32();
3447 TCGv t1 = tcg_temp_new();
3448 gen_helper_float64_to_float32(t0, arg1);
3449 tcg_gen_extu_i32_tl(t1, t0);
3450 tcg_temp_free_i32(t0);
3451 gen_qemu_st32(ctx, t1, arg2);
3452 tcg_temp_free(t1);
3453 }
3454
3455 /* stfd stfdu stfdux stfdx */
3456 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3457 /* stfs stfsu stfsux stfsx */
3458 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3459
3460 /* Optional: */
3461 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3462 {
3463 TCGv t0 = tcg_temp_new();
3464 tcg_gen_trunc_i64_tl(t0, arg1),
3465 gen_qemu_st32(ctx, t0, arg2);
3466 tcg_temp_free(t0);
3467 }
3468 /* stfiwx */
3469 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3470
3471 /*** Branch ***/
3472 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3473 target_ulong dest)
3474 {
3475 TranslationBlock *tb;
3476 tb = ctx->tb;
3477 #if defined(TARGET_PPC64)
3478 if (!ctx->sf_mode)
3479 dest = (uint32_t) dest;
3480 #endif
3481 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3482 likely(!ctx->singlestep_enabled)) {
3483 tcg_gen_goto_tb(n);
3484 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3485 tcg_gen_exit_tb((long)tb + n);
3486 } else {
3487 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3488 if (unlikely(ctx->singlestep_enabled)) {
3489 if ((ctx->singlestep_enabled &
3490 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3491 ctx->exception == POWERPC_EXCP_BRANCH) {
3492 target_ulong tmp = ctx->nip;
3493 ctx->nip = dest;
3494 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3495 ctx->nip = tmp;
3496 }
3497 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3498 gen_update_nip(ctx, dest);
3499 gen_helper_raise_debug();
3500 }
3501 }
3502 tcg_gen_exit_tb(0);
3503 }
3504 }
3505
3506 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3507 {
3508 #if defined(TARGET_PPC64)
3509 if (ctx->sf_mode == 0)
3510 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3511 else
3512 #endif
3513 tcg_gen_movi_tl(cpu_lr, nip);
3514 }
3515
3516 /* b ba bl bla */
3517 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3518 {
3519 target_ulong li, target;
3520
3521 ctx->exception = POWERPC_EXCP_BRANCH;
3522 /* sign extend LI */
3523 #if defined(TARGET_PPC64)
3524 if (ctx->sf_mode)
3525 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3526 else
3527 #endif
3528 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3529 if (likely(AA(ctx->opcode) == 0))
3530 target = ctx->nip + li - 4;
3531 else
3532 target = li;
3533 if (LK(ctx->opcode))
3534 gen_setlr(ctx, ctx->nip);
3535 gen_goto_tb(ctx, 0, target);
3536 }
3537
3538 #define BCOND_IM 0
3539 #define BCOND_LR 1
3540 #define BCOND_CTR 2
3541
3542 static always_inline void gen_bcond (DisasContext *ctx, int type)
3543 {
3544 uint32_t bo = BO(ctx->opcode);
3545 int l1 = gen_new_label();
3546 TCGv target;
3547
3548 ctx->exception = POWERPC_EXCP_BRANCH;
3549 if (type == BCOND_LR || type == BCOND_CTR) {
3550 target = tcg_temp_local_new();
3551 if (type == BCOND_CTR)
3552 tcg_gen_mov_tl(target, cpu_ctr);
3553 else
3554 tcg_gen_mov_tl(target, cpu_lr);
3555 }
3556 if (LK(ctx->opcode))
3557 gen_setlr(ctx, ctx->nip);
3558 l1 = gen_new_label();
3559 if ((bo & 0x4) == 0) {
3560 /* Decrement and test CTR */
3561 TCGv temp = tcg_temp_new();
3562 if (unlikely(type == BCOND_CTR)) {
3563 GEN_EXCP_INVAL(ctx);
3564 return;
3565 }
3566 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3567 #if defined(TARGET_PPC64)
3568 if (!ctx->sf_mode)
3569 tcg_gen_ext32u_tl(temp, cpu_ctr);
3570 else
3571 #endif
3572 tcg_gen_mov_tl(temp, cpu_ctr);
3573 if (bo & 0x2) {
3574 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3575 } else {
3576 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3577 }
3578 tcg_temp_free(temp);
3579 }
3580 if ((bo & 0x10) == 0) {
3581 /* Test CR */
3582 uint32_t bi = BI(ctx->opcode);
3583 uint32_t mask = 1 << (3 - (bi & 0x03));
3584 TCGv_i32 temp = tcg_temp_new_i32();
3585
3586 if (bo & 0x8) {
3587 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3588 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3589 } else {
3590 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3591 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3592 }
3593 tcg_temp_free_i32(temp);
3594 }
3595 if (type == BCOND_IM) {
3596 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3597 if (likely(AA(ctx->opcode) == 0)) {
3598 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3599 } else {
3600 gen_goto_tb(ctx, 0, li);
3601 }
3602 gen_set_label(l1);
3603 gen_goto_tb(ctx, 1, ctx->nip);
3604 } else {
3605 #if defined(TARGET_PPC64)
3606 if (!(ctx->sf_mode))
3607 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3608 else
3609 #endif
3610 tcg_gen_andi_tl(cpu_nip, target, ~3);
3611 tcg_gen_exit_tb(0);
3612 gen_set_label(l1);
3613 #if defined(TARGET_PPC64)
3614 if (!(ctx->sf_mode))
3615 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3616 else
3617 #endif
3618 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3619 tcg_gen_exit_tb(0);
3620 }
3621 }
3622
3623 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3624 {
3625 gen_bcond(ctx, BCOND_IM);
3626 }
3627
3628 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3629 {
3630 gen_bcond(ctx, BCOND_CTR);
3631 }
3632
3633 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3634 {
3635 gen_bcond(ctx, BCOND_LR);
3636 }
3637
3638 /*** Condition register logical ***/
3639 #define GEN_CRLOGIC(name, tcg_op, opc) \
3640 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3641 { \
3642 uint8_t bitmask; \
3643 int sh; \
3644 TCGv_i32 t0, t1; \
3645 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3646 t0 = tcg_temp_new_i32(); \
3647 if (sh > 0) \
3648 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3649 else if (sh < 0) \
3650 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3651 else \
3652 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3653 t1 = tcg_temp_new_i32(); \
3654 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3655 if (sh > 0) \
3656 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3657 else if (sh < 0) \
3658 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3659 else \
3660 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3661 tcg_op(t0, t0, t1); \
3662 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3663 tcg_gen_andi_i32(t0, t0, bitmask); \
3664 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3665 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3666 tcg_temp_free_i32(t0); \
3667 tcg_temp_free_i32(t1); \
3668 }
3669
3670 /* crand */
3671 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3672 /* crandc */
3673 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3674 /* creqv */
3675 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3676 /* crnand */
3677 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3678 /* crnor */
3679 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3680 /* cror */
3681 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3682 /* crorc */
3683 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3684 /* crxor */
3685 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3686 /* mcrf */
3687 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3688 {
3689 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3690 }
3691
3692 /*** System linkage ***/
3693 /* rfi (mem_idx only) */
3694 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3695 {
3696 #if defined(CONFIG_USER_ONLY)
3697 GEN_EXCP_PRIVOPC(ctx);
3698 #else
3699 /* Restore CPU state */
3700 if (unlikely(!ctx->mem_idx)) {
3701 GEN_EXCP_PRIVOPC(ctx);
3702 return;
3703 }
3704 gen_helper_rfi();
3705 GEN_SYNC(ctx);
3706 #endif
3707 }
3708
3709 #if defined(TARGET_PPC64)
3710 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3711 {
3712 #if defined(CONFIG_USER_ONLY)
3713 GEN_EXCP_PRIVOPC(ctx);
3714 #else
3715 /* Restore CPU state */
3716 if (unlikely(!ctx->mem_idx)) {
3717 GEN_EXCP_PRIVOPC(ctx);
3718 return;
3719 }
3720 gen_helper_rfid();
3721 GEN_SYNC(ctx);
3722 #endif
3723 }
3724
3725 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3726 {
3727 #if defined(CONFIG_USER_ONLY)
3728 GEN_EXCP_PRIVOPC(ctx);
3729 #else
3730 /* Restore CPU state */
3731 if (unlikely(ctx->mem_idx <= 1)) {
3732 GEN_EXCP_PRIVOPC(ctx);
3733 return;
3734 }
3735 gen_helper_hrfid();
3736 GEN_SYNC(ctx);
3737 #endif
3738 }
3739 #endif
3740
3741 /* sc */
3742 #if defined(CONFIG_USER_ONLY)
3743 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3744 #else
3745 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3746 #endif
3747 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3748 {
3749 uint32_t lev;
3750
3751 lev = (ctx->opcode >> 5) & 0x7F;
3752 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3753 }
3754
3755 /*** Trap ***/
3756 /* tw */
3757 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3758 {
3759 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3760 /* Update the nip since this might generate a trap exception */
3761 gen_update_nip(ctx, ctx->nip);
3762 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3763 tcg_temp_free_i32(t0);
3764 }
3765
3766 /* twi */
3767 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3768 {
3769 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3770 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3771 /* Update the nip since this might generate a trap exception */
3772 gen_update_nip(ctx, ctx->nip);
3773 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3774 tcg_temp_free(t0);
3775 tcg_temp_free_i32(t1);
3776 }
3777
3778 #if defined(TARGET_PPC64)
3779 /* td */
3780 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3781 {
3782 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3783 /* Update the nip since this might generate a trap exception */
3784 gen_update_nip(ctx, ctx->nip);
3785 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3786 tcg_temp_free_i32(t0);
3787 }
3788
3789 /* tdi */
3790 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3791 {
3792 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3793 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3794 /* Update the nip since this might generate a trap exception */
3795 gen_update_nip(ctx, ctx->nip);
3796 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3797 tcg_temp_free(t0);
3798 tcg_temp_free_i32(t1);
3799 }
3800 #endif
3801
3802 /*** Processor control ***/
3803 /* mcrxr */
3804 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3805 {
3806 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3807 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3808 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3809 }
3810
3811 /* mfcr */
3812 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3813 {
3814 uint32_t crm, crn;
3815
3816 if (likely(ctx->opcode & 0x00100000)) {
3817 crm = CRM(ctx->opcode);
3818 if (likely((crm ^ (crm - 1)) == 0)) {
3819 crn = ffs(crm);
3820 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3821 }
3822 } else {
3823 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3824 }
3825 }
3826
3827 /* mfmsr */
3828 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3829 {
3830 #if defined(CONFIG_USER_ONLY)
3831 GEN_EXCP_PRIVREG(ctx);
3832 #else
3833 if (unlikely(!ctx->mem_idx)) {
3834 GEN_EXCP_PRIVREG(ctx);
3835 return;
3836 }
3837 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3838 #endif
3839 }
3840
3841 #if 1
3842 #define SPR_NOACCESS ((void *)(-1UL))
3843 #else
3844 static void spr_noaccess (void *opaque, int sprn)
3845 {
3846 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3847 printf("ERROR: try to access SPR %d !\n", sprn);
3848 }
3849 #define SPR_NOACCESS (&spr_noaccess)
3850 #endif
3851
3852 /* mfspr */
3853 static always_inline void gen_op_mfspr (DisasContext *ctx)
3854 {
3855 void (*read_cb)(void *opaque, int gprn, int sprn);
3856 uint32_t sprn = SPR(ctx->opcode);
3857
3858 #if !defined(CONFIG_USER_ONLY)
3859 if (ctx->mem_idx == 2)
3860 read_cb = ctx->spr_cb[sprn].hea_read;
3861 else if (ctx->mem_idx)
3862 read_cb = ctx->spr_cb[sprn].oea_read;
3863 else
3864 #endif
3865 read_cb = ctx->spr_cb[sprn].uea_read;
3866 if (likely(read_cb != NULL)) {
3867 if (likely(read_cb != SPR_NOACCESS)) {
3868 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3869 } else {
3870 /* Privilege exception */
3871 /* This is a hack to avoid warnings when running Linux:
3872 * this OS breaks the PowerPC virtualisation model,
3873 * allowing userland application to read the PVR
3874 */
3875 if (sprn != SPR_PVR) {
3876 if (loglevel != 0) {
3877 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3878 ADDRX "\n", sprn, sprn, ctx->nip);
3879 }
3880 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3881 sprn, sprn, ctx->nip);
3882 }
3883 GEN_EXCP_PRIVREG(ctx);
3884 }
3885 } else {
3886 /* Not defined */
3887 if (loglevel != 0) {
3888 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3889 ADDRX "\n", sprn, sprn, ctx->nip);
3890 }
3891 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3892 sprn, sprn, ctx->nip);
3893 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3894 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3895 }
3896 }
3897
3898 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3899 {
3900 gen_op_mfspr(ctx);
3901 }
3902
3903 /* mftb */
3904 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3905 {
3906 gen_op_mfspr(ctx);
3907 }
3908
3909 /* mtcrf */
3910 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3911 {
3912 uint32_t crm, crn;
3913
3914 crm = CRM(ctx->opcode);
3915 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3916 TCGv_i32 temp = tcg_temp_new_i32();
3917 crn = ffs(crm);
3918 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3919 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3920 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3921 tcg_temp_free_i32(temp);
3922 } else {
3923 TCGv_i32 temp = tcg_const_i32(crm);
3924 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3925 tcg_temp_free_i32(temp);
3926 }
3927 }
3928
3929 /* mtmsr */
3930 #if defined(TARGET_PPC64)
3931 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3932 {
3933 #if defined(CONFIG_USER_ONLY)
3934 GEN_EXCP_PRIVREG(ctx);
3935 #else
3936 if (unlikely(!ctx->mem_idx)) {
3937 GEN_EXCP_PRIVREG(ctx);
3938 return;
3939 }
3940 if (ctx->opcode & 0x00010000) {
3941 /* Special form that does not need any synchronisation */
3942 TCGv t0 = tcg_temp_new();
3943 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3944 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3945 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3946 tcg_temp_free(t0);
3947 } else {
3948 /* XXX: we need to update nip before the store
3949 * if we enter power saving mode, we will exit the loop
3950 * directly from ppc_store_msr
3951 */
3952 gen_update_nip(ctx, ctx->nip);
3953 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3954 /* Must stop the translation as machine state (may have) changed */
3955 /* Note that mtmsr is not always defined as context-synchronizing */
3956 ctx->exception = POWERPC_EXCP_STOP;
3957 }
3958 #endif
3959 }
3960 #endif
3961
3962 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3963 {
3964 #if defined(CONFIG_USER_ONLY)
3965 GEN_EXCP_PRIVREG(ctx);
3966 #else
3967 if (unlikely(!ctx->mem_idx)) {
3968 GEN_EXCP_PRIVREG(ctx);
3969 return;
3970 }
3971 if (ctx->opcode & 0x00010000) {
3972 /* Special form that does not need any synchronisation */
3973 TCGv t0 = tcg_temp_new();
3974 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3975 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3976 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3977 tcg_temp_free(t0);
3978 } else {
3979 /* XXX: we need to update nip before the store
3980 * if we enter power saving mode, we will exit the loop
3981 * directly from ppc_store_msr
3982 */
3983 gen_update_nip(ctx, ctx->nip);
3984 #if defined(TARGET_PPC64)
3985 if (!ctx->sf_mode) {
3986 TCGv t0 = tcg_temp_new();
3987 TCGv t1 = tcg_temp_new();
3988 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3989 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3990 tcg_gen_or_tl(t0, t0, t1);
3991 tcg_temp_free(t1);
3992 gen_helper_store_msr(t0);
3993 tcg_temp_free(t0);
3994 } else
3995 #endif
3996 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3997 /* Must stop the translation as machine state (may have) changed */
3998 /* Note that mtmsr is not always defined as context-synchronizing */
3999 ctx->exception = POWERPC_EXCP_STOP;
4000 }
4001 #endif
4002 }
4003
4004 /* mtspr */
4005 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4006 {
4007 void (*write_cb)(void *opaque, int sprn, int gprn);
4008 uint32_t sprn = SPR(ctx->opcode);
4009
4010 #if !defined(CONFIG_USER_ONLY)
4011 if (ctx->mem_idx == 2)
4012 write_cb = ctx->spr_cb[sprn].hea_write;
4013 else if (ctx->mem_idx)
4014 write_cb = ctx->spr_cb[sprn].oea_write;
4015 else
4016 #endif
4017 write_cb = ctx->spr_cb[sprn].uea_write;
4018 if (likely(write_cb != NULL)) {
4019 if (likely(write_cb != SPR_NOACCESS)) {
4020 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4021 } else {
4022 /* Privilege exception */
4023 if (loglevel != 0) {
4024 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4025 ADDRX "\n", sprn, sprn, ctx->nip);
4026 }
4027 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4028 sprn, sprn, ctx->nip);
4029 GEN_EXCP_PRIVREG(ctx);
4030 }
4031 } else {
4032 /* Not defined */
4033 if (loglevel != 0) {
4034 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4035 ADDRX "\n", sprn, sprn, ctx->nip);
4036 }
4037 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4038 sprn, sprn, ctx->nip);
4039 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4040 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
4041 }
4042 }
4043
4044 /*** Cache management ***/
4045 /* dcbf */
4046 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4047 {
4048 /* XXX: specification says this is treated as a load by the MMU */
4049 TCGv t0;
4050 gen_set_access_type(ctx, ACCESS_CACHE);
4051 t0 = tcg_temp_new();
4052 gen_addr_reg_index(ctx, t0);
4053 gen_qemu_ld8u(ctx, t0, t0);
4054 tcg_temp_free(t0);
4055 }
4056
4057 /* dcbi (Supervisor only) */
4058 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4059 {
4060 #if defined(CONFIG_USER_ONLY)
4061 GEN_EXCP_PRIVOPC(ctx);
4062 #else
4063 TCGv EA, val;
4064 if (unlikely(!ctx->mem_idx)) {
4065 GEN_EXCP_PRIVOPC(ctx);
4066 return;
4067 }
4068 EA = tcg_temp_new();
4069 gen_set_access_type(ctx, ACCESS_CACHE);
4070 gen_addr_reg_index(ctx, EA);
4071 val = tcg_temp_new();
4072 /* XXX: specification says this should be treated as a store by the MMU */
4073 gen_qemu_ld8u(ctx, val, EA);
4074 gen_qemu_st8(ctx, val, EA);
4075 tcg_temp_free(val);
4076 tcg_temp_free(EA);
4077 #endif
4078 }
4079
4080 /* dcdst */
4081 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4082 {
4083 /* XXX: specification say this is treated as a load by the MMU */
4084 TCGv t0;
4085 gen_set_access_type(ctx, ACCESS_CACHE);
4086 t0 = tcg_temp_new();
4087 gen_addr_reg_index(ctx, t0);
4088 gen_qemu_ld8u(ctx, t0, t0);
4089 tcg_temp_free(t0);
4090 }
4091
4092 /* dcbt */
4093 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4094 {
4095 /* interpreted as no-op */
4096 /* XXX: specification say this is treated as a load by the MMU
4097 * but does not generate any exception
4098 */
4099 }
4100
4101 /* dcbtst */
4102 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4103 {
4104 /* interpreted as no-op */
4105 /* XXX: specification say this is treated as a load by the MMU
4106 * but does not generate any exception
4107 */
4108 }
4109
4110 /* dcbz */
4111 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4112 {
4113 TCGv t0;
4114 gen_set_access_type(ctx, ACCESS_CACHE);
4115 /* NIP cannot be restored if the memory exception comes from an helper */
4116 gen_update_nip(ctx, ctx->nip - 4);
4117 t0 = tcg_temp_new();
4118 gen_addr_reg_index(ctx, t0);
4119 gen_helper_dcbz(t0);
4120 tcg_temp_free(t0);
4121 }
4122
4123 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4124 {
4125 TCGv t0;
4126 gen_set_access_type(ctx, ACCESS_CACHE);
4127 /* NIP cannot be restored if the memory exception comes from an helper */
4128 gen_update_nip(ctx, ctx->nip - 4);
4129 t0 = tcg_temp_new();
4130 gen_addr_reg_index(ctx, t0);
4131 if (ctx->opcode & 0x00200000)
4132 gen_helper_dcbz(t0);
4133 else
4134 gen_helper_dcbz_970(t0);
4135 tcg_temp_free(t0);
4136 }
4137
4138 /* icbi */
4139 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4140 {
4141 TCGv t0;
4142 gen_set_access_type(ctx, ACCESS_CACHE);
4143 /* NIP cannot be restored if the memory exception comes from an helper */
4144 gen_update_nip(ctx, ctx->nip - 4);
4145 t0 = tcg_temp_new();
4146 gen_addr_reg_index(ctx, t0);
4147 gen_helper_icbi(t0);
4148 tcg_temp_free(t0);
4149 }
4150
4151 /* Optional: */
4152 /* dcba */
4153 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4154 {
4155 /* interpreted as no-op */
4156 /* XXX: specification say this is treated as a store by the MMU
4157 * but does not generate any exception
4158 */
4159 }
4160
4161 /*** Segment register manipulation ***/
4162 /* Supervisor only: */
4163 /* mfsr */
4164 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4165 {
4166 #if defined(CONFIG_USER_ONLY)
4167 GEN_EXCP_PRIVREG(ctx);
4168 #else
4169 TCGv t0;
4170 if (unlikely(!ctx->mem_idx)) {
4171 GEN_EXCP_PRIVREG(ctx);
4172 return;
4173 }
4174 t0 = tcg_const_tl(SR(ctx->opcode));
4175 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4176 tcg_temp_free(t0);
4177 #endif
4178 }
4179
4180 /* mfsrin */
4181 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4182 {
4183 #if defined(CONFIG_USER_ONLY)
4184 GEN_EXCP_PRIVREG(ctx);
4185 #else
4186 TCGv t0;
4187 if (unlikely(!ctx->mem_idx)) {
4188 GEN_EXCP_PRIVREG(ctx);
4189 return;
4190 }
4191 t0 = tcg_temp_new();
4192 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4193 tcg_gen_andi_tl(t0, t0, 0xF);
4194 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4195 tcg_temp_free(t0);
4196 #endif
4197 }
4198
4199 /* mtsr */
4200 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4201 {
4202 #if defined(CONFIG_USER_ONLY)
4203 GEN_EXCP_PRIVREG(ctx);
4204 #else
4205 TCGv t0;
4206 if (unlikely(!ctx->mem_idx)) {
4207 GEN_EXCP_PRIVREG(ctx);
4208 return;
4209 }
4210 t0 = tcg_const_tl(SR(ctx->opcode));
4211 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4212 tcg_temp_free(t0);
4213 #endif
4214 }
4215
4216 /* mtsrin */
4217 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4218 {
4219 #if defined(CONFIG_USER_ONLY)
4220 GEN_EXCP_PRIVREG(ctx);
4221 #else
4222 TCGv t0;
4223 if (unlikely(!ctx->mem_idx)) {
4224 GEN_EXCP_PRIVREG(ctx);
4225 return;
4226 }
4227 t0 = tcg_temp_new();
4228 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4229 tcg_gen_andi_tl(t0, t0, 0xF);
4230 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4231 tcg_temp_free(t0);
4232 #endif
4233 }
4234
4235 #if defined(TARGET_PPC64)
4236 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4237 /* mfsr */
4238 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4239 {
4240 #if defined(CONFIG_USER_ONLY)
4241 GEN_EXCP_PRIVREG(ctx);
4242 #else
4243 TCGv t0;
4244 if (unlikely(!ctx->mem_idx)) {
4245 GEN_EXCP_PRIVREG(ctx);
4246 return;
4247 }
4248 t0 = tcg_const_tl(SR(ctx->opcode));
4249 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4250 tcg_temp_free(t0);
4251 #endif
4252 }
4253
4254 /* mfsrin */
4255 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4256 PPC_SEGMENT_64B)
4257 {
4258 #if defined(CONFIG_USER_ONLY)
4259 GEN_EXCP_PRIVREG(ctx);
4260 #else
4261 TCGv t0;
4262 if (unlikely(!ctx->mem_idx)) {
4263 GEN_EXCP_PRIVREG(ctx);
4264 return;
4265 }
4266 t0 = tcg_temp_new();
4267 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4268 tcg_gen_andi_tl(t0, t0, 0xF);
4269 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4270 tcg_temp_free(t0);
4271 #endif
4272 }
4273
4274 /* mtsr */
4275 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4276 {
4277 #if defined(CONFIG_USER_ONLY)
4278 GEN_EXCP_PRIVREG(ctx);
4279 #else
4280 TCGv t0;
4281 if (unlikely(!ctx->mem_idx)) {
4282 GEN_EXCP_PRIVREG(ctx);
4283 return;
4284 }
4285 t0 = tcg_const_tl(SR(ctx->opcode));
4286 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4287 tcg_temp_free(t0);
4288 #endif
4289 }
4290
4291 /* mtsrin */
4292 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4293 PPC_SEGMENT_64B)
4294 {
4295 #if defined(CONFIG_USER_ONLY)
4296 GEN_EXCP_PRIVREG(ctx);
4297 #else
4298 TCGv t0;
4299 if (unlikely(!ctx->mem_idx)) {
4300 GEN_EXCP_PRIVREG(ctx);
4301 return;
4302 }
4303 t0 = tcg_temp_new();
4304 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4305 tcg_gen_andi_tl(t0, t0, 0xF);
4306 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4307 tcg_temp_free(t0);
4308 #endif
4309 }
4310 #endif /* defined(TARGET_PPC64) */
4311
4312 /*** Lookaside buffer management ***/
4313 /* Optional & mem_idx only: */
4314 /* tlbia */
4315 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4316 {
4317 #if defined(CONFIG_USER_ONLY)
4318 GEN_EXCP_PRIVOPC(ctx);
4319 #else
4320 if (unlikely(!ctx->mem_idx)) {
4321 GEN_EXCP_PRIVOPC(ctx);
4322 return;
4323 }
4324 gen_helper_tlbia();
4325 #endif
4326 }
4327
4328 /* tlbie */
4329 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4330 {
4331 #if defined(CONFIG_USER_ONLY)
4332 GEN_EXCP_PRIVOPC(ctx);
4333 #else
4334 if (unlikely(!ctx->mem_idx)) {
4335 GEN_EXCP_PRIVOPC(ctx);
4336 return;
4337 }
4338 #if defined(TARGET_PPC64)
4339 if (!ctx->sf_mode) {
4340 TCGv t0 = tcg_temp_new();
4341 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4342 gen_helper_tlbie(t0);
4343 tcg_temp_free(t0);
4344 } else
4345 #endif
4346 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4347 #endif
4348 }
4349
4350 /* tlbsync */
4351 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4352 {
4353 #if defined(CONFIG_USER_ONLY)
4354 GEN_EXCP_PRIVOPC(ctx);
4355 #else
4356 if (unlikely(!ctx->mem_idx)) {
4357 GEN_EXCP_PRIVOPC(ctx);
4358 return;
4359 }
4360 /* This has no effect: it should ensure that all previous
4361 * tlbie have completed
4362 */
4363 GEN_STOP(ctx);
4364 #endif
4365 }
4366
4367 #if defined(TARGET_PPC64)
4368 /* slbia */
4369 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4370 {
4371 #if defined(CONFIG_USER_ONLY)
4372 GEN_EXCP_PRIVOPC(ctx);
4373 #else
4374 if (unlikely(!ctx->mem_idx)) {
4375 GEN_EXCP_PRIVOPC(ctx);
4376 return;
4377 }
4378 gen_helper_slbia();
4379 #endif
4380 }
4381
4382 /* slbie */
4383 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4384 {
4385 #if defined(CONFIG_USER_ONLY)
4386 GEN_EXCP_PRIVOPC(ctx);
4387 #else
4388 if (unlikely(!ctx->mem_idx)) {
4389 GEN_EXCP_PRIVOPC(ctx);
4390 return;
4391 }
4392 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4393 #endif
4394 }
4395 #endif
4396
4397 /*** External control ***/
4398 /* Optional: */
4399 /* eciwx */
4400 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4401 {
4402 TCGv t0;
4403 /* Should check EAR[E] ! */
4404 gen_set_access_type(ctx, ACCESS_EXT);
4405 t0 = tcg_temp_new();
4406 gen_addr_reg_index(ctx, t0);
4407 gen_check_align(ctx, t0, 0x03);
4408 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4409 tcg_temp_free(t0);
4410 }
4411
4412 /* ecowx */
4413 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4414 {
4415 TCGv t0;
4416 /* Should check EAR[E] ! */
4417 gen_set_access_type(ctx, ACCESS_EXT);
4418 t0 = tcg_temp_new();
4419 gen_addr_reg_index(ctx, t0);
4420 gen_check_align(ctx, t0, 0x03);
4421 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4422 tcg_temp_free(t0);
4423 }
4424
4425 /* PowerPC 601 specific instructions */
4426 /* abs - abs. */
4427 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4428 {
4429 int l1 = gen_new_label();
4430 int l2 = gen_new_label();
4431 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4432 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4433 tcg_gen_br(l2);
4434 gen_set_label(l1);
4435 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4436 gen_set_label(l2);
4437 if (unlikely(Rc(ctx->opcode) != 0))
4438 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4439 }
4440
4441 /* abso - abso. */
4442 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4443 {
4444 int l1 = gen_new_label();
4445 int l2 = gen_new_label();
4446 int l3 = gen_new_label();
4447 /* Start with XER OV disabled, the most likely case */
4448 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4449 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4450 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4451 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4452 tcg_gen_br(l2);
4453 gen_set_label(l1);
4454 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4455 tcg_gen_br(l3);
4456 gen_set_label(l2);
4457 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4458 gen_set_label(l3);
4459 if (unlikely(Rc(ctx->opcode) != 0))
4460 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4461 }
4462
4463 /* clcs */
4464 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4465 {
4466 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4467 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4468 tcg_temp_free_i32(t0);
4469 /* Rc=1 sets CR0 to an undefined state */
4470 }
4471
4472 /* div - div. */
4473 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4474 {
4475 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4476 if (unlikely(Rc(ctx->opcode) != 0))
4477 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4478 }
4479
4480 /* divo - divo. */
4481 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4482 {
4483 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4484 if (unlikely(Rc(ctx->opcode) != 0))
4485 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4486 }
4487
4488 /* divs - divs. */
4489 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4490 {
4491 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4492 if (unlikely(Rc(ctx->opcode) != 0))
4493 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4494 }
4495
4496 /* divso - divso. */
4497 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4498 {
4499 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4500 if (unlikely(Rc(ctx->opcode) != 0))
4501 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4502 }
4503
4504 /* doz - doz. */
4505 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4506 {
4507 int l1 = gen_new_label();
4508 int l2 = gen_new_label();
4509 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4510 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4511 tcg_gen_br(l2);
4512 gen_set_label(l1);
4513 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4514 gen_set_label(l2);
4515 if (unlikely(Rc(ctx->opcode) != 0))
4516 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4517 }
4518
4519 /* dozo - dozo. */
4520 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4521 {
4522 int l1 = gen_new_label();
4523 int l2 = gen_new_label();
4524 TCGv t0 = tcg_temp_new();
4525 TCGv t1 = tcg_temp_new();
4526 TCGv t2 = tcg_temp_new();
4527 /* Start with XER OV disabled, the most likely case */
4528 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4529 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4530 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4531 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4532 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4533 tcg_gen_andc_tl(t1, t1, t2);
4534 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4535 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4536 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4537 tcg_gen_br(l2);
4538 gen_set_label(l1);
4539 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4540 gen_set_label(l2);
4541 tcg_temp_free(t0);
4542 tcg_temp_free(t1);
4543 tcg_temp_free(t2);
4544 if (unlikely(Rc(ctx->opcode) != 0))
4545 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4546 }
4547
4548 /* dozi */
4549 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4550 {
4551 target_long simm = SIMM(ctx->opcode);
4552 int l1 = gen_new_label();
4553 int l2 = gen_new_label();
4554 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4555 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4556 tcg_gen_br(l2);
4557 gen_set_label(l1);
4558 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4559 gen_set_label(l2);
4560 if (unlikely(Rc(ctx->opcode) != 0))
4561 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4562 }
4563
4564 /* lscbx - lscbx. */
4565 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4566 {
4567 TCGv t0 = tcg_temp_new();
4568 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4569 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4570 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4571
4572 gen_addr_reg_index(ctx, t0);
4573 /* NIP cannot be restored if the memory exception comes from an helper */
4574 gen_update_nip(ctx, ctx->nip - 4);
4575 gen_helper_lscbx(t0, t0, t1, t2, t3);
4576 tcg_temp_free_i32(t1);
4577 tcg_temp_free_i32(t2);
4578 tcg_temp_free_i32(t3);
4579 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4580 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4581 if (unlikely(Rc(ctx->opcode) != 0))
4582 gen_set_Rc0(ctx, t0);
4583 tcg_temp_free(t0);
4584 }
4585
4586 /* maskg - maskg. */
4587 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4588 {
4589 int l1 = gen_new_label();
4590 TCGv t0 = tcg_temp_new();
4591 TCGv t1 = tcg_temp_new();
4592 TCGv t2 = tcg_temp_new();
4593 TCGv t3 = tcg_temp_new();
4594 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4595 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4596 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4597 tcg_gen_addi_tl(t2, t0, 1);
4598 tcg_gen_shr_tl(t2, t3, t2);
4599 tcg_gen_shr_tl(t3, t3, t1);
4600 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4601 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4602 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4603 gen_set_label(l1);
4604 tcg_temp_free(t0);
4605 tcg_temp_free(t1);
4606 tcg_temp_free(t2);
4607 tcg_temp_free(t3);
4608 if (unlikely(Rc(ctx->opcode) != 0))
4609 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4610 }
4611
4612 /* maskir - maskir. */
4613 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4614 {
4615 TCGv t0 = tcg_temp_new();
4616 TCGv t1 = tcg_temp_new();
4617 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4618 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4619 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4620 tcg_temp_free(t0);
4621 tcg_temp_free(t1);
4622 if (unlikely(Rc(ctx->opcode) != 0))
4623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4624 }
4625
4626 /* mul - mul. */
4627 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4628 {
4629 TCGv_i64 t0 = tcg_temp_new_i64();
4630 TCGv_i64 t1 = tcg_temp_new_i64();
4631 TCGv t2 = tcg_temp_new();
4632 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4633 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4634 tcg_gen_mul_i64(t0, t0, t1);
4635 tcg_gen_trunc_i64_tl(t2, t0);
4636 gen_store_spr(SPR_MQ, t2);
4637 tcg_gen_shri_i64(t1, t0, 32);
4638 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4639 tcg_temp_free_i64(t0);
4640 tcg_temp_free_i64(t1);
4641 tcg_temp_free(t2);
4642 if (unlikely(Rc(ctx->opcode) != 0))
4643 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4644 }
4645
4646 /* mulo - mulo. */
4647 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4648 {
4649 int l1 = gen_new_label();
4650 TCGv_i64 t0 = tcg_temp_new_i64();
4651 TCGv_i64 t1 = tcg_temp_new_i64();
4652 TCGv t2 = tcg_temp_new();
4653 /* Start with XER OV disabled, the most likely case */
4654 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4655 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4656 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4657 tcg_gen_mul_i64(t0, t0, t1);
4658 tcg_gen_trunc_i64_tl(t2, t0);
4659 gen_store_spr(SPR_MQ, t2);
4660 tcg_gen_shri_i64(t1, t0, 32);
4661 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4662 tcg_gen_ext32s_i64(t1, t0);
4663 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4664 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4665 gen_set_label(l1);
4666 tcg_temp_free_i64(t0);
4667 tcg_temp_free_i64(t1);
4668 tcg_temp_free(t2);
4669 if (unlikely(Rc(ctx->opcode) != 0))
4670 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4671 }
4672
4673 /* nabs - nabs. */
4674 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4675 {
4676 int l1 = gen_new_label();
4677 int l2 = gen_new_label();
4678 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4679 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4680 tcg_gen_br(l2);
4681 gen_set_label(l1);
4682 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4683 gen_set_label(l2);
4684 if (unlikely(Rc(ctx->opcode) != 0))
4685 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4686 }
4687
4688 /* nabso - nabso. */
4689 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4690 {
4691 int l1 = gen_new_label();
4692 int l2 = gen_new_label();
4693 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4694 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4695 tcg_gen_br(l2);
4696 gen_set_label(l1);
4697 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4698 gen_set_label(l2);
4699 /* nabs never overflows */
4700 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4701 if (unlikely(Rc(ctx->opcode) != 0))
4702 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4703 }
4704
4705 /* rlmi - rlmi. */
4706 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4707 {
4708 uint32_t mb = MB(ctx->opcode);
4709 uint32_t me = ME(ctx->opcode);
4710 TCGv t0 = tcg_temp_new();
4711 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4712 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4713 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4714 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4715 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4716 tcg_temp_free(t0);
4717 if (unlikely(Rc(ctx->opcode) != 0))
4718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4719 }
4720
4721 /* rrib - rrib. */
4722 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4723 {
4724 TCGv t0 = tcg_temp_new();
4725 TCGv t1 = tcg_temp_new();
4726 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4727 tcg_gen_movi_tl(t1, 0x80000000);
4728 tcg_gen_shr_tl(t1, t1, t0);
4729 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4730 tcg_gen_and_tl(t0, t0, t1);
4731 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4732 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4733 tcg_temp_free(t0);
4734 tcg_temp_free(t1);
4735 if (unlikely(Rc(ctx->opcode) != 0))
4736 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4737 }
4738
4739 /* sle - sle. */
4740 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4741 {
4742 TCGv t0 = tcg_temp_new();
4743 TCGv t1 = tcg_temp_new();
4744 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4745 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4746 tcg_gen_subfi_tl(t1, 32, t1);
4747 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4748 tcg_gen_or_tl(t1, t0, t1);
4749 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4750 gen_store_spr(SPR_MQ, t1);
4751 tcg_temp_free(t0);
4752 tcg_temp_free(t1);
4753 if (unlikely(Rc(ctx->opcode) != 0))
4754 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4755 }
4756
4757 /* sleq - sleq. */
4758 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4759 {
4760 TCGv t0 = tcg_temp_new();
4761 TCGv t1 = tcg_temp_new();
4762 TCGv t2 = tcg_temp_new();
4763 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4764 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4765 tcg_gen_shl_tl(t2, t2, t0);
4766 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4767 gen_load_spr(t1, SPR_MQ);
4768 gen_store_spr(SPR_MQ, t0);
4769 tcg_gen_and_tl(t0, t0, t2);
4770 tcg_gen_andc_tl(t1, t1, t2);
4771 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4772 tcg_temp_free(t0);
4773 tcg_temp_free(t1);
4774 tcg_temp_free(t2);
4775 if (unlikely(Rc(ctx->opcode) != 0))
4776 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4777 }
4778
4779 /* sliq - sliq. */
4780 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4781 {
4782 int sh = SH(ctx->opcode);
4783 TCGv t0 = tcg_temp_new();
4784 TCGv t1 = tcg_temp_new();
4785 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4786 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4787 tcg_gen_or_tl(t1, t0, t1);
4788 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4789 gen_store_spr(SPR_MQ, t1);
4790 tcg_temp_free(t0);
4791 tcg_temp_free(t1);
4792 if (unlikely(Rc(ctx->opcode) != 0))
4793 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4794 }
4795
4796 /* slliq - slliq. */
4797 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4798 {
4799 int sh = SH(ctx->opcode);
4800 TCGv t0 = tcg_temp_new();
4801 TCGv t1 = tcg_temp_new();
4802 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4803 gen_load_spr(t1, SPR_MQ);
4804 gen_store_spr(SPR_MQ, t0);
4805 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4806 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4807 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4808 tcg_temp_free(t0);
4809 tcg_temp_free(t1);
4810 if (unlikely(Rc(ctx->opcode) != 0))
4811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4812 }
4813
4814 /* sllq - sllq. */
4815 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4816 {
4817 int l1 = gen_new_label();
4818 int l2 = gen_new_label();
4819 TCGv t0 = tcg_temp_local_new();
4820 TCGv t1 = tcg_temp_local_new();
4821 TCGv t2 = tcg_temp_local_new();
4822 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4823 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4824 tcg_gen_shl_tl(t1, t1, t2);
4825 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4826 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4827 gen_load_spr(t0, SPR_MQ);
4828 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4829 tcg_gen_br(l2);
4830 gen_set_label(l1);
4831 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4832 gen_load_spr(t2, SPR_MQ);
4833 tcg_gen_andc_tl(t1, t2, t1);
4834 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4835 gen_set_label(l2);
4836 tcg_temp_free(t0);
4837 tcg_temp_free(t1);
4838 tcg_temp_free(t2);
4839 if (unlikely(Rc(ctx->opcode) != 0))
4840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4841 }
4842
4843 /* slq - slq. */
4844 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4845 {
4846 int l1 = gen_new_label();
4847 TCGv t0 = tcg_temp_new();
4848 TCGv t1 = tcg_temp_new();
4849 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4850 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4851 tcg_gen_subfi_tl(t1, 32, t1);
4852 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4853 tcg_gen_or_tl(t1, t0, t1);
4854 gen_store_spr(SPR_MQ, t1);
4855 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4856 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4857 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4858 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4859 gen_set_label(l1);
4860 tcg_temp_free(t0);
4861 tcg_temp_free(t1);
4862 if (unlikely(Rc(ctx->opcode) != 0))
4863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4864 }
4865
4866 /* sraiq - sraiq. */
4867 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4868 {
4869 int sh = SH(ctx->opcode);
4870 int l1 = gen_new_label();
4871 TCGv t0 = tcg_temp_new();
4872 TCGv t1 = tcg_temp_new();
4873 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4874 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4875 tcg_gen_or_tl(t0, t0, t1);
4876 gen_store_spr(SPR_MQ, t0);
4877 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4878 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4879 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4880 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4881 gen_set_label(l1);
4882 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4883 tcg_temp_free(t0);
4884 tcg_temp_free(t1);
4885 if (unlikely(Rc(ctx->opcode) != 0))
4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4887 }
4888
4889 /* sraq - sraq. */
4890 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4891 {
4892 int l1 = gen_new_label();
4893 int l2 = gen_new_label();
4894 TCGv t0 = tcg_temp_new();
4895 TCGv t1 = tcg_temp_local_new();
4896 TCGv t2 = tcg_temp_local_new();
4897 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4898 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4899 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4900 tcg_gen_subfi_tl(t2, 32, t2);
4901 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4902 tcg_gen_or_tl(t0, t0, t2);
4903 gen_store_spr(SPR_MQ, t0);
4904 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4905 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4906 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4907 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4908 gen_set_label(l1);
4909 tcg_temp_free(t0);
4910 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4911 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4912 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4913 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4914 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4915 gen_set_label(l2);
4916 tcg_temp_free(t1);
4917 tcg_temp_free(t2);
4918 if (unlikely(Rc(ctx->opcode) != 0))
4919 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4920 }
4921
4922 /* sre - sre. */
4923 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4924 {
4925 TCGv t0 = tcg_temp_new();
4926 TCGv t1 = tcg_temp_new();
4927 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4928 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4929 tcg_gen_subfi_tl(t1, 32, t1);
4930 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4931 tcg_gen_or_tl(t1, t0, t1);
4932 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4933 gen_store_spr(SPR_MQ, t1);
4934 tcg_temp_free(t0);
4935 tcg_temp_free(t1);
4936 if (unlikely(Rc(ctx->opcode) != 0))
4937 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4938 }
4939
4940 /* srea - srea. */
4941 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4942 {
4943 TCGv t0 = tcg_temp_new();
4944 TCGv t1 = tcg_temp_new();
4945 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4946 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4947 gen_store_spr(SPR_MQ, t0);
4948 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4949 tcg_temp_free(t0);
4950 tcg_temp_free(t1);
4951 if (unlikely(Rc(ctx->opcode) != 0))
4952 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4953 }
4954
4955 /* sreq */
4956 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4957 {
4958 TCGv t0 = tcg_temp_new();
4959 TCGv t1 = tcg_temp_new();
4960 TCGv t2 = tcg_temp_new();
4961 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4962 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4963 tcg_gen_shr_tl(t1, t1, t0);
4964 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4965 gen_load_spr(t2, SPR_MQ);
4966 gen_store_spr(SPR_MQ, t0);
4967 tcg_gen_and_tl(t0, t0, t1);
4968 tcg_gen_andc_tl(t2, t2, t1);
4969 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4970 tcg_temp_free(t0);
4971 tcg_temp_free(t1);
4972 tcg_temp_free(t2);
4973 if (unlikely(Rc(ctx->opcode) != 0))
4974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4975 }
4976
4977 /* sriq */
4978 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4979 {
4980 int sh = SH(ctx->opcode);
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_new();
4983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4984 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4985 tcg_gen_or_tl(t1, t0, t1);
4986 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4987 gen_store_spr(SPR_MQ, t1);
4988 tcg_temp_free(t0);
4989 tcg_temp_free(t1);
4990 if (unlikely(Rc(ctx->opcode) != 0))
4991 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4992 }
4993
4994 /* srliq */
4995 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4996 {
4997 int sh = SH(ctx->opcode);
4998 TCGv t0 = tcg_temp_new();
4999 TCGv t1 = tcg_temp_new();
5000 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5001 gen_load_spr(t1, SPR_MQ);
5002 gen_store_spr(SPR_MQ, t0);
5003 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5004 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5005 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5006 tcg_temp_free(t0);
5007 tcg_temp_free(t1);
5008 if (unlikely(Rc(ctx->opcode) != 0))
5009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5010 }
5011
5012 /* srlq */
5013 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5014 {
5015 int l1 = gen_new_label();
5016 int l2 = gen_new_label();
5017 TCGv t0 = tcg_temp_local_new();
5018 TCGv t1 = tcg_temp_local_new();
5019 TCGv t2 = tcg_temp_local_new();
5020 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5021 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5022 tcg_gen_shr_tl(t2, t1, t2);
5023 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5024 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5025 gen_load_spr(t0, SPR_MQ);
5026 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5027 tcg_gen_br(l2);
5028 gen_set_label(l1);
5029 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5030 tcg_gen_and_tl(t0, t0, t2);
5031 gen_load_spr(t1, SPR_MQ);
5032 tcg_gen_andc_tl(t1, t1, t2);
5033 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5034 gen_set_label(l2);
5035 tcg_temp_free(t0);
5036 tcg_temp_free(t1);
5037 tcg_temp_free(t2);
5038 if (unlikely(Rc(ctx->opcode) != 0))
5039 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5040 }
5041
5042 /* srq */
5043 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5044 {
5045 int l1 = gen_new_label();
5046 TCGv t0 = tcg_temp_new();
5047 TCGv t1 = tcg_temp_new();
5048 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5049 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5050 tcg_gen_subfi_tl(t1, 32, t1);
5051 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5052 tcg_gen_or_tl(t1, t0, t1);
5053 gen_store_spr(SPR_MQ, t1);
5054 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5055 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5056 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5057 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5058 gen_set_label(l1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
5061 if (unlikely(Rc(ctx->opcode) != 0))
5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5063 }
5064
5065 /* PowerPC 602 specific instructions */
5066 /* dsa */
5067 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5068 {
5069 /* XXX: TODO */
5070 GEN_EXCP_INVAL(ctx);
5071 }
5072
5073 /* esa */
5074 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5075 {
5076 /* XXX: TODO */
5077 GEN_EXCP_INVAL(ctx);
5078 }
5079
5080 /* mfrom */
5081 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5082 {
5083 #if defined(CONFIG_USER_ONLY)
5084 GEN_EXCP_PRIVOPC(ctx);
5085 #else
5086 if (unlikely(!ctx->mem_idx)) {
5087 GEN_EXCP_PRIVOPC(ctx);
5088 return;
5089 }
5090 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5091 #endif
5092 }
5093
5094 /* 602 - 603 - G2 TLB management */
5095 /* tlbld */
5096 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5097 {
5098 #if defined(CONFIG_USER_ONLY)
5099 GEN_EXCP_PRIVOPC(ctx);
5100 #else
5101 if (unlikely(!ctx->mem_idx)) {
5102 GEN_EXCP_PRIVOPC(ctx);
5103 return;
5104 }
5105 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5106 #endif
5107 }
5108
5109 /* tlbli */
5110 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5111 {
5112 #if defined(CONFIG_USER_ONLY)
5113 GEN_EXCP_PRIVOPC(ctx);
5114 #else
5115 if (unlikely(!ctx->mem_idx)) {
5116 GEN_EXCP_PRIVOPC(ctx);
5117 return;
5118 }
5119 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5120 #endif
5121 }
5122
5123 /* 74xx TLB management */
5124 /* tlbld */
5125 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5126 {
5127 #if defined(CONFIG_USER_ONLY)
5128 GEN_EXCP_PRIVOPC(ctx);
5129 #else
5130 if (unlikely(!ctx->mem_idx)) {
5131 GEN_EXCP_PRIVOPC(ctx);
5132 return;
5133 }
5134 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5135 #endif
5136 }
5137
5138 /* tlbli */
5139 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5140 {
5141 #if defined(CONFIG_USER_ONLY)
5142 GEN_EXCP_PRIVOPC(ctx);
5143 #else
5144 if (unlikely(!ctx->mem_idx)) {
5145 GEN_EXCP_PRIVOPC(ctx);
5146 return;
5147 }
5148 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5149 #endif
5150 }
5151
5152 /* POWER instructions not in PowerPC 601 */
5153 /* clf */
5154 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5155 {
5156 /* Cache line flush: implemented as no-op */
5157 }
5158
5159 /* cli */
5160 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5161 {
5162 /* Cache line invalidate: privileged and treated as no-op */
5163 #if defined(CONFIG_USER_ONLY)
5164 GEN_EXCP_PRIVOPC(ctx);
5165 #else
5166 if (unlikely(!ctx->mem_idx)) {
5167 GEN_EXCP_PRIVOPC(ctx);
5168 return;
5169 }
5170 #endif
5171 }
5172
5173 /* dclst */
5174 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5175 {
5176 /* Data cache line store: treated as no-op */
5177 }
5178
5179 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5180 {
5181 #if defined(CONFIG_USER_ONLY)
5182 GEN_EXCP_PRIVOPC(ctx);
5183 #else
5184 int ra = rA(ctx->opcode);
5185 int rd = rD(ctx->opcode);
5186 TCGv t0;
5187 if (unlikely(!ctx->mem_idx)) {
5188 GEN_EXCP_PRIVOPC(ctx);
5189 return;
5190 }
5191 t0 = tcg_temp_new();
5192 gen_addr_reg_index(ctx, t0);
5193 tcg_gen_shri_tl(t0, t0, 28);
5194 tcg_gen_andi_tl(t0, t0, 0xF);
5195 gen_helper_load_sr(cpu_gpr[rd], t0);
5196 tcg_temp_free(t0);
5197 if (ra != 0 && ra != rd)
5198 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5199 #endif
5200 }
5201
5202 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5203 {
5204 #if defined(CONFIG_USER_ONLY)
5205 GEN_EXCP_PRIVOPC(ctx);
5206 #else
5207 TCGv t0;
5208 if (unlikely(!ctx->mem_idx)) {
5209 GEN_EXCP_PRIVOPC(ctx);
5210 return;
5211 }
5212 t0 = tcg_temp_new();
5213 gen_addr_reg_index(ctx, t0);
5214 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5215 tcg_temp_free(t0);
5216 #endif
5217 }
5218
5219 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5220 {
5221 #if defined(CONFIG_USER_ONLY)
5222 GEN_EXCP_PRIVOPC(ctx);
5223 #else
5224 if (unlikely(!ctx->mem_idx)) {
5225 GEN_EXCP_PRIVOPC(ctx);
5226 return;
5227 }
5228 gen_helper_rfsvc();
5229 GEN_SYNC(ctx);
5230 #endif
5231 }
5232
5233 /* svc is not implemented for now */
5234
5235 /* POWER2 specific instructions */
5236 /* Quad manipulation (load/store two floats at a time) */
5237
5238 /* lfq */
5239 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5240 {
5241 int rd = rD(ctx->opcode);
5242 TCGv t0;
5243 gen_set_access_type(ctx, ACCESS_FLOAT);
5244 t0 = tcg_temp_new();
5245 gen_addr_imm_index(ctx, t0, 0);
5246 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5247 gen_addr_add(ctx, t0, t0, 8);
5248 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5249 tcg_temp_free(t0);
5250 }
5251
5252 /* lfqu */
5253 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5254 {
5255 int ra = rA(ctx->opcode);
5256 int rd = rD(ctx->opcode);
5257 TCGv t0, t1;
5258 gen_set_access_type(ctx, ACCESS_FLOAT);
5259 t0 = tcg_temp_new();
5260 t1 = tcg_temp_new();
5261 gen_addr_imm_index(ctx, t0, 0);
5262 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5263 gen_addr_add(ctx, t1, t0, 8);
5264 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5265 if (ra != 0)
5266 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5267 tcg_temp_free(t0);
5268 tcg_temp_free(t1);
5269 }
5270
5271 /* lfqux */
5272 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5273 {
5274 int ra = rA(ctx->opcode);
5275 int rd = rD(ctx->opcode);
5276 gen_set_access_type(ctx, ACCESS_FLOAT);
5277 TCGv t0, t1;
5278 t0 = tcg_temp_new();
5279 gen_addr_reg_index(ctx, t0);
5280 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5281 t1 = tcg_temp_new();
5282 gen_addr_add(ctx, t1, t0, 8);
5283 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5284 tcg_temp_free(t1);
5285 if (ra != 0)
5286 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5287 tcg_temp_free(t0);
5288 }
5289
5290 /* lfqx */
5291 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5292 {
5293 int rd = rD(ctx->opcode);
5294 TCGv t0;
5295 gen_set_access_type(ctx, ACCESS_FLOAT);
5296 t0 = tcg_temp_new();
5297 gen_addr_reg_index(ctx, t0);
5298 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5299 gen_addr_add(ctx, t0, t0, 8);
5300 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5301 tcg_temp_free(t0);
5302 }
5303
5304 /* stfq */
5305 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5306 {
5307 int rd = rD(ctx->opcode);
5308 TCGv t0;
5309 gen_set_access_type(ctx, ACCESS_FLOAT);
5310 t0 = tcg_temp_new();
5311 gen_addr_imm_index(ctx, t0, 0);
5312 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5313 gen_addr_add(ctx, t0, t0, 8);
5314 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5315 tcg_temp_free(t0);
5316 }
5317
5318 /* stfqu */
5319 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5320 {
5321 int ra = rA(ctx->opcode);
5322 int rd = rD(ctx->opcode);
5323 TCGv t0, t1;
5324 gen_set_access_type(ctx, ACCESS_FLOAT);
5325 t0 = tcg_temp_new();
5326 gen_addr_imm_index(ctx, t0, 0);
5327 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5328 t1 = tcg_temp_new();
5329 gen_addr_add(ctx, t1, t0, 8);
5330 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5331 tcg_temp_free(t1);
5332 if (ra != 0)
5333 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5334 tcg_temp_free(t0);
5335 }
5336
5337 /* stfqux */
5338 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5339 {
5340 int ra = rA(ctx->opcode);
5341 int rd = rD(ctx->opcode);
5342 TCGv t0, t1;
5343 gen_set_access_type(ctx, ACCESS_FLOAT);
5344 t0 = tcg_temp_new();
5345 gen_addr_reg_index(ctx, t0);
5346 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5347 t1 = tcg_temp_new();
5348 gen_addr_add(ctx, t1, t0, 8);
5349 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5350 tcg_temp_free(t1);
5351 if (ra != 0)
5352 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5353 tcg_temp_free(t0);
5354 }
5355
5356 /* stfqx */
5357 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5358 {
5359 int rd = rD(ctx->opcode);
5360 TCGv t0;
5361 gen_set_access_type(ctx, ACCESS_FLOAT);
5362 t0 = tcg_temp_new();
5363 gen_addr_reg_index(ctx, t0);
5364 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5365 gen_addr_add(ctx, t0, t0, 8);
5366 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5367 tcg_temp_free(t0);
5368 }
5369
5370 /* BookE specific instructions */
5371 /* XXX: not implemented on 440 ? */
5372 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5373 {
5374 /* XXX: TODO */
5375 GEN_EXCP_INVAL(ctx);
5376 }
5377
5378 /* XXX: not implemented on 440 ? */
5379 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5380 {
5381 #if defined(CONFIG_USER_ONLY)
5382 GEN_EXCP_PRIVOPC(ctx);
5383 #else
5384 TCGv t0;
5385 if (unlikely(!ctx->mem_idx)) {
5386 GEN_EXCP_PRIVOPC(ctx);
5387 return;
5388 }
5389 t0 = tcg_temp_new();
5390 gen_addr_reg_index(ctx, t0);
5391 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5392 tcg_temp_free(t0);
5393 #endif
5394 }
5395
5396 /* All 405 MAC instructions are translated here */
5397 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5398 int opc2, int opc3,
5399 int ra, int rb, int rt, int Rc)
5400 {
5401 TCGv t0, t1;
5402
5403 t0 = tcg_temp_local_new();
5404 t1 = tcg_temp_local_new();
5405
5406 switch (opc3 & 0x0D) {
5407 case 0x05:
5408 /* macchw - macchw. - macchwo - macchwo. */
5409 /* macchws - macchws. - macchwso - macchwso. */
5410 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5411 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5412 /* mulchw - mulchw. */
5413 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5414 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5415 tcg_gen_ext16s_tl(t1, t1);
5416 break;
5417 case 0x04:
5418 /* macchwu - macchwu. - macchwuo - macchwuo. */
5419 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5420 /* mulchwu - mulchwu. */
5421 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5422 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5423 tcg_gen_ext16u_tl(t1, t1);
5424 break;
5425 case 0x01:
5426 /* machhw - machhw. - machhwo - machhwo. */
5427 /* machhws - machhws. - machhwso - machhwso. */
5428 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5429 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5430 /* mulhhw - mulhhw. */
5431 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5432 tcg_gen_ext16s_tl(t0, t0);
5433 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5434 tcg_gen_ext16s_tl(t1, t1);
5435 break;
5436 case 0x00:
5437 /* machhwu - machhwu. - machhwuo - machhwuo. */
5438 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5439 /* mulhhwu - mulhhwu. */
5440 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5441 tcg_gen_ext16u_tl(t0, t0);
5442 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5443 tcg_gen_ext16u_tl(t1, t1);
5444 break;
5445 case 0x0D:
5446 /* maclhw - maclhw. - maclhwo - maclhwo. */
5447 /* maclhws - maclhws. - maclhwso - maclhwso. */
5448 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5449 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5450 /* mullhw - mullhw. */
5451 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5452 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5453 break;
5454 case 0x0C:
5455 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5456 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5457 /* mullhwu - mullhwu. */
5458 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5459 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5460 break;
5461 }
5462 if (opc2 & 0x04) {
5463 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5464 tcg_gen_mul_tl(t1, t0, t1);
5465 if (opc2 & 0x02) {
5466 /* nmultiply-and-accumulate (0x0E) */
5467 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5468 } else {
5469 /* multiply-and-accumulate (0x0C) */
5470 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5471 }
5472
5473 if (opc3 & 0x12) {
5474 /* Check overflow and/or saturate */
5475 int l1 = gen_new_label();
5476
5477 if (opc3 & 0x10) {
5478 /* Start with XER OV disabled, the most likely case */
5479 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5480 }
5481 if (opc3 & 0x01) {
5482 /* Signed */
5483 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5484 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5485 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5486 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5487 if (opc3 & 0x02) {
5488 /* Saturate */
5489 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5490 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5491 }
5492 } else {
5493 /* Unsigned */
5494 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5495 if (opc3 & 0x02) {
5496 /* Saturate */
5497 tcg_gen_movi_tl(t0, UINT32_MAX);
5498 }
5499 }
5500 if (opc3 & 0x10) {
5501 /* Check overflow */
5502 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5503 }
5504 gen_set_label(l1);
5505 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5506 }
5507 } else {
5508 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5509 }
5510 tcg_temp_free(t0);
5511 tcg_temp_free(t1);
5512 if (unlikely(Rc) != 0) {
5513 /* Update Rc0 */
5514 gen_set_Rc0(ctx, cpu_gpr[rt]);
5515 }
5516 }
5517
5518 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5519 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5520 { \
5521 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5522 rD(ctx->opcode), Rc(ctx->opcode)); \
5523 }
5524
5525 /* macchw - macchw. */
5526 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5527 /* macchwo - macchwo. */
5528 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5529 /* macchws - macchws. */
5530 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5531 /* macchwso - macchwso. */
5532 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5533 /* macchwsu - macchwsu. */
5534 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5535 /* macchwsuo - macchwsuo. */
5536 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5537 /* macchwu - macchwu. */
5538 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5539 /* macchwuo - macchwuo. */
5540 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5541 /* machhw - machhw. */
5542 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5543 /* machhwo - machhwo. */
5544 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5545 /* machhws - machhws. */
5546 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5547 /* machhwso - machhwso. */
5548 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5549 /* machhwsu - machhwsu. */
5550 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5551 /* machhwsuo - machhwsuo. */
5552 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5553 /* machhwu - machhwu. */
5554 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5555 /* machhwuo - machhwuo. */
5556 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5557 /* maclhw - maclhw. */
5558 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5559 /* maclhwo - maclhwo. */
5560 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5561 /* maclhws - maclhws. */
5562 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5563 /* maclhwso - maclhwso. */
5564 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5565 /* maclhwu - maclhwu. */
5566 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5567 /* maclhwuo - maclhwuo. */
5568 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5569 /* maclhwsu - maclhwsu. */
5570 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5571 /* maclhwsuo - maclhwsuo. */
5572 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5573 /* nmacchw - nmacchw. */
5574 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5575 /* nmacchwo - nmacchwo. */
5576 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5577 /* nmacchws - nmacchws. */
5578 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5579 /* nmacchwso - nmacchwso. */
5580 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5581 /* nmachhw - nmachhw. */
5582 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5583 /* nmachhwo - nmachhwo. */
5584 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5585 /* nmachhws - nmachhws. */
5586 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5587 /* nmachhwso - nmachhwso. */
5588 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5589 /* nmaclhw - nmaclhw. */
5590 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5591 /* nmaclhwo - nmaclhwo. */
5592 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5593 /* nmaclhws - nmaclhws. */
5594 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5595 /* nmaclhwso - nmaclhwso. */
5596 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5597
5598 /* mulchw - mulchw. */
5599 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5600 /* mulchwu - mulchwu. */
5601 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5602 /* mulhhw - mulhhw. */
5603 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5604 /* mulhhwu - mulhhwu. */
5605 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5606 /* mullhw - mullhw. */
5607 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5608 /* mullhwu - mullhwu. */
5609 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5610
5611 /* mfdcr */
5612 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5613 {
5614 #if defined(CONFIG_USER_ONLY)
5615 GEN_EXCP_PRIVREG(ctx);
5616 #else
5617 TCGv dcrn;
5618 if (unlikely(!ctx->mem_idx)) {
5619 GEN_EXCP_PRIVREG(ctx);
5620 return;
5621 }
5622 /* NIP cannot be restored if the memory exception comes from an helper */
5623 gen_update_nip(ctx, ctx->nip - 4);
5624 dcrn = tcg_const_tl(SPR(ctx->opcode));
5625 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5626 tcg_temp_free(dcrn);
5627 #endif
5628 }
5629
5630 /* mtdcr */
5631 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5632 {
5633 #if defined(CONFIG_USER_ONLY)
5634 GEN_EXCP_PRIVREG(ctx);
5635 #else
5636 TCGv dcrn;
5637 if (unlikely(!ctx->mem_idx)) {
5638 GEN_EXCP_PRIVREG(ctx);
5639 return;
5640 }
5641 /* NIP cannot be restored if the memory exception comes from an helper */
5642 gen_update_nip(ctx, ctx->nip - 4);
5643 dcrn = tcg_const_tl(SPR(ctx->opcode));
5644 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5645 tcg_temp_free(dcrn);
5646 #endif
5647 }
5648
5649 /* mfdcrx */
5650 /* XXX: not implemented on 440 ? */
5651 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5652 {
5653 #if defined(CONFIG_USER_ONLY)
5654 GEN_EXCP_PRIVREG(ctx);
5655 #else
5656 if (unlikely(!ctx->mem_idx)) {
5657 GEN_EXCP_PRIVREG(ctx);
5658 return;
5659 }
5660 /* NIP cannot be restored if the memory exception comes from an helper */
5661 gen_update_nip(ctx, ctx->nip - 4);
5662 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5663 /* Note: Rc update flag set leads to undefined state of Rc0 */
5664 #endif
5665 }
5666
5667 /* mtdcrx */
5668 /* XXX: not implemented on 440 ? */
5669 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5670 {
5671 #if defined(CONFIG_USER_ONLY)
5672 GEN_EXCP_PRIVREG(ctx);
5673 #else
5674 if (unlikely(!ctx->mem_idx)) {
5675 GEN_EXCP_PRIVREG(ctx);
5676 return;
5677 }
5678 /* NIP cannot be restored if the memory exception comes from an helper */
5679 gen_update_nip(ctx, ctx->nip - 4);
5680 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5681 /* Note: Rc update flag set leads to undefined state of Rc0 */
5682 #endif
5683 }
5684
5685 /* mfdcrux (PPC 460) : user-mode access to DCR */
5686 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5687 {
5688 /* NIP cannot be restored if the memory exception comes from an helper */
5689 gen_update_nip(ctx, ctx->nip - 4);
5690 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5691 /* Note: Rc update flag set leads to undefined state of Rc0 */
5692 }
5693
5694 /* mtdcrux (PPC 460) : user-mode access to DCR */
5695 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5696 {
5697 /* NIP cannot be restored if the memory exception comes from an helper */
5698 gen_update_nip(ctx, ctx->nip - 4);
5699 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5700 /* Note: Rc update flag set leads to undefined state of Rc0 */
5701 }
5702
5703 /* dccci */
5704 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5705 {
5706 #if defined(CONFIG_USER_ONLY)
5707 GEN_EXCP_PRIVOPC(ctx);
5708 #else
5709 if (unlikely(!ctx->mem_idx)) {
5710 GEN_EXCP_PRIVOPC(ctx);
5711 return;
5712 }
5713 /* interpreted as no-op */
5714 #endif
5715 }
5716
5717 /* dcread */
5718 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5719 {
5720 #if defined(CONFIG_USER_ONLY)
5721 GEN_EXCP_PRIVOPC(ctx);
5722 #else
5723 TCGv EA, val;
5724 if (unlikely(!ctx->mem_idx)) {
5725 GEN_EXCP_PRIVOPC(ctx);
5726 return;
5727 }
5728 gen_set_access_type(ctx, ACCESS_CACHE);
5729 EA = tcg_temp_new();
5730 gen_addr_reg_index(ctx, EA);
5731 val = tcg_temp_new();
5732 gen_qemu_ld32u(ctx, val, EA);
5733 tcg_temp_free(val);
5734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5735 tcg_temp_free(EA);
5736 #endif
5737 }
5738
5739 /* icbt */
5740 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5741 {
5742 /* interpreted as no-op */
5743 /* XXX: specification say this is treated as a load by the MMU
5744 * but does not generate any exception
5745 */
5746 }
5747
5748 /* iccci */
5749 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5750 {
5751 #if defined(CONFIG_USER_ONLY)
5752 GEN_EXCP_PRIVOPC(ctx);
5753 #else
5754 if (unlikely(!ctx->mem_idx)) {
5755 GEN_EXCP_PRIVOPC(ctx);
5756 return;
5757 }
5758 /* interpreted as no-op */
5759 #endif
5760 }
5761
5762 /* icread */
5763 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5764 {
5765 #if defined(CONFIG_USER_ONLY)
5766 GEN_EXCP_PRIVOPC(ctx);
5767 #else
5768 if (unlikely(!ctx->mem_idx)) {
5769 GEN_EXCP_PRIVOPC(ctx);
5770 return;
5771 }
5772 /* interpreted as no-op */
5773 #endif
5774 }
5775
5776 /* rfci (mem_idx only) */
5777 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5778 {
5779 #if defined(CONFIG_USER_ONLY)
5780 GEN_EXCP_PRIVOPC(ctx);
5781 #else
5782 if (unlikely(!ctx->mem_idx)) {
5783 GEN_EXCP_PRIVOPC(ctx);
5784 return;
5785 }
5786 /* Restore CPU state */
5787 gen_helper_40x_rfci();
5788 GEN_SYNC(ctx);
5789 #endif
5790 }
5791
5792 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5793 {
5794 #if defined(CONFIG_USER_ONLY)
5795 GEN_EXCP_PRIVOPC(ctx);
5796 #else
5797 if (unlikely(!ctx->mem_idx)) {
5798 GEN_EXCP_PRIVOPC(ctx);
5799 return;
5800 }
5801 /* Restore CPU state */
5802 gen_helper_rfci();
5803 GEN_SYNC(ctx);
5804 #endif
5805 }
5806
5807 /* BookE specific */
5808 /* XXX: not implemented on 440 ? */
5809 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5810 {
5811 #if defined(CONFIG_USER_ONLY)
5812 GEN_EXCP_PRIVOPC(ctx);
5813 #else
5814 if (unlikely(!ctx->mem_idx)) {
5815 GEN_EXCP_PRIVOPC(ctx);
5816 return;
5817 }
5818 /* Restore CPU state */
5819 gen_helper_rfdi();
5820 GEN_SYNC(ctx);
5821 #endif
5822 }
5823
5824 /* XXX: not implemented on 440 ? */
5825 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5826 {
5827 #if defined(CONFIG_USER_ONLY)
5828 GEN_EXCP_PRIVOPC(ctx);
5829 #else
5830 if (unlikely(!ctx->mem_idx)) {
5831 GEN_EXCP_PRIVOPC(ctx);
5832 return;
5833 }
5834 /* Restore CPU state */
5835 gen_helper_rfmci();
5836 GEN_SYNC(ctx);
5837 #endif
5838 }
5839
5840 /* TLB management - PowerPC 405 implementation */
5841 /* tlbre */
5842 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5843 {
5844 #if defined(CONFIG_USER_ONLY)
5845 GEN_EXCP_PRIVOPC(ctx);
5846 #else
5847 if (unlikely(!ctx->mem_idx)) {
5848 GEN_EXCP_PRIVOPC(ctx);
5849 return;
5850 }
5851 switch (rB(ctx->opcode)) {
5852 case 0:
5853 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5854 break;
5855 case 1:
5856 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5857 break;
5858 default:
5859 GEN_EXCP_INVAL(ctx);
5860 break;
5861 }
5862 #endif
5863 }
5864
5865 /* tlbsx - tlbsx. */
5866 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5867 {
5868 #if defined(CONFIG_USER_ONLY)
5869 GEN_EXCP_PRIVOPC(ctx);
5870 #else
5871 TCGv t0;
5872 if (unlikely(!ctx->mem_idx)) {
5873 GEN_EXCP_PRIVOPC(ctx);
5874 return;
5875 }
5876 t0 = tcg_temp_new();
5877 gen_addr_reg_index(ctx, t0);
5878 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5879 tcg_temp_free(t0);
5880 if (Rc(ctx->opcode)) {
5881 int l1 = gen_new_label();
5882 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5883 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5884 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5885 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5886 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5887 gen_set_label(l1);
5888 }
5889 #endif
5890 }
5891
5892 /* tlbwe */
5893 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5894 {
5895 #if defined(CONFIG_USER_ONLY)
5896 GEN_EXCP_PRIVOPC(ctx);
5897 #else
5898 if (unlikely(!ctx->mem_idx)) {
5899 GEN_EXCP_PRIVOPC(ctx);
5900 return;
5901 }
5902 switch (rB(ctx->opcode)) {
5903 case 0:
5904 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5905 break;
5906 case 1:
5907 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5908 break;
5909 default:
5910 GEN_EXCP_INVAL(ctx);
5911 break;
5912 }
5913 #endif
5914 }
5915
5916 /* TLB management - PowerPC 440 implementation */
5917 /* tlbre */
5918 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5919 {
5920 #if defined(CONFIG_USER_ONLY)
5921 GEN_EXCP_PRIVOPC(ctx);
5922 #else
5923 if (unlikely(!ctx->mem_idx)) {
5924 GEN_EXCP_PRIVOPC(ctx);
5925 return;
5926 }
5927 switch (rB(ctx->opcode)) {
5928 case 0:
5929 case 1:
5930 case 2:
5931 {
5932 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5933 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5934 tcg_temp_free_i32(t0);
5935 }
5936 break;
5937 default:
5938 GEN_EXCP_INVAL(ctx);
5939 break;
5940 }
5941 #endif
5942 }
5943
5944 /* tlbsx - tlbsx. */
5945 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5946 {
5947 #if defined(CONFIG_USER_ONLY)
5948 GEN_EXCP_PRIVOPC(ctx);
5949 #else
5950 TCGv t0;
5951 if (unlikely(!ctx->mem_idx)) {
5952 GEN_EXCP_PRIVOPC(ctx);
5953 return;
5954 }
5955 t0 = tcg_temp_new();
5956 gen_addr_reg_index(ctx, t0);
5957 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5958 tcg_temp_free(t0);
5959 if (Rc(ctx->opcode)) {
5960 int l1 = gen_new_label();
5961 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5962 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5963 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5964 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5965 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5966 gen_set_label(l1);
5967 }
5968 #endif
5969 }
5970
5971 /* tlbwe */
5972 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5973 {
5974 #if defined(CONFIG_USER_ONLY)
5975 GEN_EXCP_PRIVOPC(ctx);
5976 #else
5977 if (unlikely(!ctx->mem_idx)) {
5978 GEN_EXCP_PRIVOPC(ctx);
5979 return;
5980 }
5981 switch (rB(ctx->opcode)) {
5982 case 0:
5983 case 1:
5984 case 2:
5985 {
5986 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5987 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5988 tcg_temp_free_i32(t0);
5989 }
5990 break;
5991 default:
5992 GEN_EXCP_INVAL(ctx);
5993 break;
5994 }
5995 #endif
5996 }
5997
5998 /* wrtee */
5999 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6000 {
6001 #if defined(CONFIG_USER_ONLY)
6002 GEN_EXCP_PRIVOPC(ctx);
6003 #else
6004 TCGv t0;
6005 if (unlikely(!ctx->mem_idx)) {
6006 GEN_EXCP_PRIVOPC(ctx);
6007 return;
6008 }
6009 t0 = tcg_temp_new();
6010 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6011 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6012 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6013 tcg_temp_free(t0);
6014 /* Stop translation to have a chance to raise an exception
6015 * if we just set msr_ee to 1
6016 */
6017 GEN_STOP(ctx);
6018 #endif
6019 }
6020
6021 /* wrteei */
6022 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6023 {
6024 #if defined(CONFIG_USER_ONLY)
6025 GEN_EXCP_PRIVOPC(ctx);
6026 #else
6027 if (unlikely(!ctx->mem_idx)) {
6028 GEN_EXCP_PRIVOPC(ctx);
6029 return;
6030 }
6031 if (ctx->opcode & 0x00010000) {
6032 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6033 /* Stop translation to have a chance to raise an exception */
6034 GEN_STOP(ctx);
6035 } else {
6036 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6037 }
6038 #endif
6039 }
6040
6041 /* PowerPC 440 specific instructions */
6042 /* dlmzb */
6043 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6044 {
6045 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6046 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6047 cpu_gpr[rB(ctx->opcode)], t0);
6048 tcg_temp_free_i32(t0);
6049 }
6050
6051 /* mbar replaces eieio on 440 */
6052 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
6053 {
6054 /* interpreted as no-op */
6055 }
6056
6057 /* msync replaces sync on 440 */
6058 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6059 {
6060 /* interpreted as no-op */
6061 }
6062
6063 /* icbt */
6064 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6065 {
6066 /* interpreted as no-op */
6067 /* XXX: specification say this is treated as a load by the MMU
6068 * but does not generate any exception
6069 */
6070 }
6071
6072 /*** Altivec vector extension ***/
6073 /* Altivec registers moves */
6074
6075 #define GEN_VR_LDX(name, opc2, opc3) \
6076 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6077 { \
6078 TCGv EA; \
6079 if (unlikely(!ctx->altivec_enabled)) { \
6080 GEN_EXCP_NO_VR(ctx); \
6081 return; \
6082 } \
6083 gen_set_access_type(ctx, ACCESS_INT); \
6084 EA = tcg_temp_new(); \
6085 gen_addr_reg_index(ctx, EA); \
6086 tcg_gen_andi_tl(EA, EA, ~0xf); \
6087 if (ctx->le_mode) { \
6088 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6089 tcg_gen_addi_tl(EA, EA, 8); \
6090 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6091 } else { \
6092 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6093 tcg_gen_addi_tl(EA, EA, 8); \
6094 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6095 } \
6096 tcg_temp_free(EA); \
6097 }
6098
6099 #define GEN_VR_STX(name, opc2, opc3) \
6100 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6101 { \
6102 TCGv EA; \
6103 if (unlikely(!ctx->altivec_enabled)) { \
6104 GEN_EXCP_NO_VR(ctx); \
6105 return; \
6106 } \
6107 gen_set_access_type(ctx, ACCESS_INT); \
6108 EA = tcg_temp_new(); \
6109 gen_addr_reg_index(ctx, EA); \
6110 tcg_gen_andi_tl(EA, EA, ~0xf); \
6111 if (ctx->le_mode) { \
6112 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6113 tcg_gen_addi_tl(EA, EA, 8); \
6114 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6115 } else { \
6116 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6117 tcg_gen_addi_tl(EA, EA, 8); \
6118 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6119 } \
6120 tcg_temp_free(EA); \
6121 }
6122
6123 GEN_VR_LDX(lvx, 0x07, 0x03);
6124 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6125 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6126
6127 GEN_VR_STX(svx, 0x07, 0x07);
6128 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6129 GEN_VR_STX(svxl, 0x07, 0x0F);
6130
6131 /*** SPE extension ***/
6132 /* Register moves */
6133
6134 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6135 #if defined(TARGET_PPC64)
6136 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6137 #else
6138 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6139 #endif
6140 }
6141
6142 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6143 #if defined(TARGET_PPC64)
6144 tcg_gen_mov_i64(cpu_gpr[reg], t);
6145 #else
6146 TCGv_i64 tmp = tcg_temp_new_i64();
6147 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6148 tcg_gen_shri_i64(tmp, t, 32);
6149 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6150 tcg_temp_free_i64(tmp);
6151 #endif
6152 }
6153
6154 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6155 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6156 { \
6157 if (Rc(ctx->opcode)) \
6158 gen_##name1(ctx); \
6159 else \
6160 gen_##name0(ctx); \
6161 }
6162
6163 /* Handler for undefined SPE opcodes */
6164 static always_inline void gen_speundef (DisasContext *ctx)
6165 {
6166 GEN_EXCP_INVAL(ctx);
6167 }
6168
6169 /* SPE logic */
6170 #if defined(TARGET_PPC64)
6171 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6172 static always_inline void gen_##name (DisasContext *ctx) \
6173 { \
6174 if (unlikely(!ctx->spe_enabled)) { \
6175 GEN_EXCP_NO_AP(ctx); \
6176 return; \
6177 } \
6178 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6179 cpu_gpr[rB(ctx->opcode)]); \
6180 }
6181 #else
6182 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6183 static always_inline void gen_##name (DisasContext *ctx) \
6184 { \
6185 if (unlikely(!ctx->spe_enabled)) { \
6186 GEN_EXCP_NO_AP(ctx); \
6187 return; \
6188 } \
6189 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6190 cpu_gpr[rB(ctx->opcode)]); \
6191 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6192 cpu_gprh[rB(ctx->opcode)]); \
6193 }
6194 #endif
6195
6196 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6197 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6198 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6199 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6200 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6201 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6202 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6203 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6204
6205 /* SPE logic immediate */
6206 #if defined(TARGET_PPC64)
6207 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6208 static always_inline void gen_##name (DisasContext *ctx) \
6209 { \
6210 if (unlikely(!ctx->spe_enabled)) { \
6211 GEN_EXCP_NO_AP(ctx); \
6212 return; \
6213 } \
6214 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6215 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6216 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6217 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6218 tcg_opi(t0, t0, rB(ctx->opcode)); \
6219 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6220 tcg_gen_trunc_i64_i32(t1, t2); \
6221 tcg_temp_free_i64(t2); \
6222 tcg_opi(t1, t1, rB(ctx->opcode)); \
6223 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6224 tcg_temp_free_i32(t0); \
6225 tcg_temp_free_i32(t1); \
6226 }
6227 #else
6228 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6229 static always_inline void gen_##name (DisasContext *ctx) \
6230 { \
6231 if (unlikely(!ctx->spe_enabled)) { \
6232 GEN_EXCP_NO_AP(ctx); \
6233 return; \
6234 } \
6235 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6236 rB(ctx->opcode)); \
6237 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6238 rB(ctx->opcode)); \
6239 }
6240 #endif
6241 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6242 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6243 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6244 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6245
6246 /* SPE arithmetic */
6247 #if defined(TARGET_PPC64)
6248 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6249 static always_inline void gen_##name (DisasContext *ctx) \
6250 { \
6251 if (unlikely(!ctx->spe_enabled)) { \
6252 GEN_EXCP_NO_AP(ctx); \
6253 return; \
6254 } \
6255 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6256 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6257 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6258 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6259 tcg_op(t0, t0); \
6260 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6261 tcg_gen_trunc_i64_i32(t1, t2); \
6262 tcg_temp_free_i64(t2); \
6263 tcg_op(t1, t1); \
6264 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6265 tcg_temp_free_i32(t0); \
6266 tcg_temp_free_i32(t1); \
6267 }
6268 #else
6269 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6270 static always_inline void gen_##name (DisasContext *ctx) \
6271 { \
6272 if (unlikely(!ctx->spe_enabled)) { \
6273 GEN_EXCP_NO_AP(ctx); \
6274 return; \
6275 } \
6276 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6277 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6278 }
6279 #endif
6280
6281 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6282 {
6283 int l1 = gen_new_label();
6284 int l2 = gen_new_label();
6285
6286 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6287 tcg_gen_neg_i32(ret, arg1);
6288 tcg_gen_br(l2);
6289 gen_set_label(l1);
6290 tcg_gen_mov_i32(ret, arg1);
6291 gen_set_label(l2);
6292 }
6293 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6294 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6295 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6296 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6297 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6298 {
6299 tcg_gen_addi_i32(ret, arg1, 0x8000);
6300 tcg_gen_ext16u_i32(ret, ret);
6301 }
6302 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6303 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6304 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6305
6306 #if defined(TARGET_PPC64)
6307 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6308 static always_inline void gen_##name (DisasContext *ctx) \
6309 { \
6310 if (unlikely(!ctx->spe_enabled)) { \
6311 GEN_EXCP_NO_AP(ctx); \
6312 return; \
6313 } \
6314 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6315 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6316 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6317 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
6318 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6319 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6320 tcg_op(t0, t0, t2); \
6321 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6322 tcg_gen_trunc_i64_i32(t1, t3); \
6323 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6324 tcg_gen_trunc_i64_i32(t2, t3); \
6325 tcg_temp_free_i64(t3); \
6326 tcg_op(t1, t1, t2); \
6327 tcg_temp_free_i32(t2); \
6328 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6329 tcg_temp_free_i32(t0); \
6330 tcg_temp_free_i32(t1); \
6331 }
6332 #else
6333 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6334 static always_inline void gen_##name (DisasContext *ctx) \
6335 { \
6336 if (unlikely(!ctx->spe_enabled)) { \
6337 GEN_EXCP_NO_AP(ctx); \
6338 return; \
6339 } \
6340 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6341 cpu_gpr[rB(ctx->opcode)]); \
6342 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6343 cpu_gprh[rB(ctx->opcode)]); \
6344 }
6345 #endif
6346
6347 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6348 {
6349 TCGv_i32 t0;
6350 int l1, l2;
6351
6352 l1 = gen_new_label();
6353 l2 = gen_new_label();
6354 t0 = tcg_temp_local_new_i32();
6355 /* No error here: 6 bits are used */
6356 tcg_gen_andi_i32(t0, arg2, 0x3F);
6357 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6358 tcg_gen_shr_i32(ret, arg1, t0);
6359 tcg_gen_br(l2);
6360 gen_set_label(l1);
6361 tcg_gen_movi_i32(ret, 0);
6362 tcg_gen_br(l2);
6363 tcg_temp_free_i32(t0);
6364 }
6365 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6366 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6367 {
6368 TCGv_i32 t0;
6369 int l1, l2;
6370
6371 l1 = gen_new_label();
6372 l2 = gen_new_label();
6373 t0 = tcg_temp_local_new_i32();
6374 /* No error here: 6 bits are used */
6375 tcg_gen_andi_i32(t0, arg2, 0x3F);
6376 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6377 tcg_gen_sar_i32(ret, arg1, t0);
6378 tcg_gen_br(l2);
6379 gen_set_label(l1);
6380 tcg_gen_movi_i32(ret, 0);
6381 tcg_gen_br(l2);
6382 tcg_temp_free_i32(t0);
6383 }
6384 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6385 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6386 {
6387 TCGv_i32 t0;
6388 int l1, l2;
6389
6390 l1 = gen_new_label();
6391 l2 = gen_new_label();
6392 t0 = tcg_temp_local_new_i32();
6393 /* No error here: 6 bits are used */
6394 tcg_gen_andi_i32(t0, arg2, 0x3F);
6395 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6396 tcg_gen_shl_i32(ret, arg1, t0);
6397 tcg_gen_br(l2);
6398 gen_set_label(l1);
6399 tcg_gen_movi_i32(ret, 0);
6400 tcg_gen_br(l2);
6401 tcg_temp_free_i32(t0);
6402 }
6403 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6404 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6405 {
6406 TCGv_i32 t0 = tcg_temp_new_i32();
6407 tcg_gen_andi_i32(t0, arg2, 0x1F);
6408 tcg_gen_rotl_i32(ret, arg1, t0);
6409 tcg_temp_free_i32(t0);
6410 }
6411 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6412 static always_inline void gen_evmergehi (DisasContext *ctx)
6413 {
6414 if (unlikely(!ctx->spe_enabled)) {
6415 GEN_EXCP_NO_AP(ctx);
6416 return;
6417 }
6418 #if defined(TARGET_PPC64)
6419 TCGv t0 = tcg_temp_new();
6420 TCGv t1 = tcg_temp_new();
6421 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6422 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6423 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6424 tcg_temp_free(t0);
6425 tcg_temp_free(t1);
6426 #else
6427 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6428 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6429 #endif
6430 }
6431 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6432 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6433 {
6434 tcg_gen_sub_i32(ret, arg2, arg1);
6435 }
6436 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6437
6438 /* SPE arithmetic immediate */
6439 #if defined(TARGET_PPC64)
6440 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6441 static always_inline void gen_##name (DisasContext *ctx) \
6442 { \
6443 if (unlikely(!ctx->spe_enabled)) { \
6444 GEN_EXCP_NO_AP(ctx); \
6445 return; \
6446 } \
6447 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6448 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6449 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6450 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6451 tcg_op(t0, t0, rA(ctx->opcode)); \
6452 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6453 tcg_gen_trunc_i64_i32(t1, t2); \
6454 tcg_temp_free_i64(t2); \
6455 tcg_op(t1, t1, rA(ctx->opcode)); \
6456 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6457 tcg_temp_free_i32(t0); \
6458 tcg_temp_free_i32(t1); \
6459 }
6460 #else
6461 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6462 static always_inline void gen_##name (DisasContext *ctx) \
6463 { \
6464 if (unlikely(!ctx->spe_enabled)) { \
6465 GEN_EXCP_NO_AP(ctx); \
6466 return; \
6467 } \
6468 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6469 rA(ctx->opcode)); \
6470 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6471 rA(ctx->opcode)); \
6472 }
6473 #endif
6474 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6475 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6476
6477 /* SPE comparison */
6478 #if defined(TARGET_PPC64)
6479 #define GEN_SPEOP_COMP(name, tcg_cond) \
6480 static always_inline void gen_##name (DisasContext *ctx) \
6481 { \
6482 if (unlikely(!ctx->spe_enabled)) { \
6483 GEN_EXCP_NO_AP(ctx); \
6484 return; \
6485 } \
6486 int l1 = gen_new_label(); \
6487 int l2 = gen_new_label(); \
6488 int l3 = gen_new_label(); \
6489 int l4 = gen_new_label(); \
6490 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6491 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6492 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6493 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6494 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6495 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6496 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6497 tcg_gen_br(l2); \
6498 gen_set_label(l1); \
6499 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6500 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6501 gen_set_label(l2); \
6502 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6503 tcg_gen_trunc_i64_i32(t0, t2); \
6504 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6505 tcg_gen_trunc_i64_i32(t1, t2); \
6506 tcg_temp_free_i64(t2); \
6507 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6508 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6509 ~(CRF_CH | CRF_CH_AND_CL)); \
6510 tcg_gen_br(l4); \
6511 gen_set_label(l3); \
6512 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6513 CRF_CH | CRF_CH_OR_CL); \
6514 gen_set_label(l4); \
6515 tcg_temp_free_i32(t0); \
6516 tcg_temp_free_i32(t1); \
6517 }
6518 #else
6519 #define GEN_SPEOP_COMP(name, tcg_cond) \
6520 static always_inline void gen_##name (DisasContext *ctx) \
6521 { \
6522 if (unlikely(!ctx->spe_enabled)) { \
6523 GEN_EXCP_NO_AP(ctx); \
6524 return; \
6525 } \
6526 int l1 = gen_new_label(); \
6527 int l2 = gen_new_label(); \
6528 int l3 = gen_new_label(); \
6529 int l4 = gen_new_label(); \
6530 \
6531 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6532 cpu_gpr[rB(ctx->opcode)], l1); \
6533 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6534 tcg_gen_br(l2); \
6535 gen_set_label(l1); \
6536 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6537 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6538 gen_set_label(l2); \
6539 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6540 cpu_gprh[rB(ctx->opcode)], l3); \
6541 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6542 ~(CRF_CH | CRF_CH_AND_CL)); \
6543 tcg_gen_br(l4); \
6544 gen_set_label(l3); \
6545 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6546 CRF_CH | CRF_CH_OR_CL); \
6547 gen_set_label(l4); \
6548 }
6549 #endif
6550 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6551 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6552 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6553 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6554 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6555
6556 /* SPE misc */
6557 static always_inline void gen_brinc (DisasContext *ctx)
6558 {
6559 /* Note: brinc is usable even if SPE is disabled */
6560 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6561 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6562 }
6563 static always_inline void gen_evmergelo (DisasContext *ctx)
6564 {
6565 if (unlikely(!ctx->spe_enabled)) {
6566 GEN_EXCP_NO_AP(ctx);
6567 return;
6568 }
6569 #if defined(TARGET_PPC64)
6570 TCGv t0 = tcg_temp_new();
6571 TCGv t1 = tcg_temp_new();
6572 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6573 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6574 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6575 tcg_temp_free(t0);
6576 tcg_temp_free(t1);
6577 #else
6578 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6579 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6580 #endif
6581 }
6582 static always_inline void gen_evmergehilo (DisasContext *ctx)
6583 {
6584 if (unlikely(!ctx->spe_enabled)) {
6585 GEN_EXCP_NO_AP(ctx);
6586 return;
6587 }
6588 #if defined(TARGET_PPC64)
6589 TCGv t0 = tcg_temp_new();
6590 TCGv t1 = tcg_temp_new();
6591 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6592 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6593 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6594 tcg_temp_free(t0);
6595 tcg_temp_free(t1);
6596 #else
6597 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6598 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6599 #endif
6600 }
6601 static always_inline void gen_evmergelohi (DisasContext *ctx)
6602 {
6603 if (unlikely(!ctx->spe_enabled)) {
6604 GEN_EXCP_NO_AP(ctx);
6605 return;
6606 }
6607 #if defined(TARGET_PPC64)
6608 TCGv t0 = tcg_temp_new();
6609 TCGv t1 = tcg_temp_new();
6610 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6611 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6612 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6613 tcg_temp_free(t0);
6614 tcg_temp_free(t1);
6615 #else
6616 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6617 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6618 #endif
6619 }
6620 static always_inline void gen_evsplati (DisasContext *ctx)
6621 {
6622 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
6623
6624 #if defined(TARGET_PPC64)
6625 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6626 #else
6627 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6628 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6629 #endif
6630 }
6631 static always_inline void gen_evsplatfi (DisasContext *ctx)
6632 {
6633 uint64_t imm = rA(ctx->opcode) << 11;
6634
6635 #if defined(TARGET_PPC64)
6636 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6637 #else
6638 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6639 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6640 #endif
6641 }
6642
6643 static always_inline void gen_evsel (DisasContext *ctx)
6644 {
6645 int l1 = gen_new_label();
6646 int l2 = gen_new_label();
6647 int l3 = gen_new_label();
6648 int l4 = gen_new_label();
6649 TCGv_i32 t0 = tcg_temp_local_new_i32();
6650 #if defined(TARGET_PPC64)
6651 TCGv t1 = tcg_temp_local_new();
6652 TCGv t2 = tcg_temp_local_new();
6653 #endif
6654 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6655 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6656 #if defined(TARGET_PPC64)
6657 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6658 #else
6659 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6660 #endif
6661 tcg_gen_br(l2);
6662 gen_set_label(l1);
6663 #if defined(TARGET_PPC64)
6664 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6665 #else
6666 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6667 #endif
6668 gen_set_label(l2);
6669 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6670 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6671 #if defined(TARGET_PPC64)
6672 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6673 #else
6674 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6675 #endif
6676 tcg_gen_br(l4);
6677 gen_set_label(l3);
6678 #if defined(TARGET_PPC64)
6679 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6680 #else
6681 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6682 #endif
6683 gen_set_label(l4);
6684 tcg_temp_free_i32(t0);
6685 #if defined(TARGET_PPC64)
6686 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6687 tcg_temp_free(t1);
6688 tcg_temp_free(t2);
6689 #endif
6690 }
6691 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6692 {
6693 gen_evsel(ctx);
6694 }
6695 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6696 {
6697 gen_evsel(ctx);
6698 }
6699 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6700 {
6701 gen_evsel(ctx);
6702 }
6703 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6704 {
6705 gen_evsel(ctx);
6706 }
6707
6708 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6709 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6710 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6711 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6712 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6713 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6714 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6715 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6716 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6717 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6718 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6719 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6720 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6721 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6722 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6723 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6724 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6725 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6726 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6727 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6728 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6729 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6730 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6731 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6732 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6733
6734 /* SPE load and stores */
6735 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6736 {
6737 target_ulong uimm = rB(ctx->opcode);
6738
6739 if (rA(ctx->opcode) == 0) {
6740 tcg_gen_movi_tl(EA, uimm << sh);
6741 } else {
6742 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
6743 #if defined(TARGET_PPC64)
6744 if (!ctx->sf_mode) {
6745 tcg_gen_ext32u_tl(EA, EA);
6746 }
6747 #endif
6748 }
6749 }
6750
6751 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6752 {
6753 #if defined(TARGET_PPC64)
6754 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6755 #else
6756 TCGv_i64 t0 = tcg_temp_new_i64();
6757 gen_qemu_ld64(ctx, t0, addr);
6758 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6759 tcg_gen_shri_i64(t0, t0, 32);
6760 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6761 tcg_temp_free_i64(t0);
6762 #endif
6763 }
6764
6765 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6766 {
6767 #if defined(TARGET_PPC64)
6768 TCGv t0 = tcg_temp_new();
6769 gen_qemu_ld32u(ctx, t0, addr);
6770 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6771 gen_addr_add(ctx, addr, addr, 4);
6772 gen_qemu_ld32u(ctx, t0, addr);
6773 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6774 tcg_temp_free(t0);
6775 #else
6776 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
6777 gen_addr_add(ctx, addr, addr, 4);
6778 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6779 #endif
6780 }
6781
6782 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6783 {
6784 TCGv t0 = tcg_temp_new();
6785 #if defined(TARGET_PPC64)
6786 gen_qemu_ld16u(ctx, t0, addr);
6787 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6788 gen_addr_add(ctx, addr, addr, 2);
6789 gen_qemu_ld16u(ctx, t0, addr);
6790 tcg_gen_shli_tl(t0, t0, 32);
6791 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6792 gen_addr_add(ctx, addr, addr, 2);
6793 gen_qemu_ld16u(ctx, t0, addr);
6794 tcg_gen_shli_tl(t0, t0, 16);
6795 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6796 gen_addr_add(ctx, addr, addr, 2);
6797 gen_qemu_ld16u(ctx, t0, addr);
6798 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6799 #else
6800 gen_qemu_ld16u(ctx, t0, addr);
6801 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6802 gen_addr_add(ctx, addr, addr, 2);
6803 gen_qemu_ld16u(ctx, t0, addr);
6804 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6805 gen_addr_add(ctx, addr, addr, 2);
6806 gen_qemu_ld16u(ctx, t0, addr);
6807 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6808 gen_addr_add(ctx, addr, addr, 2);
6809 gen_qemu_ld16u(ctx, t0, addr);
6810 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6811 #endif
6812 tcg_temp_free(t0);
6813 }
6814
6815 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6816 {
6817 TCGv t0 = tcg_temp_new();
6818 gen_qemu_ld16u(ctx, t0, addr);
6819 #if defined(TARGET_PPC64)
6820 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6821 tcg_gen_shli_tl(t0, t0, 16);
6822 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6823 #else
6824 tcg_gen_shli_tl(t0, t0, 16);
6825 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6826 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6827 #endif
6828 tcg_temp_free(t0);
6829 }
6830
6831 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6832 {
6833 TCGv t0 = tcg_temp_new();
6834 gen_qemu_ld16u(ctx, t0, addr);
6835 #if defined(TARGET_PPC64)
6836 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6837 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6838 #else
6839 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6840 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6841 #endif
6842 tcg_temp_free(t0);
6843 }
6844
6845 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6846 {
6847 TCGv t0 = tcg_temp_new();
6848 gen_qemu_ld16s(ctx, t0, addr);
6849 #if defined(TARGET_PPC64)
6850 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6851 tcg_gen_ext32u_tl(t0, t0);
6852 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6853 #else
6854 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6855 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6856 #endif
6857 tcg_temp_free(t0);
6858 }
6859
6860 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6861 {
6862 TCGv t0 = tcg_temp_new();
6863 #if defined(TARGET_PPC64)
6864 gen_qemu_ld16u(ctx, t0, addr);
6865 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6866 gen_addr_add(ctx, addr, addr, 2);
6867 gen_qemu_ld16u(ctx, t0, addr);
6868 tcg_gen_shli_tl(t0, t0, 16);
6869 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6870 #else
6871 gen_qemu_ld16u(ctx, t0, addr);
6872 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6873 gen_addr_add(ctx, addr, addr, 2);
6874 gen_qemu_ld16u(ctx, t0, addr);
6875 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6876 #endif
6877 tcg_temp_free(t0);
6878 }
6879
6880 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6881 {
6882 #if defined(TARGET_PPC64)
6883 TCGv t0 = tcg_temp_new();
6884 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6885 gen_addr_add(ctx, addr, addr, 2);
6886 gen_qemu_ld16u(ctx, t0, addr);
6887 tcg_gen_shli_tl(t0, t0, 32);
6888 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6889 tcg_temp_free(t0);
6890 #else
6891 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
6892 gen_addr_add(ctx, addr, addr, 2);
6893 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6894 #endif
6895 }
6896
6897 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6898 {
6899 #if defined(TARGET_PPC64)
6900 TCGv t0 = tcg_temp_new();
6901 gen_qemu_ld16s(ctx, t0, addr);
6902 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6903 gen_addr_add(ctx, addr, addr, 2);
6904 gen_qemu_ld16s(ctx, t0, addr);
6905 tcg_gen_shli_tl(t0, t0, 32);
6906 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6907 tcg_temp_free(t0);
6908 #else
6909 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
6910 gen_addr_add(ctx, addr, addr, 2);
6911 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6912 #endif
6913 }
6914
6915 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6916 {
6917 TCGv t0 = tcg_temp_new();
6918 gen_qemu_ld32u(ctx, t0, addr);
6919 #if defined(TARGET_PPC64)
6920 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6921 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6922 #else
6923 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6924 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6925 #endif
6926 tcg_temp_free(t0);
6927 }
6928
6929 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6930 {
6931 TCGv t0 = tcg_temp_new();
6932 #if defined(TARGET_PPC64)
6933 gen_qemu_ld16u(ctx, t0, addr);
6934 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6935 tcg_gen_shli_tl(t0, t0, 32);
6936 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6937 gen_addr_add(ctx, addr, addr, 2);
6938 gen_qemu_ld16u(ctx, t0, addr);
6939 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6940 tcg_gen_shli_tl(t0, t0, 16);
6941 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6942 #else
6943 gen_qemu_ld16u(ctx, t0, addr);
6944 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6945 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6946 gen_addr_add(ctx, addr, addr, 2);
6947 gen_qemu_ld16u(ctx, t0, addr);
6948 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6949 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6950 #endif
6951 tcg_temp_free(t0);
6952 }
6953
6954 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6955 {
6956 #if defined(TARGET_PPC64)
6957 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6958 #else
6959 TCGv_i64 t0 = tcg_temp_new_i64();
6960 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6961 gen_qemu_st64(ctx, t0, addr);
6962 tcg_temp_free_i64(t0);
6963 #endif
6964 }
6965
6966 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6967 {
6968 #if defined(TARGET_PPC64)
6969 TCGv t0 = tcg_temp_new();
6970 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6971 gen_qemu_st32(ctx, t0, addr);
6972 tcg_temp_free(t0);
6973 #else
6974 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6975 #endif
6976 gen_addr_add(ctx, addr, addr, 4);
6977 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6978 }
6979
6980 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6981 {
6982 TCGv t0 = tcg_temp_new();
6983 #if defined(TARGET_PPC64)
6984 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6985 #else
6986 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6987 #endif
6988 gen_qemu_st16(ctx, t0, addr);
6989 gen_addr_add(ctx, addr, addr, 2);
6990 #if defined(TARGET_PPC64)
6991 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6992 gen_qemu_st16(ctx, t0, addr);
6993 #else
6994 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6995 #endif
6996 gen_addr_add(ctx, addr, addr, 2);
6997 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6998 gen_qemu_st16(ctx, t0, addr);
6999 tcg_temp_free(t0);
7000 gen_addr_add(ctx, addr, addr, 2);
7001 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7002 }
7003
7004 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7005 {
7006 TCGv t0 = tcg_temp_new();
7007 #if defined(TARGET_PPC64)
7008 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7009 #else
7010 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7011 #endif
7012 gen_qemu_st16(ctx, t0, addr);
7013 gen_addr_add(ctx, addr, addr, 2);
7014 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7015 gen_qemu_st16(ctx, t0, addr);
7016 tcg_temp_free(t0);
7017 }
7018
7019 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7020 {
7021 #if defined(TARGET_PPC64)
7022 TCGv t0 = tcg_temp_new();
7023 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7024 gen_qemu_st16(ctx, t0, addr);
7025 tcg_temp_free(t0);
7026 #else
7027 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7028 #endif
7029 gen_addr_add(ctx, addr, addr, 2);
7030 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7031 }
7032
7033 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7034 {
7035 #if defined(TARGET_PPC64)
7036 TCGv t0 = tcg_temp_new();
7037 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7038 gen_qemu_st32(ctx, t0, addr);
7039 tcg_temp_free(t0);
7040 #else
7041 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7042 #endif
7043 }
7044
7045 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7046 {
7047 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7048 }
7049
7050 #define GEN_SPEOP_LDST(name, opc2, sh) \
7051 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7052 { \
7053 TCGv t0; \
7054 if (unlikely(!ctx->spe_enabled)) { \
7055 GEN_EXCP_NO_AP(ctx); \
7056 return; \
7057 } \
7058 gen_set_access_type(ctx, ACCESS_INT); \
7059 t0 = tcg_temp_new(); \
7060 if (Rc(ctx->opcode)) { \
7061 gen_addr_spe_imm_index(ctx, t0, sh); \
7062 } else { \
7063 gen_addr_reg_index(ctx, t0); \
7064 } \
7065 gen_op_##name(ctx, t0); \
7066 tcg_temp_free(t0); \
7067 }
7068
7069 GEN_SPEOP_LDST(evldd, 0x00, 3);
7070 GEN_SPEOP_LDST(evldw, 0x01, 3);
7071 GEN_SPEOP_LDST(evldh, 0x02, 3);
7072 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7073 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7074 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7075 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7076 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7077 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7078 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7079 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7080
7081 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7082 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7083 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7084 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7085 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7086 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7087 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7088
7089 /* Multiply and add - TODO */
7090 #if 0
7091 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7092 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7093 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7094 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7095 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7096 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7097 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7098 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7099 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7100 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7101 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7102 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7103
7104 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7105 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7106 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7107 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7108 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7109 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7110 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7111 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7112 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7113 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7114 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7115 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7116 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7117 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7118
7119 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7120 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7121 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7122 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7123 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7124 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7125
7126 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7127 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7128 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7129 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7130 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7131 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7132 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7133 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7134 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7135 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7136 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7137 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7138
7139 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7140 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7141 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7142 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7143 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7144
7145 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7146 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7147 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7148 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7149 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7150 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7151 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7152 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7153 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7154 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7155 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7156 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7157
7158 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7159 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7160 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7161 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7162 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7163 #endif
7164
7165 /*** SPE floating-point extension ***/
7166 #if defined(TARGET_PPC64)
7167 #define GEN_SPEFPUOP_CONV_32_32(name) \
7168 static always_inline void gen_##name (DisasContext *ctx) \
7169 { \
7170 TCGv_i32 t0; \
7171 TCGv t1; \
7172 t0 = tcg_temp_new_i32(); \
7173 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7174 gen_helper_##name(t0, t0); \
7175 t1 = tcg_temp_new(); \
7176 tcg_gen_extu_i32_tl(t1, t0); \
7177 tcg_temp_free_i32(t0); \
7178 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7179 0xFFFFFFFF00000000ULL); \
7180 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7181 tcg_temp_free(t1); \
7182 }
7183 #define GEN_SPEFPUOP_CONV_32_64(name) \
7184 static always_inline void gen_##name (DisasContext *ctx) \
7185 { \
7186 TCGv_i32 t0; \
7187 TCGv t1; \
7188 t0 = tcg_temp_new_i32(); \
7189 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7190 t1 = tcg_temp_new(); \
7191 tcg_gen_extu_i32_tl(t1, t0); \
7192 tcg_temp_free_i32(t0); \
7193 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7194 0xFFFFFFFF00000000ULL); \
7195 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7196 tcg_temp_free(t1); \
7197 }
7198 #define GEN_SPEFPUOP_CONV_64_32(name) \
7199 static always_inline void gen_##name (DisasContext *ctx) \
7200 { \
7201 TCGv_i32 t0 = tcg_temp_new_i32(); \
7202 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7203 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7204 tcg_temp_free_i32(t0); \
7205 }
7206 #define GEN_SPEFPUOP_CONV_64_64(name) \
7207 static always_inline void gen_##name (DisasContext *ctx) \
7208 { \
7209 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7210 }
7211 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7212 static always_inline void gen_##name (DisasContext *ctx) \
7213 { \
7214 TCGv_i32 t0, t1; \
7215 TCGv_i64 t2; \
7216 if (unlikely(!ctx->spe_enabled)) { \
7217 GEN_EXCP_NO_AP(ctx); \
7218 return; \
7219 } \
7220 t0 = tcg_temp_new_i32(); \
7221 t1 = tcg_temp_new_i32(); \
7222 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7223 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7224 gen_helper_##name(t0, t0, t1); \
7225 tcg_temp_free_i32(t1); \
7226 t2 = tcg_temp_new(); \
7227 tcg_gen_extu_i32_tl(t2, t0); \
7228 tcg_temp_free_i32(t0); \
7229 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7230 0xFFFFFFFF00000000ULL); \
7231 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7232 tcg_temp_free(t2); \
7233 }
7234 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7235 static always_inline void gen_##name (DisasContext *ctx) \
7236 { \
7237 if (unlikely(!ctx->spe_enabled)) { \
7238 GEN_EXCP_NO_AP(ctx); \
7239 return; \
7240 } \
7241 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7242 cpu_gpr[rB(ctx->opcode)]); \
7243 }
7244 #define GEN_SPEFPUOP_COMP_32(name) \
7245 static always_inline void gen_##name (DisasContext *ctx) \
7246 { \
7247 TCGv_i32 t0, t1; \
7248 if (unlikely(!ctx->spe_enabled)) { \
7249 GEN_EXCP_NO_AP(ctx); \
7250 return; \
7251 } \
7252 t0 = tcg_temp_new_i32(); \
7253 t1 = tcg_temp_new_i32(); \
7254 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7255 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7256 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7257 tcg_temp_free_i32(t0); \
7258 tcg_temp_free_i32(t1); \
7259 }
7260 #define GEN_SPEFPUOP_COMP_64(name) \
7261 static always_inline void gen_##name (DisasContext *ctx) \
7262 { \
7263 if (unlikely(!ctx->spe_enabled)) { \
7264 GEN_EXCP_NO_AP(ctx); \
7265 return; \
7266 } \
7267 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7268 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7269 }
7270 #else
7271 #define GEN_SPEFPUOP_CONV_32_32(name) \
7272 static always_inline void gen_##name (DisasContext *ctx) \
7273 { \
7274 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7275 }
7276 #define GEN_SPEFPUOP_CONV_32_64(name) \
7277 static always_inline void gen_##name (DisasContext *ctx) \
7278 { \
7279 TCGv_i64 t0 = tcg_temp_new_i64(); \
7280 gen_load_gpr64(t0, rB(ctx->opcode)); \
7281 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7282 tcg_temp_free_i64(t0); \
7283 }
7284 #define GEN_SPEFPUOP_CONV_64_32(name) \
7285 static always_inline void gen_##name (DisasContext *ctx) \
7286 { \
7287 TCGv_i64 t0 = tcg_temp_new_i64(); \
7288 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7289 gen_store_gpr64(rD(ctx->opcode), t0); \
7290 tcg_temp_free_i64(t0); \
7291 }
7292 #define GEN_SPEFPUOP_CONV_64_64(name) \
7293 static always_inline void gen_##name (DisasContext *ctx) \
7294 { \
7295 TCGv_i64 t0 = tcg_temp_new_i64(); \
7296 gen_load_gpr64(t0, rB(ctx->opcode)); \
7297 gen_helper_##name(t0, t0); \
7298 gen_store_gpr64(rD(ctx->opcode), t0); \
7299 tcg_temp_free_i64(t0); \
7300 }
7301 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7302 static always_inline void gen_##name (DisasContext *ctx) \
7303 { \
7304 if (unlikely(!ctx->spe_enabled)) { \
7305 GEN_EXCP_NO_AP(ctx); \
7306 return; \
7307 } \
7308 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7309 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7310 }
7311 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7312 static always_inline void gen_##name (DisasContext *ctx) \
7313 { \
7314 TCGv_i64 t0, t1; \
7315 if (unlikely(!ctx->spe_enabled)) { \
7316 GEN_EXCP_NO_AP(ctx); \
7317 return; \
7318 } \
7319 t0 = tcg_temp_new_i64(); \
7320 t1 = tcg_temp_new_i64(); \
7321 gen_load_gpr64(t0, rA(ctx->opcode)); \
7322 gen_load_gpr64(t1, rB(ctx->opcode)); \
7323 gen_helper_##name(t0, t0, t1); \
7324 gen_store_gpr64(rD(ctx->opcode), t0); \
7325 tcg_temp_free_i64(t0); \
7326 tcg_temp_free_i64(t1); \
7327 }
7328 #define GEN_SPEFPUOP_COMP_32(name) \
7329 static always_inline void gen_##name (DisasContext *ctx) \
7330 { \
7331 if (unlikely(!ctx->spe_enabled)) { \
7332 GEN_EXCP_NO_AP(ctx); \
7333 return; \
7334 } \
7335 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7336 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7337 }
7338 #define GEN_SPEFPUOP_COMP_64(name) \
7339 static always_inline void gen_##name (DisasContext *ctx) \
7340 { \
7341 TCGv_i64 t0, t1; \
7342 if (unlikely(!ctx->spe_enabled)) { \
7343 GEN_EXCP_NO_AP(ctx); \
7344 return; \
7345 } \
7346 t0 = tcg_temp_new_i64(); \
7347 t1 = tcg_temp_new_i64(); \
7348 gen_load_gpr64(t0, rA(ctx->opcode)); \
7349 gen_load_gpr64(t1, rB(ctx->opcode)); \
7350 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7351 tcg_temp_free_i64(t0); \
7352 tcg_temp_free_i64(t1); \
7353 }
7354 #endif
7355
7356 /* Single precision floating-point vectors operations */
7357 /* Arithmetic */
7358 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7359 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7360 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7361 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7362 static always_inline void gen_evfsabs (DisasContext *ctx)
7363 {
7364 if (unlikely(!ctx->spe_enabled)) {
7365 GEN_EXCP_NO_AP(ctx);
7366 return;
7367 }
7368 #if defined(TARGET_PPC64)
7369 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7370 #else
7371 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7372 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7373 #endif
7374 }
7375 static always_inline void gen_evfsnabs (DisasContext *ctx)
7376 {
7377 if (unlikely(!ctx->spe_enabled)) {
7378 GEN_EXCP_NO_AP(ctx);
7379 return;
7380 }
7381 #if defined(TARGET_PPC64)
7382 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7383 #else
7384 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7385 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7386 #endif
7387 }
7388 static always_inline void gen_evfsneg (DisasContext *ctx)
7389 {
7390 if (unlikely(!ctx->spe_enabled)) {
7391 GEN_EXCP_NO_AP(ctx);
7392 return;
7393 }
7394 #if defined(TARGET_PPC64)
7395 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7396 #else
7397 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7398 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7399 #endif
7400 }
7401
7402 /* Conversion */
7403 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7404 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7405 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7406 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7407 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7408 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7409 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7410 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7411 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7412 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7413
7414 /* Comparison */
7415 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7416 GEN_SPEFPUOP_COMP_64(evfscmplt);
7417 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7418 GEN_SPEFPUOP_COMP_64(evfststgt);
7419 GEN_SPEFPUOP_COMP_64(evfststlt);
7420 GEN_SPEFPUOP_COMP_64(evfststeq);
7421
7422 /* Opcodes definitions */
7423 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7424 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7425 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7426 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7427 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7428 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7429 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7430 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7431 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7432 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7433 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7434 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7435 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7436 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7437
7438 /* Single precision floating-point operations */
7439 /* Arithmetic */
7440 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7441 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7442 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7443 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7444 static always_inline void gen_efsabs (DisasContext *ctx)
7445 {
7446 if (unlikely(!ctx->spe_enabled)) {
7447 GEN_EXCP_NO_AP(ctx);
7448 return;
7449 }
7450 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7451 }
7452 static always_inline void gen_efsnabs (DisasContext *ctx)
7453 {
7454 if (unlikely(!ctx->spe_enabled)) {
7455 GEN_EXCP_NO_AP(ctx);
7456 return;
7457 }
7458 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7459 }
7460 static always_inline void gen_efsneg (DisasContext *ctx)
7461 {
7462 if (unlikely(!ctx->spe_enabled)) {
7463 GEN_EXCP_NO_AP(ctx);
7464 return;
7465 }
7466 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7467 }
7468
7469 /* Conversion */
7470 GEN_SPEFPUOP_CONV_32_32(efscfui);
7471 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7472 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7473 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7474 GEN_SPEFPUOP_CONV_32_32(efsctui);
7475 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7476 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7477 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7478 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7479 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7480 GEN_SPEFPUOP_CONV_32_64(efscfd);
7481
7482 /* Comparison */
7483 GEN_SPEFPUOP_COMP_32(efscmpgt);
7484 GEN_SPEFPUOP_COMP_32(efscmplt);
7485 GEN_SPEFPUOP_COMP_32(efscmpeq);
7486 GEN_SPEFPUOP_COMP_32(efststgt);
7487 GEN_SPEFPUOP_COMP_32(efststlt);
7488 GEN_SPEFPUOP_COMP_32(efststeq);
7489
7490 /* Opcodes definitions */
7491 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
7492 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7493 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7494 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7495 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7496 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7497 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7498 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7499 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7500 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7501 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7502 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
7503 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7504 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7505
7506 /* Double precision floating-point operations */
7507 /* Arithmetic */
7508 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7509 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7510 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7511 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7512 static always_inline void gen_efdabs (DisasContext *ctx)
7513 {
7514 if (unlikely(!ctx->spe_enabled)) {
7515 GEN_EXCP_NO_AP(ctx);
7516 return;
7517 }
7518 #if defined(TARGET_PPC64)
7519 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7520 #else
7521 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7522 #endif
7523 }
7524 static always_inline void gen_efdnabs (DisasContext *ctx)
7525 {
7526 if (unlikely(!ctx->spe_enabled)) {
7527 GEN_EXCP_NO_AP(ctx);
7528 return;
7529 }
7530 #if defined(TARGET_PPC64)
7531 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7532 #else
7533 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7534 #endif
7535 }
7536 static always_inline void gen_efdneg (DisasContext *ctx)
7537 {
7538 if (unlikely(!ctx->spe_enabled)) {
7539 GEN_EXCP_NO_AP(ctx);
7540 return;
7541 }
7542 #if defined(TARGET_PPC64)
7543 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7544 #else
7545 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7546 #endif
7547 }
7548
7549 /* Conversion */
7550 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7551 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7552 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7553 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7554 GEN_SPEFPUOP_CONV_32_64(efdctui);
7555 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7556 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7557 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7558 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7559 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7560 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7561 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7562 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7563 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7564 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7565
7566 /* Comparison */
7567 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7568 GEN_SPEFPUOP_COMP_64(efdcmplt);
7569 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7570 GEN_SPEFPUOP_COMP_64(efdtstgt);
7571 GEN_SPEFPUOP_COMP_64(efdtstlt);
7572 GEN_SPEFPUOP_COMP_64(efdtsteq);
7573
7574 /* Opcodes definitions */
7575 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7576 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7577 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7578 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7579 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7580 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7581 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7582 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7583 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7584 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7585 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7586 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7587 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7588 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7589 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7590 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
7591
7592 /* End opcode list */
7593 GEN_OPCODE_MARK(end);
7594
7595 #include "translate_init.c"
7596 #include "helper_regs.h"
7597
7598 /*****************************************************************************/
7599 /* Misc PowerPC helpers */
7600 void cpu_dump_state (CPUState *env, FILE *f,
7601 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7602 int flags)
7603 {
7604 #define RGPL 4
7605 #define RFPL 4
7606
7607 int i;
7608
7609 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
7610 env->nip, env->lr, env->ctr, env->xer);
7611 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7612 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
7613 #if !defined(NO_TIMER_DUMP)
7614 cpu_fprintf(f, "TB %08x %08x "
7615 #if !defined(CONFIG_USER_ONLY)
7616 "DECR %08x"
7617 #endif
7618 "\n",
7619 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7620 #if !defined(CONFIG_USER_ONLY)
7621 , cpu_ppc_load_decr(env)
7622 #endif
7623 );
7624 #endif
7625 for (i = 0; i < 32; i++) {
7626 if ((i & (RGPL - 1)) == 0)
7627 cpu_fprintf(f, "GPR%02d", i);
7628 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
7629 if ((i & (RGPL - 1)) == (RGPL - 1))
7630 cpu_fprintf(f, "\n");
7631 }
7632 cpu_fprintf(f, "CR ");
7633 for (i = 0; i < 8; i++)
7634 cpu_fprintf(f, "%01x", env->crf[i]);
7635 cpu_fprintf(f, " [");
7636 for (i = 0; i < 8; i++) {
7637 char a = '-';
7638 if (env->crf[i] & 0x08)
7639 a = 'L';
7640 else if (env->crf[i] & 0x04)
7641 a = 'G';
7642 else if (env->crf[i] & 0x02)
7643 a = 'E';
7644 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7645 }
7646 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
7647 for (i = 0; i < 32; i++) {
7648 if ((i & (RFPL - 1)) == 0)
7649 cpu_fprintf(f, "FPR%02d", i);
7650 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7651 if ((i & (RFPL - 1)) == (RFPL - 1))
7652 cpu_fprintf(f, "\n");
7653 }
7654 #if !defined(CONFIG_USER_ONLY)
7655 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
7656 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
7657 #endif
7658
7659 #undef RGPL
7660 #undef RFPL
7661 }
7662
7663 void cpu_dump_statistics (CPUState *env, FILE*f,
7664 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7665 int flags)
7666 {
7667 #if defined(DO_PPC_STATISTICS)
7668 opc_handler_t **t1, **t2, **t3, *handler;
7669 int op1, op2, op3;
7670
7671 t1 = env->opcodes;
7672 for (op1 = 0; op1 < 64; op1++) {
7673 handler = t1[op1];
7674 if (is_indirect_opcode(handler)) {
7675 t2 = ind_table(handler);
7676 for (op2 = 0; op2 < 32; op2++) {
7677 handler = t2[op2];
7678 if (is_indirect_opcode(handler)) {
7679 t3 = ind_table(handler);
7680 for (op3 = 0; op3 < 32; op3++) {
7681 handler = t3[op3];
7682 if (handler->count == 0)
7683 continue;
7684 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7685 "%016llx %lld\n",
7686 op1, op2, op3, op1, (op3 << 5) | op2,
7687 handler->oname,
7688 handler->count, handler->count);
7689 }
7690 } else {
7691 if (handler->count == 0)
7692 continue;
7693 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7694 "%016llx %lld\n",
7695 op1, op2, op1, op2, handler->oname,
7696 handler->count, handler->count);
7697 }
7698 }
7699 } else {
7700 if (handler->count == 0)
7701 continue;
7702 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7703 op1, op1, handler->oname,
7704 handler->count, handler->count);
7705 }
7706 }
7707 #endif
7708 }
7709
7710 /*****************************************************************************/
7711 static always_inline void gen_intermediate_code_internal (CPUState *env,
7712 TranslationBlock *tb,
7713 int search_pc)
7714 {
7715 DisasContext ctx, *ctxp = &ctx;
7716 opc_handler_t **table, *handler;
7717 target_ulong pc_start;
7718 uint16_t *gen_opc_end;
7719 CPUBreakpoint *bp;
7720 int j, lj = -1;
7721 int num_insns;
7722 int max_insns;
7723
7724 pc_start = tb->pc;
7725 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7726 #if defined(OPTIMIZE_FPRF_UPDATE)
7727 gen_fprf_ptr = gen_fprf_buf;
7728 #endif
7729 ctx.nip = pc_start;
7730 ctx.tb = tb;
7731 ctx.exception = POWERPC_EXCP_NONE;
7732 ctx.spr_cb = env->spr_cb;
7733 ctx.mem_idx = env->mmu_idx;
7734 ctx.access_type = -1;
7735 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
7736 #if defined(TARGET_PPC64)
7737 ctx.sf_mode = msr_sf;
7738 #endif
7739 ctx.fpu_enabled = msr_fp;
7740 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7741 ctx.spe_enabled = msr_spe;
7742 else
7743 ctx.spe_enabled = 0;
7744 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7745 ctx.altivec_enabled = msr_vr;
7746 else
7747 ctx.altivec_enabled = 0;
7748 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7749 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7750 else
7751 ctx.singlestep_enabled = 0;
7752 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7753 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7754 if (unlikely(env->singlestep_enabled))
7755 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7756 #if defined (DO_SINGLE_STEP) && 0
7757 /* Single step trace mode */
7758 msr_se = 1;
7759 #endif
7760 num_insns = 0;
7761 max_insns = tb->cflags & CF_COUNT_MASK;
7762 if (max_insns == 0)
7763 max_insns = CF_COUNT_MASK;
7764
7765 gen_icount_start();
7766 /* Set env in case of segfault during code fetch */
7767 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
7768 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7769 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7770 if (bp->pc == ctx.nip) {
7771 gen_update_nip(&ctx, ctx.nip);
7772 gen_helper_raise_debug();
7773 break;
7774 }
7775 }
7776 }
7777 if (unlikely(search_pc)) {
7778 j = gen_opc_ptr - gen_opc_buf;
7779 if (lj < j) {
7780 lj++;
7781 while (lj < j)
7782 gen_opc_instr_start[lj++] = 0;
7783 gen_opc_pc[lj] = ctx.nip;
7784 gen_opc_instr_start[lj] = 1;
7785 gen_opc_icount[lj] = num_insns;
7786 }
7787 }
7788 #if defined PPC_DEBUG_DISAS
7789 if (loglevel & CPU_LOG_TB_IN_ASM) {
7790 fprintf(logfile, "----------------\n");
7791 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
7792 ctx.nip, ctx.mem_idx, (int)msr_ir);
7793 }
7794 #endif
7795 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7796 gen_io_start();
7797 if (unlikely(ctx.le_mode)) {
7798 ctx.opcode = bswap32(ldl_code(ctx.nip));
7799 } else {
7800 ctx.opcode = ldl_code(ctx.nip);
7801 }
7802 #if defined PPC_DEBUG_DISAS
7803 if (loglevel & CPU_LOG_TB_IN_ASM) {
7804 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
7805 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7806 opc3(ctx.opcode), little_endian ? "little" : "big");
7807 }
7808 #endif
7809 ctx.nip += 4;
7810 table = env->opcodes;
7811 num_insns++;
7812 handler = table[opc1(ctx.opcode)];
7813 if (is_indirect_opcode(handler)) {
7814 table = ind_table(handler);
7815 handler = table[opc2(ctx.opcode)];
7816 if (is_indirect_opcode(handler)) {
7817 table = ind_table(handler);
7818 handler = table[opc3(ctx.opcode)];
7819 }
7820 }
7821 /* Is opcode *REALLY* valid ? */
7822 if (unlikely(handler->handler == &gen_invalid)) {
7823 if (loglevel != 0) {
7824 fprintf(logfile, "invalid/unsupported opcode: "
7825 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7826 opc1(ctx.opcode), opc2(ctx.opcode),
7827 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7828 } else {
7829 printf("invalid/unsupported opcode: "
7830 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7831 opc1(ctx.opcode), opc2(ctx.opcode),
7832 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7833 }
7834 } else {
7835 if (unlikely((ctx.opcode & handler->inval) != 0)) {
7836 if (loglevel != 0) {
7837 fprintf(logfile, "invalid bits: %08x for opcode: "
7838 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7839 ctx.opcode & handler->inval, opc1(ctx.opcode),
7840 opc2(ctx.opcode), opc3(ctx.opcode),
7841 ctx.opcode, ctx.nip - 4);
7842 } else {
7843 printf("invalid bits: %08x for opcode: "
7844 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7845 ctx.opcode & handler->inval, opc1(ctx.opcode),
7846 opc2(ctx.opcode), opc3(ctx.opcode),
7847 ctx.opcode, ctx.nip - 4);
7848 }
7849 GEN_EXCP_INVAL(ctxp);
7850 break;
7851 }
7852 }
7853 (*(handler->handler))(&ctx);
7854 #if defined(DO_PPC_STATISTICS)
7855 handler->count++;
7856 #endif
7857 /* Check trace mode exceptions */
7858 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7859 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7860 ctx.exception != POWERPC_SYSCALL &&
7861 ctx.exception != POWERPC_EXCP_TRAP &&
7862 ctx.exception != POWERPC_EXCP_BRANCH)) {
7863 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
7864 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7865 (env->singlestep_enabled) ||
7866 num_insns >= max_insns)) {
7867 /* if we reach a page boundary or are single stepping, stop
7868 * generation
7869 */
7870 break;
7871 }
7872 #if defined (DO_SINGLE_STEP)
7873 break;
7874 #endif
7875 }
7876 if (tb->cflags & CF_LAST_IO)
7877 gen_io_end();
7878 if (ctx.exception == POWERPC_EXCP_NONE) {
7879 gen_goto_tb(&ctx, 0, ctx.nip);
7880 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7881 if (unlikely(env->singlestep_enabled)) {
7882 gen_update_nip(&ctx, ctx.nip);
7883 gen_helper_raise_debug();
7884 }
7885 /* Generate the return instruction */
7886 tcg_gen_exit_tb(0);
7887 }
7888 gen_icount_end(tb, num_insns);
7889 *gen_opc_ptr = INDEX_op_end;
7890 if (unlikely(search_pc)) {
7891 j = gen_opc_ptr - gen_opc_buf;
7892 lj++;
7893 while (lj <= j)
7894 gen_opc_instr_start[lj++] = 0;
7895 } else {
7896 tb->size = ctx.nip - pc_start;
7897 tb->icount = num_insns;
7898 }
7899 #if defined(DEBUG_DISAS)
7900 if (loglevel & CPU_LOG_TB_CPU) {
7901 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7902 cpu_dump_state(env, logfile, fprintf, 0);
7903 }
7904 if (loglevel & CPU_LOG_TB_IN_ASM) {
7905 int flags;
7906 flags = env->bfd_mach;
7907 flags |= ctx.le_mode << 16;
7908 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7909 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
7910 fprintf(logfile, "\n");
7911 }
7912 #endif
7913 }
7914
7915 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
7916 {
7917 gen_intermediate_code_internal(env, tb, 0);
7918 }
7919
7920 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
7921 {
7922 gen_intermediate_code_internal(env, tb, 1);
7923 }
7924
7925 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7926 unsigned long searched_pc, int pc_pos, void *puc)
7927 {
7928 env->nip = gen_opc_pc[pc_pos];
7929 }
SH4 target port of Qemu