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sh4/r2d: update pci, usb and kernel management
[qemu/sh4.git] / target-sparc / helper.c
blobf222e3a2c065d556b6c7cb5edd96e9f35d271e90
1 /*
2 * sparc helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "qemu-common.h"
31
32 //#define DEBUG_MMU
33 //#define DEBUG_FEATURES
34
35 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
36
37 /* Sparc MMU emulation */
38
39 /* thread support */
40
41 static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
42
43 void cpu_lock(void)
44 {
45 spin_lock(&global_cpu_lock);
46 }
47
48 void cpu_unlock(void)
49 {
50 spin_unlock(&global_cpu_lock);
51 }
52
53 #if defined(CONFIG_USER_ONLY)
54
55 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
56 int mmu_idx, int is_softmmu)
57 {
58 if (rw & 2)
59 env1->exception_index = TT_TFAULT;
60 else
61 env1->exception_index = TT_DFAULT;
62 return 1;
63 }
64
65 #else
66
67 #ifndef TARGET_SPARC64
68 /*
69 * Sparc V8 Reference MMU (SRMMU)
70 */
71 static const int access_table[8][8] = {
72 { 0, 0, 0, 0, 8, 0, 12, 12 },
73 { 0, 0, 0, 0, 8, 0, 0, 0 },
74 { 8, 8, 0, 0, 0, 8, 12, 12 },
75 { 8, 8, 0, 0, 0, 8, 0, 0 },
76 { 8, 0, 8, 0, 8, 8, 12, 12 },
77 { 8, 0, 8, 0, 8, 0, 8, 0 },
78 { 8, 8, 8, 0, 8, 8, 12, 12 },
79 { 8, 8, 8, 0, 8, 8, 8, 0 }
80 };
81
82 static const int perm_table[2][8] = {
83 {
84 PAGE_READ,
85 PAGE_READ | PAGE_WRITE,
86 PAGE_READ | PAGE_EXEC,
87 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
88 PAGE_EXEC,
89 PAGE_READ | PAGE_WRITE,
90 PAGE_READ | PAGE_EXEC,
91 PAGE_READ | PAGE_WRITE | PAGE_EXEC
92 },
93 {
94 PAGE_READ,
95 PAGE_READ | PAGE_WRITE,
96 PAGE_READ | PAGE_EXEC,
97 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
98 PAGE_EXEC,
99 PAGE_READ,
100 0,
101 0,
102 }
103 };
104
105 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
106 int *prot, int *access_index,
107 target_ulong address, int rw, int mmu_idx)
108 {
109 int access_perms = 0;
110 target_phys_addr_t pde_ptr;
111 uint32_t pde;
112 target_ulong virt_addr;
113 int error_code = 0, is_dirty, is_user;
114 unsigned long page_offset;
115
116 is_user = mmu_idx == MMU_USER_IDX;
117 virt_addr = address & TARGET_PAGE_MASK;
118
119 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
120 // Boot mode: instruction fetches are taken from PROM
121 if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
122 *physical = env->prom_addr | (address & 0x7ffffULL);
123 *prot = PAGE_READ | PAGE_EXEC;
124 return 0;
125 }
126 *physical = address;
127 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
128 return 0;
129 }
130
131 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
132 *physical = 0xffffffffffff0000ULL;
133
134 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
135 /* Context base + context number */
136 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
137 pde = ldl_phys(pde_ptr);
138
139 /* Ctx pde */
140 switch (pde & PTE_ENTRYTYPE_MASK) {
141 default:
142 case 0: /* Invalid */
143 return 1 << 2;
144 case 2: /* L0 PTE, maybe should not happen? */
145 case 3: /* Reserved */
146 return 4 << 2;
147 case 1: /* L0 PDE */
148 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
149 pde = ldl_phys(pde_ptr);
150
151 switch (pde & PTE_ENTRYTYPE_MASK) {
152 default:
153 case 0: /* Invalid */
154 return (1 << 8) | (1 << 2);
155 case 3: /* Reserved */
156 return (1 << 8) | (4 << 2);
157 case 1: /* L1 PDE */
158 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
159 pde = ldl_phys(pde_ptr);
160
161 switch (pde & PTE_ENTRYTYPE_MASK) {
162 default:
163 case 0: /* Invalid */
164 return (2 << 8) | (1 << 2);
165 case 3: /* Reserved */
166 return (2 << 8) | (4 << 2);
167 case 1: /* L2 PDE */
168 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
169 pde = ldl_phys(pde_ptr);
170
171 switch (pde & PTE_ENTRYTYPE_MASK) {
172 default:
173 case 0: /* Invalid */
174 return (3 << 8) | (1 << 2);
175 case 1: /* PDE, should not happen */
176 case 3: /* Reserved */
177 return (3 << 8) | (4 << 2);
178 case 2: /* L3 PTE */
179 virt_addr = address & TARGET_PAGE_MASK;
180 page_offset = (address & TARGET_PAGE_MASK) &
181 (TARGET_PAGE_SIZE - 1);
182 }
183 break;
184 case 2: /* L2 PTE */
185 virt_addr = address & ~0x3ffff;
186 page_offset = address & 0x3ffff;
187 }
188 break;
189 case 2: /* L1 PTE */
190 virt_addr = address & ~0xffffff;
191 page_offset = address & 0xffffff;
192 }
193 }
194
195 /* update page modified and dirty bits */
196 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
197 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
198 pde |= PG_ACCESSED_MASK;
199 if (is_dirty)
200 pde |= PG_MODIFIED_MASK;
201 stl_phys_notdirty(pde_ptr, pde);
202 }
203 /* check access */
204 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
205 error_code = access_table[*access_index][access_perms];
206 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
207 return error_code;
208
209 /* the page can be put in the TLB */
210 *prot = perm_table[is_user][access_perms];
211 if (!(pde & PG_MODIFIED_MASK)) {
212 /* only set write access if already dirty... otherwise wait
213 for dirty access */
214 *prot &= ~PAGE_WRITE;
215 }
216
217 /* Even if large ptes, we map only one 4KB page in the cache to
218 avoid filling it too fast */
219 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
220 return error_code;
221 }
222
223 /* Perform address translation */
224 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
225 int mmu_idx, int is_softmmu)
226 {
227 target_phys_addr_t paddr;
228 target_ulong vaddr;
229 int error_code = 0, prot, ret = 0, access_index;
230
231 error_code = get_physical_address(env, &paddr, &prot, &access_index,
232 address, rw, mmu_idx);
233 if (error_code == 0) {
234 vaddr = address & TARGET_PAGE_MASK;
235 paddr &= TARGET_PAGE_MASK;
236 #ifdef DEBUG_MMU
237 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
238 TARGET_FMT_lx "\n", address, paddr, vaddr);
239 #endif
240 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
241 return ret;
242 }
243
244 if (env->mmuregs[3]) /* Fault status register */
245 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
246 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
247 env->mmuregs[4] = address; /* Fault address register */
248
249 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
250 // No fault mode: if a mapping is available, just override
251 // permissions. If no mapping is available, redirect accesses to
252 // neverland. Fake/overridden mappings will be flushed when
253 // switching to normal mode.
254 vaddr = address & TARGET_PAGE_MASK;
255 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
256 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
257 return ret;
258 } else {
259 if (rw & 2)
260 env->exception_index = TT_TFAULT;
261 else
262 env->exception_index = TT_DFAULT;
263 return 1;
264 }
265 }
266
267 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
268 {
269 target_phys_addr_t pde_ptr;
270 uint32_t pde;
271
272 /* Context base + context number */
273 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
274 (env->mmuregs[2] << 2);
275 pde = ldl_phys(pde_ptr);
276
277 switch (pde & PTE_ENTRYTYPE_MASK) {
278 default:
279 case 0: /* Invalid */
280 case 2: /* PTE, maybe should not happen? */
281 case 3: /* Reserved */
282 return 0;
283 case 1: /* L1 PDE */
284 if (mmulev == 3)
285 return pde;
286 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
287 pde = ldl_phys(pde_ptr);
288
289 switch (pde & PTE_ENTRYTYPE_MASK) {
290 default:
291 case 0: /* Invalid */
292 case 3: /* Reserved */
293 return 0;
294 case 2: /* L1 PTE */
295 return pde;
296 case 1: /* L2 PDE */
297 if (mmulev == 2)
298 return pde;
299 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
300 pde = ldl_phys(pde_ptr);
301
302 switch (pde & PTE_ENTRYTYPE_MASK) {
303 default:
304 case 0: /* Invalid */
305 case 3: /* Reserved */
306 return 0;
307 case 2: /* L2 PTE */
308 return pde;
309 case 1: /* L3 PDE */
310 if (mmulev == 1)
311 return pde;
312 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
313 pde = ldl_phys(pde_ptr);
314
315 switch (pde & PTE_ENTRYTYPE_MASK) {
316 default:
317 case 0: /* Invalid */
318 case 1: /* PDE, should not happen */
319 case 3: /* Reserved */
320 return 0;
321 case 2: /* L3 PTE */
322 return pde;
323 }
324 }
325 }
326 }
327 return 0;
328 }
329
330 #ifdef DEBUG_MMU
331 void dump_mmu(CPUState *env)
332 {
333 target_ulong va, va1, va2;
334 unsigned int n, m, o;
335 target_phys_addr_t pde_ptr, pa;
336 uint32_t pde;
337
338 printf("MMU dump:\n");
339 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
340 pde = ldl_phys(pde_ptr);
341 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
342 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
343 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
344 pde = mmu_probe(env, va, 2);
345 if (pde) {
346 pa = cpu_get_phys_page_debug(env, va);
347 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
348 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
349 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
350 pde = mmu_probe(env, va1, 1);
351 if (pde) {
352 pa = cpu_get_phys_page_debug(env, va1);
353 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
354 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
355 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
356 pde = mmu_probe(env, va2, 0);
357 if (pde) {
358 pa = cpu_get_phys_page_debug(env, va2);
359 printf(" VA: " TARGET_FMT_lx ", PA: "
360 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
361 va2, pa, pde);
362 }
363 }
364 }
365 }
366 }
367 }
368 printf("MMU dump ends\n");
369 }
370 #endif /* DEBUG_MMU */
371
372 #else /* !TARGET_SPARC64 */
373 /*
374 * UltraSparc IIi I/DMMUs
375 */
376 static int get_physical_address_data(CPUState *env,
377 target_phys_addr_t *physical, int *prot,
378 target_ulong address, int rw, int is_user)
379 {
380 target_ulong mask;
381 unsigned int i;
382
383 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
384 *physical = address;
385 *prot = PAGE_READ | PAGE_WRITE;
386 return 0;
387 }
388
389 for (i = 0; i < 64; i++) {
390 switch ((env->dtlb_tte[i] >> 61) & 3) {
391 default:
392 case 0x0: // 8k
393 mask = 0xffffffffffffe000ULL;
394 break;
395 case 0x1: // 64k
396 mask = 0xffffffffffff0000ULL;
397 break;
398 case 0x2: // 512k
399 mask = 0xfffffffffff80000ULL;
400 break;
401 case 0x3: // 4M
402 mask = 0xffffffffffc00000ULL;
403 break;
404 }
405 // ctx match, vaddr match?
406 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
407 (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
408 // valid, access ok?
409 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
410 ((env->dtlb_tte[i] & 0x4) && is_user) ||
411 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
412 if (env->dmmuregs[3]) /* Fault status register */
413 env->dmmuregs[3] = 2; /* overflow (not read before
414 another fault) */
415 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
416 env->dmmuregs[4] = address; /* Fault address register */
417 env->exception_index = TT_DFAULT;
418 #ifdef DEBUG_MMU
419 printf("DFAULT at 0x%" PRIx64 "\n", address);
420 #endif
421 return 1;
422 }
423 *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
424 (address & ~mask & 0x1fffffff000ULL);
425 *prot = PAGE_READ;
426 if (env->dtlb_tte[i] & 0x2)
427 *prot |= PAGE_WRITE;
428 return 0;
429 }
430 }
431 #ifdef DEBUG_MMU
432 printf("DMISS at 0x%" PRIx64 "\n", address);
433 #endif
434 env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
435 env->exception_index = TT_DMISS;
436 return 1;
437 }
438
439 static int get_physical_address_code(CPUState *env,
440 target_phys_addr_t *physical, int *prot,
441 target_ulong address, int is_user)
442 {
443 target_ulong mask;
444 unsigned int i;
445
446 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
447 *physical = address;
448 *prot = PAGE_EXEC;
449 return 0;
450 }
451
452 for (i = 0; i < 64; i++) {
453 switch ((env->itlb_tte[i] >> 61) & 3) {
454 default:
455 case 0x0: // 8k
456 mask = 0xffffffffffffe000ULL;
457 break;
458 case 0x1: // 64k
459 mask = 0xffffffffffff0000ULL;
460 break;
461 case 0x2: // 512k
462 mask = 0xfffffffffff80000ULL;
463 break;
464 case 0x3: // 4M
465 mask = 0xffffffffffc00000ULL;
466 break;
467 }
468 // ctx match, vaddr match?
469 if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
470 (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
471 // valid, access ok?
472 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
473 ((env->itlb_tte[i] & 0x4) && is_user)) {
474 if (env->immuregs[3]) /* Fault status register */
475 env->immuregs[3] = 2; /* overflow (not read before
476 another fault) */
477 env->immuregs[3] |= (is_user << 3) | 1;
478 env->exception_index = TT_TFAULT;
479 #ifdef DEBUG_MMU
480 printf("TFAULT at 0x%" PRIx64 "\n", address);
481 #endif
482 return 1;
483 }
484 *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
485 (address & ~mask & 0x1fffffff000ULL);
486 *prot = PAGE_EXEC;
487 return 0;
488 }
489 }
490 #ifdef DEBUG_MMU
491 printf("TMISS at 0x%" PRIx64 "\n", address);
492 #endif
493 env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
494 env->exception_index = TT_TMISS;
495 return 1;
496 }
497
498 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
499 int *prot, int *access_index,
500 target_ulong address, int rw, int mmu_idx)
501 {
502 int is_user = mmu_idx == MMU_USER_IDX;
503
504 if (rw == 2)
505 return get_physical_address_code(env, physical, prot, address,
506 is_user);
507 else
508 return get_physical_address_data(env, physical, prot, address, rw,
509 is_user);
510 }
511
512 /* Perform address translation */
513 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
514 int mmu_idx, int is_softmmu)
515 {
516 target_ulong virt_addr, vaddr;
517 target_phys_addr_t paddr;
518 int error_code = 0, prot, ret = 0, access_index;
519
520 error_code = get_physical_address(env, &paddr, &prot, &access_index,
521 address, rw, mmu_idx);
522 if (error_code == 0) {
523 virt_addr = address & TARGET_PAGE_MASK;
524 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
525 (TARGET_PAGE_SIZE - 1));
526 #ifdef DEBUG_MMU
527 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
528 "\n", address, paddr, vaddr);
529 #endif
530 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
531 return ret;
532 }
533 // XXX
534 return 1;
535 }
536
537 #ifdef DEBUG_MMU
538 void dump_mmu(CPUState *env)
539 {
540 unsigned int i;
541 const char *mask;
542
543 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
544 env->dmmuregs[1], env->dmmuregs[2]);
545 if ((env->lsu & DMMU_E) == 0) {
546 printf("DMMU disabled\n");
547 } else {
548 printf("DMMU dump:\n");
549 for (i = 0; i < 64; i++) {
550 switch ((env->dtlb_tte[i] >> 61) & 3) {
551 default:
552 case 0x0:
553 mask = " 8k";
554 break;
555 case 0x1:
556 mask = " 64k";
557 break;
558 case 0x2:
559 mask = "512k";
560 break;
561 case 0x3:
562 mask = " 4M";
563 break;
564 }
565 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
566 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
567 ", %s, %s, %s, %s, ctx %" PRId64 "\n",
568 env->dtlb_tag[i] & ~0x1fffULL,
569 env->dtlb_tte[i] & 0x1ffffffe000ULL,
570 mask,
571 env->dtlb_tte[i] & 0x4? "priv": "user",
572 env->dtlb_tte[i] & 0x2? "RW": "RO",
573 env->dtlb_tte[i] & 0x40? "locked": "unlocked",
574 env->dtlb_tag[i] & 0x1fffULL);
575 }
576 }
577 }
578 if ((env->lsu & IMMU_E) == 0) {
579 printf("IMMU disabled\n");
580 } else {
581 printf("IMMU dump:\n");
582 for (i = 0; i < 64; i++) {
583 switch ((env->itlb_tte[i] >> 61) & 3) {
584 default:
585 case 0x0:
586 mask = " 8k";
587 break;
588 case 0x1:
589 mask = " 64k";
590 break;
591 case 0x2:
592 mask = "512k";
593 break;
594 case 0x3:
595 mask = " 4M";
596 break;
597 }
598 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
599 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
600 ", %s, %s, %s, ctx %" PRId64 "\n",
601 env->itlb_tag[i] & ~0x1fffULL,
602 env->itlb_tte[i] & 0x1ffffffe000ULL,
603 mask,
604 env->itlb_tte[i] & 0x4? "priv": "user",
605 env->itlb_tte[i] & 0x40? "locked": "unlocked",
606 env->itlb_tag[i] & 0x1fffULL);
607 }
608 }
609 }
610 }
611 #endif /* DEBUG_MMU */
612
613 #endif /* TARGET_SPARC64 */
614 #endif /* !CONFIG_USER_ONLY */
615
616
617 #if defined(CONFIG_USER_ONLY)
618 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
619 {
620 return addr;
621 }
622
623 #else
624 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
625 {
626 target_phys_addr_t phys_addr;
627 int prot, access_index;
628
629 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
630 MMU_KERNEL_IDX) != 0)
631 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
632 0, MMU_KERNEL_IDX) != 0)
633 return -1;
634 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
635 return -1;
636 return phys_addr;
637 }
638 #endif
639
640 void cpu_reset(CPUSPARCState *env)
641 {
642 tlb_flush(env, 1);
643 env->cwp = 0;
644 env->wim = 1;
645 env->regwptr = env->regbase + (env->cwp * 16);
646 #if defined(CONFIG_USER_ONLY)
647 env->user_mode_only = 1;
648 #ifdef TARGET_SPARC64
649 env->cleanwin = env->nwindows - 2;
650 env->cansave = env->nwindows - 2;
651 env->pstate = PS_RMO | PS_PEF | PS_IE;
652 env->asi = 0x82; // Primary no-fault
653 #endif
654 #else
655 env->psret = 0;
656 env->psrs = 1;
657 env->psrps = 1;
658 #ifdef TARGET_SPARC64
659 env->pstate = PS_PRIV;
660 env->hpstate = HS_PRIV;
661 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
662 #else
663 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
664 env->mmuregs[0] |= env->def->mmu_bm;
665 #endif
666 env->pc = 0;
667 env->npc = env->pc + 4;
668 #endif
669 }
670
671 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
672 {
673 sparc_def_t def1, *def = &def1;
674
675 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
676 return -1;
677
678 env->def = qemu_mallocz(sizeof(*def));
679 memcpy(env->def, def, sizeof(*def));
680 #if defined(CONFIG_USER_ONLY)
681 if ((env->def->features & CPU_FEATURE_FLOAT))
682 env->def->features |= CPU_FEATURE_FLOAT128;
683 #endif
684 env->cpu_model_str = cpu_model;
685 env->version = def->iu_version;
686 env->fsr = def->fpu_version;
687 env->nwindows = def->nwindows;
688 #if !defined(TARGET_SPARC64)
689 env->mmuregs[0] |= def->mmu_version;
690 cpu_sparc_set_id(env, 0);
691 #else
692 env->mmu_version = def->mmu_version;
693 env->maxtl = def->maxtl;
694 env->version |= def->maxtl << 8;
695 env->version |= def->nwindows - 1;
696 #endif
697 return 0;
698 }
699
700 static void cpu_sparc_close(CPUSPARCState *env)
701 {
702 free(env->def);
703 free(env);
704 }
705
706 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
707 {
708 CPUSPARCState *env;
709
710 env = qemu_mallocz(sizeof(CPUSPARCState));
711 if (!env)
712 return NULL;
713 cpu_exec_init(env);
714
715 gen_intermediate_code_init(env);
716
717 if (cpu_sparc_register(env, cpu_model) < 0) {
718 cpu_sparc_close(env);
719 return NULL;
720 }
721 cpu_reset(env);
722
723 return env;
724 }
725
726 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
727 {
728 #if !defined(TARGET_SPARC64)
729 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
730 #endif
731 }
732
733 static const sparc_def_t sparc_defs[] = {
734 #ifdef TARGET_SPARC64
735 {
736 .name = "Fujitsu Sparc64",
737 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
738 .fpu_version = 0x00000000,
739 .mmu_version = mmu_us_12,
740 .nwindows = 4,
741 .maxtl = 4,
742 .features = CPU_DEFAULT_FEATURES,
743 },
744 {
745 .name = "Fujitsu Sparc64 III",
746 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
747 .fpu_version = 0x00000000,
748 .mmu_version = mmu_us_12,
749 .nwindows = 5,
750 .maxtl = 4,
751 .features = CPU_DEFAULT_FEATURES,
752 },
753 {
754 .name = "Fujitsu Sparc64 IV",
755 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
756 .fpu_version = 0x00000000,
757 .mmu_version = mmu_us_12,
758 .nwindows = 8,
759 .maxtl = 5,
760 .features = CPU_DEFAULT_FEATURES,
761 },
762 {
763 .name = "Fujitsu Sparc64 V",
764 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
765 .fpu_version = 0x00000000,
766 .mmu_version = mmu_us_12,
767 .nwindows = 8,
768 .maxtl = 5,
769 .features = CPU_DEFAULT_FEATURES,
770 },
771 {
772 .name = "TI UltraSparc I",
773 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
774 .fpu_version = 0x00000000,
775 .mmu_version = mmu_us_12,
776 .nwindows = 8,
777 .maxtl = 5,
778 .features = CPU_DEFAULT_FEATURES,
779 },
780 {
781 .name = "TI UltraSparc II",
782 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
783 .fpu_version = 0x00000000,
784 .mmu_version = mmu_us_12,
785 .nwindows = 8,
786 .maxtl = 5,
787 .features = CPU_DEFAULT_FEATURES,
788 },
789 {
790 .name = "TI UltraSparc IIi",
791 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
792 .fpu_version = 0x00000000,
793 .mmu_version = mmu_us_12,
794 .nwindows = 8,
795 .maxtl = 5,
796 .features = CPU_DEFAULT_FEATURES,
797 },
798 {
799 .name = "TI UltraSparc IIe",
800 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
801 .fpu_version = 0x00000000,
802 .mmu_version = mmu_us_12,
803 .nwindows = 8,
804 .maxtl = 5,
805 .features = CPU_DEFAULT_FEATURES,
806 },
807 {
808 .name = "Sun UltraSparc III",
809 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
810 .fpu_version = 0x00000000,
811 .mmu_version = mmu_us_12,
812 .nwindows = 8,
813 .maxtl = 5,
814 .features = CPU_DEFAULT_FEATURES,
815 },
816 {
817 .name = "Sun UltraSparc III Cu",
818 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
819 .fpu_version = 0x00000000,
820 .mmu_version = mmu_us_3,
821 .nwindows = 8,
822 .maxtl = 5,
823 .features = CPU_DEFAULT_FEATURES,
824 },
825 {
826 .name = "Sun UltraSparc IIIi",
827 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
828 .fpu_version = 0x00000000,
829 .mmu_version = mmu_us_12,
830 .nwindows = 8,
831 .maxtl = 5,
832 .features = CPU_DEFAULT_FEATURES,
833 },
834 {
835 .name = "Sun UltraSparc IV",
836 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
837 .fpu_version = 0x00000000,
838 .mmu_version = mmu_us_4,
839 .nwindows = 8,
840 .maxtl = 5,
841 .features = CPU_DEFAULT_FEATURES,
842 },
843 {
844 .name = "Sun UltraSparc IV+",
845 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
846 .fpu_version = 0x00000000,
847 .mmu_version = mmu_us_12,
848 .nwindows = 8,
849 .maxtl = 5,
850 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
851 },
852 {
853 .name = "Sun UltraSparc IIIi+",
854 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
855 .fpu_version = 0x00000000,
856 .mmu_version = mmu_us_3,
857 .nwindows = 8,
858 .maxtl = 5,
859 .features = CPU_DEFAULT_FEATURES,
860 },
861 {
862 .name = "Sun UltraSparc T1",
863 // defined in sparc_ifu_fdp.v and ctu.h
864 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
865 .fpu_version = 0x00000000,
866 .mmu_version = mmu_sun4v,
867 .nwindows = 8,
868 .maxtl = 6,
869 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
870 | CPU_FEATURE_GL,
871 },
872 {
873 .name = "Sun UltraSparc T2",
874 // defined in tlu_asi_ctl.v and n2_revid_cust.v
875 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
876 .fpu_version = 0x00000000,
877 .mmu_version = mmu_sun4v,
878 .nwindows = 8,
879 .maxtl = 6,
880 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
881 | CPU_FEATURE_GL,
882 },
883 {
884 .name = "NEC UltraSparc I",
885 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
886 .fpu_version = 0x00000000,
887 .mmu_version = mmu_us_12,
888 .nwindows = 8,
889 .maxtl = 5,
890 .features = CPU_DEFAULT_FEATURES,
891 },
892 #else
893 {
894 .name = "Fujitsu MB86900",
895 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
896 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
897 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
898 .mmu_bm = 0x00004000,
899 .mmu_ctpr_mask = 0x007ffff0,
900 .mmu_cxr_mask = 0x0000003f,
901 .mmu_sfsr_mask = 0xffffffff,
902 .mmu_trcr_mask = 0xffffffff,
903 .nwindows = 7,
904 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
905 },
906 {
907 .name = "Fujitsu MB86904",
908 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
909 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
910 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
911 .mmu_bm = 0x00004000,
912 .mmu_ctpr_mask = 0x00ffffc0,
913 .mmu_cxr_mask = 0x000000ff,
914 .mmu_sfsr_mask = 0x00016fff,
915 .mmu_trcr_mask = 0x00ffffff,
916 .nwindows = 8,
917 .features = CPU_DEFAULT_FEATURES,
918 },
919 {
920 .name = "Fujitsu MB86907",
921 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
922 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
923 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
924 .mmu_bm = 0x00004000,
925 .mmu_ctpr_mask = 0xffffffc0,
926 .mmu_cxr_mask = 0x000000ff,
927 .mmu_sfsr_mask = 0x00016fff,
928 .mmu_trcr_mask = 0xffffffff,
929 .nwindows = 8,
930 .features = CPU_DEFAULT_FEATURES,
931 },
932 {
933 .name = "LSI L64811",
934 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
935 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
936 .mmu_version = 0x10 << 24,
937 .mmu_bm = 0x00004000,
938 .mmu_ctpr_mask = 0x007ffff0,
939 .mmu_cxr_mask = 0x0000003f,
940 .mmu_sfsr_mask = 0xffffffff,
941 .mmu_trcr_mask = 0xffffffff,
942 .nwindows = 8,
943 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
944 CPU_FEATURE_FSMULD,
945 },
946 {
947 .name = "Cypress CY7C601",
948 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
949 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
950 .mmu_version = 0x10 << 24,
951 .mmu_bm = 0x00004000,
952 .mmu_ctpr_mask = 0x007ffff0,
953 .mmu_cxr_mask = 0x0000003f,
954 .mmu_sfsr_mask = 0xffffffff,
955 .mmu_trcr_mask = 0xffffffff,
956 .nwindows = 8,
957 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
958 CPU_FEATURE_FSMULD,
959 },
960 {
961 .name = "Cypress CY7C611",
962 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
963 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
964 .mmu_version = 0x10 << 24,
965 .mmu_bm = 0x00004000,
966 .mmu_ctpr_mask = 0x007ffff0,
967 .mmu_cxr_mask = 0x0000003f,
968 .mmu_sfsr_mask = 0xffffffff,
969 .mmu_trcr_mask = 0xffffffff,
970 .nwindows = 8,
971 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
972 CPU_FEATURE_FSMULD,
973 },
974 {
975 .name = "TI SuperSparc II",
976 .iu_version = 0x40000000,
977 .fpu_version = 0 << 17,
978 .mmu_version = 0x04000000,
979 .mmu_bm = 0x00002000,
980 .mmu_ctpr_mask = 0xffffffc0,
981 .mmu_cxr_mask = 0x0000ffff,
982 .mmu_sfsr_mask = 0xffffffff,
983 .mmu_trcr_mask = 0xffffffff,
984 .nwindows = 8,
985 .features = CPU_DEFAULT_FEATURES,
986 },
987 {
988 .name = "TI MicroSparc I",
989 .iu_version = 0x41000000,
990 .fpu_version = 4 << 17,
991 .mmu_version = 0x41000000,
992 .mmu_bm = 0x00004000,
993 .mmu_ctpr_mask = 0x007ffff0,
994 .mmu_cxr_mask = 0x0000003f,
995 .mmu_sfsr_mask = 0x00016fff,
996 .mmu_trcr_mask = 0x0000003f,
997 .nwindows = 7,
998 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
999 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
1000 CPU_FEATURE_FMUL,
1001 },
1002 {
1003 .name = "TI MicroSparc II",
1004 .iu_version = 0x42000000,
1005 .fpu_version = 4 << 17,
1006 .mmu_version = 0x02000000,
1007 .mmu_bm = 0x00004000,
1008 .mmu_ctpr_mask = 0x00ffffc0,
1009 .mmu_cxr_mask = 0x000000ff,
1010 .mmu_sfsr_mask = 0x00016fff,
1011 .mmu_trcr_mask = 0x00ffffff,
1012 .nwindows = 8,
1013 .features = CPU_DEFAULT_FEATURES,
1014 },
1015 {
1016 .name = "TI MicroSparc IIep",
1017 .iu_version = 0x42000000,
1018 .fpu_version = 4 << 17,
1019 .mmu_version = 0x04000000,
1020 .mmu_bm = 0x00004000,
1021 .mmu_ctpr_mask = 0x00ffffc0,
1022 .mmu_cxr_mask = 0x000000ff,
1023 .mmu_sfsr_mask = 0x00016bff,
1024 .mmu_trcr_mask = 0x00ffffff,
1025 .nwindows = 8,
1026 .features = CPU_DEFAULT_FEATURES,
1027 },
1028 {
1029 .name = "TI SuperSparc 40", // STP1020NPGA
1030 .iu_version = 0x41000000,
1031 .fpu_version = 0 << 17,
1032 .mmu_version = 0x00000000,
1033 .mmu_bm = 0x00002000,
1034 .mmu_ctpr_mask = 0xffffffc0,
1035 .mmu_cxr_mask = 0x0000ffff,
1036 .mmu_sfsr_mask = 0xffffffff,
1037 .mmu_trcr_mask = 0xffffffff,
1038 .nwindows = 8,
1039 .features = CPU_DEFAULT_FEATURES,
1040 },
1041 {
1042 .name = "TI SuperSparc 50", // STP1020PGA
1043 .iu_version = 0x40000000,
1044 .fpu_version = 0 << 17,
1045 .mmu_version = 0x04000000,
1046 .mmu_bm = 0x00002000,
1047 .mmu_ctpr_mask = 0xffffffc0,
1048 .mmu_cxr_mask = 0x0000ffff,
1049 .mmu_sfsr_mask = 0xffffffff,
1050 .mmu_trcr_mask = 0xffffffff,
1051 .nwindows = 8,
1052 .features = CPU_DEFAULT_FEATURES,
1053 },
1054 {
1055 .name = "TI SuperSparc 51",
1056 .iu_version = 0x43000000,
1057 .fpu_version = 0 << 17,
1058 .mmu_version = 0x04000000,
1059 .mmu_bm = 0x00002000,
1060 .mmu_ctpr_mask = 0xffffffc0,
1061 .mmu_cxr_mask = 0x0000ffff,
1062 .mmu_sfsr_mask = 0xffffffff,
1063 .mmu_trcr_mask = 0xffffffff,
1064 .nwindows = 8,
1065 .features = CPU_DEFAULT_FEATURES,
1066 },
1067 {
1068 .name = "TI SuperSparc 60", // STP1020APGA
1069 .iu_version = 0x40000000,
1070 .fpu_version = 0 << 17,
1071 .mmu_version = 0x03000000,
1072 .mmu_bm = 0x00002000,
1073 .mmu_ctpr_mask = 0xffffffc0,
1074 .mmu_cxr_mask = 0x0000ffff,
1075 .mmu_sfsr_mask = 0xffffffff,
1076 .mmu_trcr_mask = 0xffffffff,
1077 .nwindows = 8,
1078 .features = CPU_DEFAULT_FEATURES,
1079 },
1080 {
1081 .name = "TI SuperSparc 61",
1082 .iu_version = 0x44000000,
1083 .fpu_version = 0 << 17,
1084 .mmu_version = 0x04000000,
1085 .mmu_bm = 0x00002000,
1086 .mmu_ctpr_mask = 0xffffffc0,
1087 .mmu_cxr_mask = 0x0000ffff,
1088 .mmu_sfsr_mask = 0xffffffff,
1089 .mmu_trcr_mask = 0xffffffff,
1090 .nwindows = 8,
1091 .features = CPU_DEFAULT_FEATURES,
1092 },
1093 {
1094 .name = "Ross RT625",
1095 .iu_version = 0x1e000000,
1096 .fpu_version = 1 << 17,
1097 .mmu_version = 0x1e000000,
1098 .mmu_bm = 0x00004000,
1099 .mmu_ctpr_mask = 0x007ffff0,
1100 .mmu_cxr_mask = 0x0000003f,
1101 .mmu_sfsr_mask = 0xffffffff,
1102 .mmu_trcr_mask = 0xffffffff,
1103 .nwindows = 8,
1104 .features = CPU_DEFAULT_FEATURES,
1105 },
1106 {
1107 .name = "Ross RT620",
1108 .iu_version = 0x1f000000,
1109 .fpu_version = 1 << 17,
1110 .mmu_version = 0x1f000000,
1111 .mmu_bm = 0x00004000,
1112 .mmu_ctpr_mask = 0x007ffff0,
1113 .mmu_cxr_mask = 0x0000003f,
1114 .mmu_sfsr_mask = 0xffffffff,
1115 .mmu_trcr_mask = 0xffffffff,
1116 .nwindows = 8,
1117 .features = CPU_DEFAULT_FEATURES,
1118 },
1119 {
1120 .name = "BIT B5010",
1121 .iu_version = 0x20000000,
1122 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1123 .mmu_version = 0x20000000,
1124 .mmu_bm = 0x00004000,
1125 .mmu_ctpr_mask = 0x007ffff0,
1126 .mmu_cxr_mask = 0x0000003f,
1127 .mmu_sfsr_mask = 0xffffffff,
1128 .mmu_trcr_mask = 0xffffffff,
1129 .nwindows = 8,
1130 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1131 CPU_FEATURE_FSMULD,
1132 },
1133 {
1134 .name = "Matsushita MN10501",
1135 .iu_version = 0x50000000,
1136 .fpu_version = 0 << 17,
1137 .mmu_version = 0x50000000,
1138 .mmu_bm = 0x00004000,
1139 .mmu_ctpr_mask = 0x007ffff0,
1140 .mmu_cxr_mask = 0x0000003f,
1141 .mmu_sfsr_mask = 0xffffffff,
1142 .mmu_trcr_mask = 0xffffffff,
1143 .nwindows = 8,
1144 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1145 CPU_FEATURE_FSMULD,
1146 },
1147 {
1148 .name = "Weitek W8601",
1149 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1150 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1151 .mmu_version = 0x10 << 24,
1152 .mmu_bm = 0x00004000,
1153 .mmu_ctpr_mask = 0x007ffff0,
1154 .mmu_cxr_mask = 0x0000003f,
1155 .mmu_sfsr_mask = 0xffffffff,
1156 .mmu_trcr_mask = 0xffffffff,
1157 .nwindows = 8,
1158 .features = CPU_DEFAULT_FEATURES,
1159 },
1160 {
1161 .name = "LEON2",
1162 .iu_version = 0xf2000000,
1163 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1164 .mmu_version = 0xf2000000,
1165 .mmu_bm = 0x00004000,
1166 .mmu_ctpr_mask = 0x007ffff0,
1167 .mmu_cxr_mask = 0x0000003f,
1168 .mmu_sfsr_mask = 0xffffffff,
1169 .mmu_trcr_mask = 0xffffffff,
1170 .nwindows = 8,
1171 .features = CPU_DEFAULT_FEATURES,
1172 },
1173 {
1174 .name = "LEON3",
1175 .iu_version = 0xf3000000,
1176 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1177 .mmu_version = 0xf3000000,
1178 .mmu_bm = 0x00004000,
1179 .mmu_ctpr_mask = 0x007ffff0,
1180 .mmu_cxr_mask = 0x0000003f,
1181 .mmu_sfsr_mask = 0xffffffff,
1182 .mmu_trcr_mask = 0xffffffff,
1183 .nwindows = 8,
1184 .features = CPU_DEFAULT_FEATURES,
1185 },
1186 #endif
1187 };
1188
1189 static const char * const feature_name[] = {
1190 "float",
1191 "float128",
1192 "swap",
1193 "mul",
1194 "div",
1195 "flush",
1196 "fsqrt",
1197 "fmul",
1198 "vis1",
1199 "vis2",
1200 "fsmuld",
1201 "hypv",
1202 "cmt",
1203 "gl",
1204 };
1205
1206 static void print_features(FILE *f,
1207 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1208 uint32_t features, const char *prefix)
1209 {
1210 unsigned int i;
1211
1212 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1213 if (feature_name[i] && (features & (1 << i))) {
1214 if (prefix)
1215 (*cpu_fprintf)(f, "%s", prefix);
1216 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1217 }
1218 }
1219
1220 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1221 {
1222 unsigned int i;
1223
1224 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1225 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1226 *features |= 1 << i;
1227 return;
1228 }
1229 fprintf(stderr, "CPU feature %s not found\n", flagname);
1230 }
1231
1232 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1233 {
1234 unsigned int i;
1235 const sparc_def_t *def = NULL;
1236 char *s = strdup(cpu_model);
1237 char *featurestr, *name = strtok(s, ",");
1238 uint32_t plus_features = 0;
1239 uint32_t minus_features = 0;
1240 long long iu_version;
1241 uint32_t fpu_version, mmu_version, nwindows;
1242
1243 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1244 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1245 def = &sparc_defs[i];
1246 }
1247 }
1248 if (!def)
1249 goto error;
1250 memcpy(cpu_def, def, sizeof(*def));
1251
1252 featurestr = strtok(NULL, ",");
1253 while (featurestr) {
1254 char *val;
1255
1256 if (featurestr[0] == '+') {
1257 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1258 } else if (featurestr[0] == '-') {
1259 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1260 } else if ((val = strchr(featurestr, '='))) {
1261 *val = 0; val++;
1262 if (!strcmp(featurestr, "iu_version")) {
1263 char *err;
1264
1265 iu_version = strtoll(val, &err, 0);
1266 if (!*val || *err) {
1267 fprintf(stderr, "bad numerical value %s\n", val);
1268 goto error;
1269 }
1270 cpu_def->iu_version = iu_version;
1271 #ifdef DEBUG_FEATURES
1272 fprintf(stderr, "iu_version %llx\n", iu_version);
1273 #endif
1274 } else if (!strcmp(featurestr, "fpu_version")) {
1275 char *err;
1276
1277 fpu_version = strtol(val, &err, 0);
1278 if (!*val || *err) {
1279 fprintf(stderr, "bad numerical value %s\n", val);
1280 goto error;
1281 }
1282 cpu_def->fpu_version = fpu_version;
1283 #ifdef DEBUG_FEATURES
1284 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1285 #endif
1286 } else if (!strcmp(featurestr, "mmu_version")) {
1287 char *err;
1288
1289 mmu_version = strtol(val, &err, 0);
1290 if (!*val || *err) {
1291 fprintf(stderr, "bad numerical value %s\n", val);
1292 goto error;
1293 }
1294 cpu_def->mmu_version = mmu_version;
1295 #ifdef DEBUG_FEATURES
1296 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1297 #endif
1298 } else if (!strcmp(featurestr, "nwindows")) {
1299 char *err;
1300
1301 nwindows = strtol(val, &err, 0);
1302 if (!*val || *err || nwindows > MAX_NWINDOWS ||
1303 nwindows < MIN_NWINDOWS) {
1304 fprintf(stderr, "bad numerical value %s\n", val);
1305 goto error;
1306 }
1307 cpu_def->nwindows = nwindows;
1308 #ifdef DEBUG_FEATURES
1309 fprintf(stderr, "nwindows %d\n", nwindows);
1310 #endif
1311 } else {
1312 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1313 goto error;
1314 }
1315 } else {
1316 fprintf(stderr, "feature string `%s' not in format "
1317 "(+feature|-feature|feature=xyz)\n", featurestr);
1318 goto error;
1319 }
1320 featurestr = strtok(NULL, ",");
1321 }
1322 cpu_def->features |= plus_features;
1323 cpu_def->features &= ~minus_features;
1324 #ifdef DEBUG_FEATURES
1325 print_features(stderr, fprintf, cpu_def->features, NULL);
1326 #endif
1327 free(s);
1328 return 0;
1329
1330 error:
1331 free(s);
1332 return -1;
1333 }
1334
1335 void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1336 {
1337 unsigned int i;
1338
1339 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1340 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1341 sparc_defs[i].name,
1342 sparc_defs[i].iu_version,
1343 sparc_defs[i].fpu_version,
1344 sparc_defs[i].mmu_version,
1345 sparc_defs[i].nwindows);
1346 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1347 ~sparc_defs[i].features, "-");
1348 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1349 sparc_defs[i].features, "+");
1350 (*cpu_fprintf)(f, "\n");
1351 }
1352 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
1353 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
1354 (*cpu_fprintf)(f, "\n");
1355 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
1356 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
1357 (*cpu_fprintf)(f, "\n");
1358 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
1359 "fpu_version mmu_version nwindows\n");
1360 }
1361
1362 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1363
1364 void cpu_dump_state(CPUState *env, FILE *f,
1365 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1366 int flags)
1367 {
1368 int i, x;
1369
1370 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1371 env->npc);
1372 cpu_fprintf(f, "General Registers:\n");
1373 for (i = 0; i < 4; i++)
1374 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1375 cpu_fprintf(f, "\n");
1376 for (; i < 8; i++)
1377 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1378 cpu_fprintf(f, "\nCurrent Register Window:\n");
1379 for (x = 0; x < 3; x++) {
1380 for (i = 0; i < 4; i++)
1381 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1382 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1383 env->regwptr[i + x * 8]);
1384 cpu_fprintf(f, "\n");
1385 for (; i < 8; i++)
1386 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1387 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1388 env->regwptr[i + x * 8]);
1389 cpu_fprintf(f, "\n");
1390 }
1391 cpu_fprintf(f, "\nFloating Point Registers:\n");
1392 for (i = 0; i < 32; i++) {
1393 if ((i & 3) == 0)
1394 cpu_fprintf(f, "%%f%02d:", i);
1395 cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
1396 if ((i & 3) == 3)
1397 cpu_fprintf(f, "\n");
1398 }
1399 #ifdef TARGET_SPARC64
1400 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1401 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1402 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1403 "cleanwin %d cwp %d\n",
1404 env->cansave, env->canrestore, env->otherwin, env->wstate,
1405 env->cleanwin, env->nwindows - 1 - env->cwp);
1406 #else
1407 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1408 GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1409 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1410 env->psrs?'S':'-', env->psrps?'P':'-',
1411 env->psret?'E':'-', env->wim);
1412 #endif
1413 cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
1414 }
SH4 target port of Qemu