hw/vga-isa-mm.c

   1 /*
   2  * QEMU ISA MM VGA Emulator.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pc.h"
  27 #include "vga_int.h"
  28 #include "pixel_ops.h"
  29 #include "qemu-timer.h"
  30
  31 typedef struct ISAVGAMMState {
  32     VGACommonState vga;
  33     int it_shift;
  34 } ISAVGAMMState;
  35
  36 /* Memory mapped interface */
  37 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
  38 {
  39     ISAVGAMMState *s = opaque;
  40
  41     return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xff;
  42 }
  43
  44 static void vga_mm_writeb (void *opaque,
  45                            target_phys_addr_t addr, uint32_t value)
  46 {
  47     ISAVGAMMState *s = opaque;
  48
  49     vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
  50 }
  51
  52 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
  53 {
  54     ISAVGAMMState *s = opaque;
  55
  56     return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xffff;
  57 }
  58
  59 static void vga_mm_writew (void *opaque,
  60                            target_phys_addr_t addr, uint32_t value)
  61 {
  62     ISAVGAMMState *s = opaque;
  63
  64     vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
  65 }
  66
  67 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
  68 {
  69     ISAVGAMMState *s = opaque;
  70
  71     return vga_ioport_read(&s->vga, addr >> s->it_shift);
  72 }
  73
  74 static void vga_mm_writel (void *opaque,
  75                            target_phys_addr_t addr, uint32_t value)
  76 {
  77     ISAVGAMMState *s = opaque;
  78
  79     vga_ioport_write(&s->vga, addr >> s->it_shift, value);
  80 }
  81
  82 static CPUReadMemoryFunc * const vga_mm_read_ctrl[] = {
  83     &vga_mm_readb,
  84     &vga_mm_readw,
  85     &vga_mm_readl,
  86 };
  87
  88 static CPUWriteMemoryFunc * const vga_mm_write_ctrl[] = {
  89     &vga_mm_writeb,
  90     &vga_mm_writew,
  91     &vga_mm_writel,
  92 };
  93
  94 static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
  95                         target_phys_addr_t ctrl_base, int it_shift)
  96 {
  97     int s_ioport_ctrl, vga_io_memory;
  98
  99     s->it_shift = it_shift;
 100     s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s,
 101                                            DEVICE_NATIVE_ENDIAN);
 102     vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s,
 103                                            DEVICE_NATIVE_ENDIAN);
 104
 105     vmstate_register(NULL, 0, &vmstate_vga_common, s);
 106
 107     cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
 108     s->vga.bank_offset = 0;
 109     cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
 110     qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
 111 }
 112
 113 int isa_vga_mm_init(target_phys_addr_t vram_base,
 114                     target_phys_addr_t ctrl_base, int it_shift)
 115 {
 116     ISAVGAMMState *s;
 117
 118     s = qemu_mallocz(sizeof(*s));
 119
 120     vga_common_init(&s->vga, VGA_RAM_SIZE);
 121     vga_mm_init(s, vram_base, ctrl_base, it_shift);
 122
 123     s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
 124                                      s->vga.screen_dump, s->vga.text_update, s);
 125
 126     vga_init_vbe(&s->vga);
 127     return 0;
 128 }