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[qemu/umeq.git] / hw / usb-ehci.c
blob2b43895315f223359404ed3f3255b32f32707958
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw.h"
26 #include "qemu-timer.h"
27 #include "usb.h"
28 #include "pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
137 #define MAX_QH 100 // Max allowable queue heads in a chain
138
139 /* Internal periodic / asynchronous schedule state machine states
140 */
141 typedef enum {
142 EST_INACTIVE = 1000,
143 EST_ACTIVE,
144 EST_EXECUTING,
145 EST_SLEEPING,
146 /* The following states are internal to the state machine function
147 */
148 EST_WAITLISTHEAD,
149 EST_FETCHENTRY,
150 EST_FETCHQH,
151 EST_FETCHITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIQueue EHCIQueue;
338 typedef struct EHCIState EHCIState;
339
340 enum async_state {
341 EHCI_ASYNC_NONE = 0,
342 EHCI_ASYNC_INFLIGHT,
343 EHCI_ASYNC_FINISHED,
344 };
345
346 struct EHCIQueue {
347 EHCIState *ehci;
348 QTAILQ_ENTRY(EHCIQueue) next;
349 bool async_schedule;
350 uint32_t seen;
351 uint64_t ts;
352
353 /* cached data from guest - needs to be flushed
354 * when guest removes an entry (doorbell, handshake sequence)
355 */
356 EHCIqh qh; // copy of current QH (being worked on)
357 uint32_t qhaddr; // address QH read from
358 EHCIqtd qtd; // copy of current QTD (being worked on)
359 uint32_t qtdaddr; // address QTD read from
360
361 USBPacket packet;
362 QEMUSGList sgl;
363 int pid;
364 uint32_t tbytes;
365 enum async_state async;
366 int usb_status;
367 };
368
369 struct EHCIState {
370 PCIDevice dev;
371 USBBus bus;
372 qemu_irq irq;
373 target_phys_addr_t mem_base;
374 int mem;
375 int companion_count;
376
377 /* properties */
378 uint32_t freq;
379 uint32_t maxframes;
380
381 /*
382 * EHCI spec version 1.0 Section 2.3
383 * Host Controller Operational Registers
384 */
385 union {
386 uint8_t mmio[MMIO_SIZE];
387 struct {
388 uint8_t cap[OPREGBASE];
389 uint32_t usbcmd;
390 uint32_t usbsts;
391 uint32_t usbintr;
392 uint32_t frindex;
393 uint32_t ctrldssegment;
394 uint32_t periodiclistbase;
395 uint32_t asynclistaddr;
396 uint32_t notused[9];
397 uint32_t configflag;
398 uint32_t portsc[NB_PORTS];
399 };
400 };
401
402 /*
403 * Internal states, shadow registers, etc
404 */
405 uint32_t sofv;
406 QEMUTimer *frame_timer;
407 int attach_poll_counter;
408 int astate; // Current state in asynchronous schedule
409 int pstate; // Current state in periodic schedule
410 USBPort ports[NB_PORTS];
411 USBPort *companion_ports[NB_PORTS];
412 uint32_t usbsts_pending;
413 QTAILQ_HEAD(, EHCIQueue) queues;
414
415 uint32_t a_fetch_addr; // which address to look at next
416 uint32_t p_fetch_addr; // which address to look at next
417
418 USBPacket ipacket;
419 QEMUSGList isgl;
420 int isoch_pause;
421
422 uint64_t last_run_ns;
423 };
424
425 #define SET_LAST_RUN_CLOCK(s) \
426 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
427
428 /* nifty macros from Arnon's EHCI version */
429 #define get_field(data, field) \
430 (((data) & field##_MASK) >> field##_SH)
431
432 #define set_field(data, newval, field) do { \
433 uint32_t val = *data; \
434 val &= ~ field##_MASK; \
435 val |= ((newval) << field##_SH) & field##_MASK; \
436 *data = val; \
437 } while(0)
438
439 static const char *ehci_state_names[] = {
440 [ EST_INACTIVE ] = "INACTIVE",
441 [ EST_ACTIVE ] = "ACTIVE",
442 [ EST_EXECUTING ] = "EXECUTING",
443 [ EST_SLEEPING ] = "SLEEPING",
444 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
445 [ EST_FETCHENTRY ] = "FETCH ENTRY",
446 [ EST_FETCHQH ] = "FETCH QH",
447 [ EST_FETCHITD ] = "FETCH ITD",
448 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
449 [ EST_FETCHQTD ] = "FETCH QTD",
450 [ EST_EXECUTE ] = "EXECUTE",
451 [ EST_WRITEBACK ] = "WRITEBACK",
452 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
453 };
454
455 static const char *ehci_mmio_names[] = {
456 [ CAPLENGTH ] = "CAPLENGTH",
457 [ HCIVERSION ] = "HCIVERSION",
458 [ HCSPARAMS ] = "HCSPARAMS",
459 [ HCCPARAMS ] = "HCCPARAMS",
460 [ USBCMD ] = "USBCMD",
461 [ USBSTS ] = "USBSTS",
462 [ USBINTR ] = "USBINTR",
463 [ FRINDEX ] = "FRINDEX",
464 [ PERIODICLISTBASE ] = "P-LIST BASE",
465 [ ASYNCLISTADDR ] = "A-LIST ADDR",
466 [ PORTSC_BEGIN ] = "PORTSC #0",
467 [ PORTSC_BEGIN + 4] = "PORTSC #1",
468 [ PORTSC_BEGIN + 8] = "PORTSC #2",
469 [ PORTSC_BEGIN + 12] = "PORTSC #3",
470 [ CONFIGFLAG ] = "CONFIGFLAG",
471 };
472
473 static const char *nr2str(const char **n, size_t len, uint32_t nr)
474 {
475 if (nr < len && n[nr] != NULL) {
476 return n[nr];
477 } else {
478 return "unknown";
479 }
480 }
481
482 static const char *state2str(uint32_t state)
483 {
484 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
485 }
486
487 static const char *addr2str(target_phys_addr_t addr)
488 {
489 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
490 }
491
492 static void ehci_trace_usbsts(uint32_t mask, int state)
493 {
494 /* interrupts */
495 if (mask & USBSTS_INT) {
496 trace_usb_ehci_usbsts("INT", state);
497 }
498 if (mask & USBSTS_ERRINT) {
499 trace_usb_ehci_usbsts("ERRINT", state);
500 }
501 if (mask & USBSTS_PCD) {
502 trace_usb_ehci_usbsts("PCD", state);
503 }
504 if (mask & USBSTS_FLR) {
505 trace_usb_ehci_usbsts("FLR", state);
506 }
507 if (mask & USBSTS_HSE) {
508 trace_usb_ehci_usbsts("HSE", state);
509 }
510 if (mask & USBSTS_IAA) {
511 trace_usb_ehci_usbsts("IAA", state);
512 }
513
514 /* status */
515 if (mask & USBSTS_HALT) {
516 trace_usb_ehci_usbsts("HALT", state);
517 }
518 if (mask & USBSTS_REC) {
519 trace_usb_ehci_usbsts("REC", state);
520 }
521 if (mask & USBSTS_PSS) {
522 trace_usb_ehci_usbsts("PSS", state);
523 }
524 if (mask & USBSTS_ASS) {
525 trace_usb_ehci_usbsts("ASS", state);
526 }
527 }
528
529 static inline void ehci_set_usbsts(EHCIState *s, int mask)
530 {
531 if ((s->usbsts & mask) == mask) {
532 return;
533 }
534 ehci_trace_usbsts(mask, 1);
535 s->usbsts |= mask;
536 }
537
538 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
539 {
540 if ((s->usbsts & mask) == 0) {
541 return;
542 }
543 ehci_trace_usbsts(mask, 0);
544 s->usbsts &= ~mask;
545 }
546
547 static inline void ehci_set_interrupt(EHCIState *s, int intr)
548 {
549 int level = 0;
550
551 // TODO honour interrupt threshold requests
552
553 ehci_set_usbsts(s, intr);
554
555 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
556 level = 1;
557 }
558
559 qemu_set_irq(s->irq, level);
560 }
561
562 static inline void ehci_record_interrupt(EHCIState *s, int intr)
563 {
564 s->usbsts_pending |= intr;
565 }
566
567 static inline void ehci_commit_interrupt(EHCIState *s)
568 {
569 if (!s->usbsts_pending) {
570 return;
571 }
572 ehci_set_interrupt(s, s->usbsts_pending);
573 s->usbsts_pending = 0;
574 }
575
576 static void ehci_set_state(EHCIState *s, int async, int state)
577 {
578 if (async) {
579 trace_usb_ehci_state("async", state2str(state));
580 s->astate = state;
581 } else {
582 trace_usb_ehci_state("periodic", state2str(state));
583 s->pstate = state;
584 }
585 }
586
587 static int ehci_get_state(EHCIState *s, int async)
588 {
589 return async ? s->astate : s->pstate;
590 }
591
592 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
593 {
594 if (async) {
595 s->a_fetch_addr = addr;
596 } else {
597 s->p_fetch_addr = addr;
598 }
599 }
600
601 static int ehci_get_fetch_addr(EHCIState *s, int async)
602 {
603 return async ? s->a_fetch_addr : s->p_fetch_addr;
604 }
605
606 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
607 {
608 /* need three here due to argument count limits */
609 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
610 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
611 trace_usb_ehci_qh_fields(addr,
612 get_field(qh->epchar, QH_EPCHAR_RL),
613 get_field(qh->epchar, QH_EPCHAR_MPLEN),
614 get_field(qh->epchar, QH_EPCHAR_EPS),
615 get_field(qh->epchar, QH_EPCHAR_EP),
616 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
617 trace_usb_ehci_qh_bits(addr,
618 (bool)(qh->epchar & QH_EPCHAR_C),
619 (bool)(qh->epchar & QH_EPCHAR_H),
620 (bool)(qh->epchar & QH_EPCHAR_DTC),
621 (bool)(qh->epchar & QH_EPCHAR_I));
622 }
623
624 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
625 {
626 /* need three here due to argument count limits */
627 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
628 trace_usb_ehci_qtd_fields(addr,
629 get_field(qtd->token, QTD_TOKEN_TBYTES),
630 get_field(qtd->token, QTD_TOKEN_CPAGE),
631 get_field(qtd->token, QTD_TOKEN_CERR),
632 get_field(qtd->token, QTD_TOKEN_PID));
633 trace_usb_ehci_qtd_bits(addr,
634 (bool)(qtd->token & QTD_TOKEN_IOC),
635 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
636 (bool)(qtd->token & QTD_TOKEN_HALT),
637 (bool)(qtd->token & QTD_TOKEN_BABBLE),
638 (bool)(qtd->token & QTD_TOKEN_XACTERR));
639 }
640
641 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
642 {
643 trace_usb_ehci_itd(addr, itd->next,
644 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
645 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
646 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
647 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
648 }
649
650 /* queue management */
651
652 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
653 {
654 EHCIQueue *q;
655
656 q = qemu_mallocz(sizeof(*q));
657 q->ehci = ehci;
658 q->async_schedule = async;
659 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
660 trace_usb_ehci_queue_action(q, "alloc");
661 return q;
662 }
663
664 static void ehci_free_queue(EHCIQueue *q)
665 {
666 trace_usb_ehci_queue_action(q, "free");
667 if (q->async == EHCI_ASYNC_INFLIGHT) {
668 usb_cancel_packet(&q->packet);
669 }
670 QTAILQ_REMOVE(&q->ehci->queues, q, next);
671 qemu_free(q);
672 }
673
674 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
675 {
676 EHCIQueue *q;
677
678 QTAILQ_FOREACH(q, &ehci->queues, next) {
679 if (addr == q->qhaddr) {
680 return q;
681 }
682 }
683 return NULL;
684 }
685
686 static void ehci_queues_rip_unused(EHCIState *ehci)
687 {
688 EHCIQueue *q, *tmp;
689
690 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
691 if (q->seen) {
692 q->seen = 0;
693 q->ts = ehci->last_run_ns;
694 continue;
695 }
696 if (ehci->last_run_ns < q->ts + 250000000) {
697 /* allow 0.25 sec idle */
698 continue;
699 }
700 ehci_free_queue(q);
701 }
702 }
703
704 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev)
705 {
706 EHCIQueue *q, *tmp;
707
708 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
709 if (q->packet.owner != dev) {
710 continue;
711 }
712 ehci_free_queue(q);
713 }
714 }
715
716 static void ehci_queues_rip_all(EHCIState *ehci)
717 {
718 EHCIQueue *q, *tmp;
719
720 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
721 ehci_free_queue(q);
722 }
723 }
724
725 /* Attach or detach a device on root hub */
726
727 static void ehci_attach(USBPort *port)
728 {
729 EHCIState *s = port->opaque;
730 uint32_t *portsc = &s->portsc[port->index];
731
732 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
733
734 if (*portsc & PORTSC_POWNER) {
735 USBPort *companion = s->companion_ports[port->index];
736 companion->dev = port->dev;
737 companion->ops->attach(companion);
738 return;
739 }
740
741 *portsc |= PORTSC_CONNECT;
742 *portsc |= PORTSC_CSC;
743
744 ehci_set_interrupt(s, USBSTS_PCD);
745 }
746
747 static void ehci_detach(USBPort *port)
748 {
749 EHCIState *s = port->opaque;
750 uint32_t *portsc = &s->portsc[port->index];
751
752 trace_usb_ehci_port_detach(port->index);
753
754 if (*portsc & PORTSC_POWNER) {
755 USBPort *companion = s->companion_ports[port->index];
756 companion->ops->detach(companion);
757 companion->dev = NULL;
758 return;
759 }
760
761 ehci_queues_rip_device(s, port->dev);
762
763 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
764 *portsc |= PORTSC_CSC;
765
766 ehci_set_interrupt(s, USBSTS_PCD);
767 }
768
769 static void ehci_child_detach(USBPort *port, USBDevice *child)
770 {
771 EHCIState *s = port->opaque;
772 uint32_t portsc = s->portsc[port->index];
773
774 if (portsc & PORTSC_POWNER) {
775 USBPort *companion = s->companion_ports[port->index];
776 companion->ops->child_detach(companion, child);
777 companion->dev = NULL;
778 return;
779 }
780
781 ehci_queues_rip_device(s, child);
782 }
783
784 static void ehci_wakeup(USBPort *port)
785 {
786 EHCIState *s = port->opaque;
787 uint32_t portsc = s->portsc[port->index];
788
789 if (portsc & PORTSC_POWNER) {
790 USBPort *companion = s->companion_ports[port->index];
791 if (companion->ops->wakeup) {
792 companion->ops->wakeup(companion);
793 }
794 }
795 }
796
797 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
798 uint32_t portcount, uint32_t firstport)
799 {
800 EHCIState *s = container_of(bus, EHCIState, bus);
801 uint32_t i;
802
803 if (firstport + portcount > NB_PORTS) {
804 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
805 "firstport on masterbus");
806 error_printf_unless_qmp(
807 "firstport value of %u makes companion take ports %u - %u, which "
808 "is outside of the valid range of 0 - %u\n", firstport, firstport,
809 firstport + portcount - 1, NB_PORTS - 1);
810 return -1;
811 }
812
813 for (i = 0; i < portcount; i++) {
814 if (s->companion_ports[firstport + i]) {
815 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
816 "an USB masterbus");
817 error_printf_unless_qmp(
818 "port %u on masterbus %s already has a companion assigned\n",
819 firstport + i, bus->qbus.name);
820 return -1;
821 }
822 }
823
824 for (i = 0; i < portcount; i++) {
825 s->companion_ports[firstport + i] = ports[i];
826 s->ports[firstport + i].speedmask |=
827 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
828 /* Ensure devs attached before the initial reset go to the companion */
829 s->portsc[firstport + i] = PORTSC_POWNER;
830 }
831
832 s->companion_count++;
833 s->mmio[0x05] = (s->companion_count << 4) | portcount;
834
835 return 0;
836 }
837
838 /* 4.1 host controller initialization */
839 static void ehci_reset(void *opaque)
840 {
841 EHCIState *s = opaque;
842 int i;
843 USBDevice *devs[NB_PORTS];
844
845 trace_usb_ehci_reset();
846
847 /*
848 * Do the detach before touching portsc, so that it correctly gets send to
849 * us or to our companion based on PORTSC_POWNER before the reset.
850 */
851 for(i = 0; i < NB_PORTS; i++) {
852 devs[i] = s->ports[i].dev;
853 if (devs[i]) {
854 usb_attach(&s->ports[i], NULL);
855 }
856 }
857
858 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
859
860 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
861 s->usbsts = USBSTS_HALT;
862
863 s->astate = EST_INACTIVE;
864 s->pstate = EST_INACTIVE;
865 s->isoch_pause = -1;
866 s->attach_poll_counter = 0;
867
868 for(i = 0; i < NB_PORTS; i++) {
869 if (s->companion_ports[i]) {
870 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
871 } else {
872 s->portsc[i] = PORTSC_PPOWER;
873 }
874 if (devs[i]) {
875 usb_attach(&s->ports[i], devs[i]);
876 }
877 }
878 ehci_queues_rip_all(s);
879 }
880
881 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
882 {
883 EHCIState *s = ptr;
884 uint32_t val;
885
886 val = s->mmio[addr];
887
888 return val;
889 }
890
891 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
892 {
893 EHCIState *s = ptr;
894 uint32_t val;
895
896 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
897
898 return val;
899 }
900
901 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
902 {
903 EHCIState *s = ptr;
904 uint32_t val;
905
906 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
907 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
908
909 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
910 return val;
911 }
912
913 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
914 {
915 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
916 exit(1);
917 }
918
919 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
920 {
921 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
922 exit(1);
923 }
924
925 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
926 {
927 USBDevice *dev = s->ports[port].dev;
928 uint32_t *portsc = &s->portsc[port];
929 uint32_t orig;
930
931 if (s->companion_ports[port] == NULL)
932 return;
933
934 owner = owner & PORTSC_POWNER;
935 orig = *portsc & PORTSC_POWNER;
936
937 if (!(owner ^ orig)) {
938 return;
939 }
940
941 if (dev) {
942 usb_attach(&s->ports[port], NULL);
943 }
944
945 *portsc &= ~PORTSC_POWNER;
946 *portsc |= owner;
947
948 if (dev) {
949 usb_attach(&s->ports[port], dev);
950 }
951 }
952
953 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
954 {
955 uint32_t *portsc = &s->portsc[port];
956 USBDevice *dev = s->ports[port].dev;
957
958 /* Clear rwc bits */
959 *portsc &= ~(val & PORTSC_RWC_MASK);
960 /* The guest may clear, but not set the PED bit */
961 *portsc &= val | ~PORTSC_PED;
962 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
963 handle_port_owner_write(s, port, val);
964 /* And finally apply RO_MASK */
965 val &= PORTSC_RO_MASK;
966
967 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
968 trace_usb_ehci_port_reset(port, 1);
969 }
970
971 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
972 trace_usb_ehci_port_reset(port, 0);
973 if (dev) {
974 usb_attach(&s->ports[port], dev);
975 usb_send_msg(dev, USB_MSG_RESET);
976 *portsc &= ~PORTSC_CSC;
977 }
978
979 /*
980 * Table 2.16 Set the enable bit(and enable bit change) to indicate
981 * to SW that this port has a high speed device attached
982 */
983 if (dev && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
984 val |= PORTSC_PED;
985 }
986 }
987
988 *portsc &= ~PORTSC_RO_MASK;
989 *portsc |= val;
990 }
991
992 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
993 {
994 EHCIState *s = ptr;
995 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
996 uint32_t old = *mmio;
997 int i;
998
999 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1000
1001 /* Only aligned reads are allowed on OHCI */
1002 if (addr & 3) {
1003 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1004 TARGET_FMT_plx "\n", addr);
1005 return;
1006 }
1007
1008 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1009 handle_port_status_write(s, (addr-PORTSC)/4, val);
1010 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1011 return;
1012 }
1013
1014 if (addr < OPREGBASE) {
1015 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1016 TARGET_FMT_plx "\n", addr);
1017 return;
1018 }
1019
1020
1021 /* Do any register specific pre-write processing here. */
1022 switch(addr) {
1023 case USBCMD:
1024 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
1025 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1026 SET_LAST_RUN_CLOCK(s);
1027 ehci_clear_usbsts(s, USBSTS_HALT);
1028 }
1029
1030 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
1031 qemu_del_timer(s->frame_timer);
1032 // TODO - should finish out some stuff before setting halt
1033 ehci_set_usbsts(s, USBSTS_HALT);
1034 }
1035
1036 if (val & USBCMD_HCRESET) {
1037 ehci_reset(s);
1038 val &= ~USBCMD_HCRESET;
1039 }
1040
1041 /* not supporting dynamic frame list size at the moment */
1042 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1043 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1044 val & USBCMD_FLS);
1045 val &= ~USBCMD_FLS;
1046 }
1047 break;
1048
1049 case USBSTS:
1050 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
1051 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
1052 val = s->usbsts;
1053 ehci_set_interrupt(s, 0);
1054 break;
1055
1056 case USBINTR:
1057 val &= USBINTR_MASK;
1058 break;
1059
1060 case FRINDEX:
1061 s->sofv = val >> 3;
1062 break;
1063
1064 case CONFIGFLAG:
1065 val &= 0x1;
1066 if (val) {
1067 for(i = 0; i < NB_PORTS; i++)
1068 handle_port_owner_write(s, i, 0);
1069 }
1070 break;
1071
1072 case PERIODICLISTBASE:
1073 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1074 fprintf(stderr,
1075 "ehci: PERIODIC list base register set while periodic schedule\n"
1076 " is enabled and HC is enabled\n");
1077 }
1078 break;
1079
1080 case ASYNCLISTADDR:
1081 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1082 fprintf(stderr,
1083 "ehci: ASYNC list address register set while async schedule\n"
1084 " is enabled and HC is enabled\n");
1085 }
1086 break;
1087 }
1088
1089 *mmio = val;
1090 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1091 }
1092
1093
1094 // TODO : Put in common header file, duplication from usb-ohci.c
1095
1096 /* Get an array of dwords from main memory */
1097 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
1098 {
1099 int i;
1100
1101 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1102 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
1103 *buf = le32_to_cpu(*buf);
1104 }
1105
1106 return 1;
1107 }
1108
1109 /* Put an array of dwords in to main memory */
1110 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
1111 {
1112 int i;
1113
1114 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1115 uint32_t tmp = cpu_to_le32(*buf);
1116 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
1117 }
1118
1119 return 1;
1120 }
1121
1122 // 4.10.2
1123
1124 static int ehci_qh_do_overlay(EHCIQueue *q)
1125 {
1126 int i;
1127 int dtoggle;
1128 int ping;
1129 int eps;
1130 int reload;
1131
1132 // remember values in fields to preserve in qh after overlay
1133
1134 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1135 ping = q->qh.token & QTD_TOKEN_PING;
1136
1137 q->qh.current_qtd = q->qtdaddr;
1138 q->qh.next_qtd = q->qtd.next;
1139 q->qh.altnext_qtd = q->qtd.altnext;
1140 q->qh.token = q->qtd.token;
1141
1142
1143 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1144 if (eps == EHCI_QH_EPS_HIGH) {
1145 q->qh.token &= ~QTD_TOKEN_PING;
1146 q->qh.token |= ping;
1147 }
1148
1149 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1150 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1151
1152 for (i = 0; i < 5; i++) {
1153 q->qh.bufptr[i] = q->qtd.bufptr[i];
1154 }
1155
1156 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1157 // preserve QH DT bit
1158 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1159 q->qh.token |= dtoggle;
1160 }
1161
1162 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1163 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1164
1165 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1166
1167 return 0;
1168 }
1169
1170 static int ehci_init_transfer(EHCIQueue *q)
1171 {
1172 uint32_t cpage, offset, bytes, plen;
1173 target_phys_addr_t page;
1174
1175 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1176 bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1177 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1178 qemu_sglist_init(&q->sgl, 5);
1179
1180 while (bytes > 0) {
1181 if (cpage > 4) {
1182 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1183 return USB_RET_PROCERR;
1184 }
1185
1186 page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1187 page += offset;
1188 plen = bytes;
1189 if (plen > 4096 - offset) {
1190 plen = 4096 - offset;
1191 offset = 0;
1192 cpage++;
1193 }
1194
1195 qemu_sglist_add(&q->sgl, page, plen);
1196 bytes -= plen;
1197 }
1198 return 0;
1199 }
1200
1201 static void ehci_finish_transfer(EHCIQueue *q, int status)
1202 {
1203 uint32_t cpage, offset;
1204
1205 qemu_sglist_destroy(&q->sgl);
1206
1207 if (status > 0) {
1208 /* update cpage & offset */
1209 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1210 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1211
1212 offset += status;
1213 cpage += offset >> QTD_BUFPTR_SH;
1214 offset &= ~QTD_BUFPTR_MASK;
1215
1216 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1217 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1218 q->qh.bufptr[0] |= offset;
1219 }
1220 }
1221
1222 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1223 {
1224 EHCIQueue *q;
1225 EHCIState *s = port->opaque;
1226 uint32_t portsc = s->portsc[port->index];
1227
1228 if (portsc & PORTSC_POWNER) {
1229 USBPort *companion = s->companion_ports[port->index];
1230 companion->ops->complete(companion, packet);
1231 return;
1232 }
1233
1234 q = container_of(packet, EHCIQueue, packet);
1235 trace_usb_ehci_queue_action(q, "wakeup");
1236 assert(q->async == EHCI_ASYNC_INFLIGHT);
1237 q->async = EHCI_ASYNC_FINISHED;
1238 q->usb_status = packet->result;
1239 }
1240
1241 static void ehci_execute_complete(EHCIQueue *q)
1242 {
1243 int c_err, reload;
1244
1245 assert(q->async != EHCI_ASYNC_INFLIGHT);
1246 q->async = EHCI_ASYNC_NONE;
1247
1248 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1249 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1250
1251 if (q->usb_status < 0) {
1252 err:
1253 /* TO-DO: put this is in a function that can be invoked below as well */
1254 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1255 c_err--;
1256 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1257
1258 switch(q->usb_status) {
1259 case USB_RET_NODEV:
1260 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1261 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1262 break;
1263 case USB_RET_STALL:
1264 q->qh.token |= QTD_TOKEN_HALT;
1265 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1266 break;
1267 case USB_RET_NAK:
1268 /* 4.10.3 */
1269 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1270 if ((q->pid == USB_TOKEN_IN) && reload) {
1271 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1272 nakcnt--;
1273 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1274 } else if (!reload) {
1275 return;
1276 }
1277 break;
1278 case USB_RET_BABBLE:
1279 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1280 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1281 break;
1282 default:
1283 /* should not be triggerable */
1284 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1285 assert(0);
1286 break;
1287 }
1288 } else {
1289 // DPRINTF("Short packet condition\n");
1290 // TODO check 4.12 for splits
1291
1292 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1293 q->usb_status = USB_RET_BABBLE;
1294 goto err;
1295 }
1296
1297 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1298 q->tbytes -= q->usb_status;
1299 } else {
1300 q->tbytes = 0;
1301 }
1302
1303 DPRINTF("updating tbytes to %d\n", q->tbytes);
1304 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1305 }
1306 ehci_finish_transfer(q, q->usb_status);
1307 usb_packet_unmap(&q->packet);
1308
1309 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1310 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1311
1312 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1313 ehci_record_interrupt(q->ehci, USBSTS_INT);
1314 }
1315 }
1316
1317 // 4.10.3
1318
1319 static int ehci_execute(EHCIQueue *q)
1320 {
1321 USBPort *port;
1322 USBDevice *dev;
1323 int ret;
1324 int i;
1325 int endp;
1326 int devadr;
1327
1328 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1329 fprintf(stderr, "Attempting to execute inactive QH\n");
1330 return USB_RET_PROCERR;
1331 }
1332
1333 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1334 if (q->tbytes > BUFF_SIZE) {
1335 fprintf(stderr, "Request for more bytes than allowed\n");
1336 return USB_RET_PROCERR;
1337 }
1338
1339 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1340 switch(q->pid) {
1341 case 0: q->pid = USB_TOKEN_OUT; break;
1342 case 1: q->pid = USB_TOKEN_IN; break;
1343 case 2: q->pid = USB_TOKEN_SETUP; break;
1344 default: fprintf(stderr, "bad token\n"); break;
1345 }
1346
1347 if (ehci_init_transfer(q) != 0) {
1348 return USB_RET_PROCERR;
1349 }
1350
1351 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1352 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1353
1354 ret = USB_RET_NODEV;
1355
1356 usb_packet_setup(&q->packet, q->pid, devadr, endp);
1357 usb_packet_map(&q->packet, &q->sgl);
1358
1359 // TO-DO: associating device with ehci port
1360 for(i = 0; i < NB_PORTS; i++) {
1361 port = &q->ehci->ports[i];
1362 dev = port->dev;
1363
1364 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1365 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1366 i, q->ehci->portsc[i]);
1367 continue;
1368 }
1369
1370 ret = usb_handle_packet(dev, &q->packet);
1371
1372 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1373 "(total %d) endp %x ret %d\n",
1374 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1375 q->packet.iov.size, q->tbytes, endp, ret);
1376
1377 if (ret != USB_RET_NODEV) {
1378 break;
1379 }
1380 }
1381
1382 if (ret > BUFF_SIZE) {
1383 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1384 return USB_RET_PROCERR;
1385 }
1386
1387 return ret;
1388 }
1389
1390 /* 4.7.2
1391 */
1392
1393 static int ehci_process_itd(EHCIState *ehci,
1394 EHCIitd *itd)
1395 {
1396 USBPort *port;
1397 USBDevice *dev;
1398 int ret;
1399 uint32_t i, j, len, pid, dir, devaddr, endp;
1400 uint32_t pg, off, ptr1, ptr2, max, mult;
1401
1402 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1403 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1404 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1405 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1406 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1407
1408 for(i = 0; i < 8; i++) {
1409 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1410 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1411 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1412 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1413 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1414 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1415
1416 if (len > max * mult) {
1417 len = max * mult;
1418 }
1419
1420 if (len > BUFF_SIZE) {
1421 return USB_RET_PROCERR;
1422 }
1423
1424 qemu_sglist_init(&ehci->isgl, 2);
1425 if (off + len > 4096) {
1426 /* transfer crosses page border */
1427 uint32_t len2 = off + len - 4096;
1428 uint32_t len1 = len - len2;
1429 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1430 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1431 } else {
1432 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1433 }
1434
1435 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1436
1437 usb_packet_setup(&ehci->ipacket, pid, devaddr, endp);
1438 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1439
1440 ret = USB_RET_NODEV;
1441 for (j = 0; j < NB_PORTS; j++) {
1442 port = &ehci->ports[j];
1443 dev = port->dev;
1444
1445 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1446 continue;
1447 }
1448
1449 ret = usb_handle_packet(dev, &ehci->ipacket);
1450
1451 if (ret != USB_RET_NODEV) {
1452 break;
1453 }
1454 }
1455
1456 usb_packet_unmap(&ehci->ipacket);
1457 qemu_sglist_destroy(&ehci->isgl);
1458
1459 #if 0
1460 /* In isoch, there is no facility to indicate a NAK so let's
1461 * instead just complete a zero-byte transaction. Setting
1462 * DBERR seems too draconian.
1463 */
1464
1465 if (ret == USB_RET_NAK) {
1466 if (ehci->isoch_pause > 0) {
1467 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1468 ehci->isoch_pause--;
1469 return 0;
1470 } else if (ehci->isoch_pause == -1) {
1471 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1472 // Pause frindex for up to 50 msec waiting for data from
1473 // remote
1474 ehci->isoch_pause = 50;
1475 return 0;
1476 } else {
1477 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1478 ret = 0;
1479 }
1480 } else {
1481 DPRINTF("ISOCH: received ACK, clearing pause\n");
1482 ehci->isoch_pause = -1;
1483 }
1484 #else
1485 if (ret == USB_RET_NAK) {
1486 ret = 0;
1487 }
1488 #endif
1489
1490 if (ret >= 0) {
1491 if (!dir) {
1492 /* OUT */
1493 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1494 } else {
1495 /* IN */
1496 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1497 }
1498
1499 if (itd->transact[i] & ITD_XACT_IOC) {
1500 ehci_record_interrupt(ehci, USBSTS_INT);
1501 }
1502 }
1503 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1504 }
1505 }
1506 return 0;
1507 }
1508
1509 /* This state is the entry point for asynchronous schedule
1510 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1511 */
1512 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1513 {
1514 EHCIqh qh;
1515 int i = 0;
1516 int again = 0;
1517 uint32_t entry = ehci->asynclistaddr;
1518
1519 /* set reclamation flag at start event (4.8.6) */
1520 if (async) {
1521 ehci_set_usbsts(ehci, USBSTS_REC);
1522 }
1523
1524 ehci_queues_rip_unused(ehci);
1525
1526 /* Find the head of the list (4.9.1.1) */
1527 for(i = 0; i < MAX_QH; i++) {
1528 get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1529 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1530
1531 if (qh.epchar & QH_EPCHAR_H) {
1532 if (async) {
1533 entry |= (NLPTR_TYPE_QH << 1);
1534 }
1535
1536 ehci_set_fetch_addr(ehci, async, entry);
1537 ehci_set_state(ehci, async, EST_FETCHENTRY);
1538 again = 1;
1539 goto out;
1540 }
1541
1542 entry = qh.next;
1543 if (entry == ehci->asynclistaddr) {
1544 break;
1545 }
1546 }
1547
1548 /* no head found for list. */
1549
1550 ehci_set_state(ehci, async, EST_ACTIVE);
1551
1552 out:
1553 return again;
1554 }
1555
1556
1557 /* This state is the entry point for periodic schedule processing as
1558 * well as being a continuation state for async processing.
1559 */
1560 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1561 {
1562 int again = 0;
1563 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1564
1565 if (entry < 0x1000) {
1566 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1567 ehci_set_state(ehci, async, EST_ACTIVE);
1568 goto out;
1569 }
1570
1571 /* section 4.8, only QH in async schedule */
1572 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1573 fprintf(stderr, "non queue head request in async schedule\n");
1574 return -1;
1575 }
1576
1577 switch (NLPTR_TYPE_GET(entry)) {
1578 case NLPTR_TYPE_QH:
1579 ehci_set_state(ehci, async, EST_FETCHQH);
1580 again = 1;
1581 break;
1582
1583 case NLPTR_TYPE_ITD:
1584 ehci_set_state(ehci, async, EST_FETCHITD);
1585 again = 1;
1586 break;
1587
1588 default:
1589 // TODO: handle siTD and FSTN types
1590 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1591 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1592 return -1;
1593 }
1594
1595 out:
1596 return again;
1597 }
1598
1599 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1600 {
1601 uint32_t entry;
1602 EHCIQueue *q;
1603 int reload;
1604
1605 entry = ehci_get_fetch_addr(ehci, async);
1606 q = ehci_find_queue_by_qh(ehci, entry);
1607 if (NULL == q) {
1608 q = ehci_alloc_queue(ehci, async);
1609 }
1610 q->qhaddr = entry;
1611 q->seen++;
1612
1613 if (q->seen > 1) {
1614 /* we are going in circles -- stop processing */
1615 ehci_set_state(ehci, async, EST_ACTIVE);
1616 q = NULL;
1617 goto out;
1618 }
1619
1620 get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1621 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1622
1623 if (q->async == EHCI_ASYNC_INFLIGHT) {
1624 /* I/O still in progress -- skip queue */
1625 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1626 goto out;
1627 }
1628 if (q->async == EHCI_ASYNC_FINISHED) {
1629 /* I/O finished -- continue processing queue */
1630 trace_usb_ehci_queue_action(q, "resume");
1631 ehci_set_state(ehci, async, EST_EXECUTING);
1632 goto out;
1633 }
1634
1635 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1636
1637 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1638 if (ehci->usbsts & USBSTS_REC) {
1639 ehci_clear_usbsts(ehci, USBSTS_REC);
1640 } else {
1641 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1642 " - done processing\n", q->qhaddr);
1643 ehci_set_state(ehci, async, EST_ACTIVE);
1644 q = NULL;
1645 goto out;
1646 }
1647 }
1648
1649 #if EHCI_DEBUG
1650 if (q->qhaddr != q->qh.next) {
1651 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1652 q->qhaddr,
1653 q->qh.epchar & QH_EPCHAR_H,
1654 q->qh.token & QTD_TOKEN_HALT,
1655 q->qh.token & QTD_TOKEN_ACTIVE,
1656 q->qh.next);
1657 }
1658 #endif
1659
1660 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1661 if (reload) {
1662 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1663 }
1664
1665 if (q->qh.token & QTD_TOKEN_HALT) {
1666 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1667
1668 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1669 q->qtdaddr = q->qh.current_qtd;
1670 ehci_set_state(ehci, async, EST_FETCHQTD);
1671
1672 } else {
1673 /* EHCI spec version 1.0 Section 4.10.2 */
1674 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1675 }
1676
1677 out:
1678 return q;
1679 }
1680
1681 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1682 {
1683 uint32_t entry;
1684 EHCIitd itd;
1685
1686 assert(!async);
1687 entry = ehci_get_fetch_addr(ehci, async);
1688
1689 get_dwords(NLPTR_GET(entry),(uint32_t *) &itd,
1690 sizeof(EHCIitd) >> 2);
1691 ehci_trace_itd(ehci, entry, &itd);
1692
1693 if (ehci_process_itd(ehci, &itd) != 0) {
1694 return -1;
1695 }
1696
1697 put_dwords(NLPTR_GET(entry), (uint32_t *) &itd,
1698 sizeof(EHCIitd) >> 2);
1699 ehci_set_fetch_addr(ehci, async, itd.next);
1700 ehci_set_state(ehci, async, EST_FETCHENTRY);
1701
1702 return 1;
1703 }
1704
1705 /* Section 4.10.2 - paragraph 3 */
1706 static int ehci_state_advqueue(EHCIQueue *q, int async)
1707 {
1708 #if 0
1709 /* TO-DO: 4.10.2 - paragraph 2
1710 * if I-bit is set to 1 and QH is not active
1711 * go to horizontal QH
1712 */
1713 if (I-bit set) {
1714 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1715 goto out;
1716 }
1717 #endif
1718
1719 /*
1720 * want data and alt-next qTD is valid
1721 */
1722 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1723 (q->qh.altnext_qtd > 0x1000) &&
1724 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1725 q->qtdaddr = q->qh.altnext_qtd;
1726 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1727
1728 /*
1729 * next qTD is valid
1730 */
1731 } else if ((q->qh.next_qtd > 0x1000) &&
1732 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1733 q->qtdaddr = q->qh.next_qtd;
1734 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1735
1736 /*
1737 * no valid qTD, try next QH
1738 */
1739 } else {
1740 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1741 }
1742
1743 return 1;
1744 }
1745
1746 /* Section 4.10.2 - paragraph 4 */
1747 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1748 {
1749 int again = 0;
1750
1751 get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2);
1752 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1753
1754 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1755 ehci_set_state(q->ehci, async, EST_EXECUTE);
1756 again = 1;
1757 } else {
1758 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1759 again = 1;
1760 }
1761
1762 return again;
1763 }
1764
1765 static int ehci_state_horizqh(EHCIQueue *q, int async)
1766 {
1767 int again = 0;
1768
1769 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1770 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1771 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1772 again = 1;
1773 } else {
1774 ehci_set_state(q->ehci, async, EST_ACTIVE);
1775 }
1776
1777 return again;
1778 }
1779
1780 /*
1781 * Write the qh back to guest physical memory. This step isn't
1782 * in the EHCI spec but we need to do it since we don't share
1783 * physical memory with our guest VM.
1784 *
1785 * The first three dwords are read-only for the EHCI, so skip them
1786 * when writing back the qh.
1787 */
1788 static void ehci_flush_qh(EHCIQueue *q)
1789 {
1790 uint32_t *qh = (uint32_t *) &q->qh;
1791 uint32_t dwords = sizeof(EHCIqh) >> 2;
1792 uint32_t addr = NLPTR_GET(q->qhaddr);
1793
1794 put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1795 }
1796
1797 static int ehci_state_execute(EHCIQueue *q, int async)
1798 {
1799 int again = 0;
1800 int reload, nakcnt;
1801 int smask;
1802
1803 if (ehci_qh_do_overlay(q) != 0) {
1804 return -1;
1805 }
1806
1807 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1808
1809 if (!smask) {
1810 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1811 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1812 if (reload && !nakcnt) {
1813 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1814 again = 1;
1815 goto out;
1816 }
1817 }
1818
1819 // TODO verify enough time remains in the uframe as in 4.4.1.1
1820 // TODO write back ptr to async list when done or out of time
1821 // TODO Windows does not seem to ever set the MULT field
1822
1823 if (!async) {
1824 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1825 if (!transactCtr) {
1826 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1827 again = 1;
1828 goto out;
1829 }
1830 }
1831
1832 if (async) {
1833 ehci_set_usbsts(q->ehci, USBSTS_REC);
1834 }
1835
1836 q->usb_status = ehci_execute(q);
1837 if (q->usb_status == USB_RET_PROCERR) {
1838 again = -1;
1839 goto out;
1840 }
1841 if (q->usb_status == USB_RET_ASYNC) {
1842 ehci_flush_qh(q);
1843 trace_usb_ehci_queue_action(q, "suspend");
1844 q->async = EHCI_ASYNC_INFLIGHT;
1845 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1846 again = 1;
1847 goto out;
1848 }
1849
1850 ehci_set_state(q->ehci, async, EST_EXECUTING);
1851 again = 1;
1852
1853 out:
1854 return again;
1855 }
1856
1857 static int ehci_state_executing(EHCIQueue *q, int async)
1858 {
1859 int again = 0;
1860 int reload, nakcnt;
1861
1862 ehci_execute_complete(q);
1863 if (q->usb_status == USB_RET_ASYNC) {
1864 goto out;
1865 }
1866 if (q->usb_status == USB_RET_PROCERR) {
1867 again = -1;
1868 goto out;
1869 }
1870
1871 // 4.10.3
1872 if (!async) {
1873 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1874 transactCtr--;
1875 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1876 // 4.10.3, bottom of page 82, should exit this state when transaction
1877 // counter decrements to 0
1878 }
1879
1880 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1881 if (reload) {
1882 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1883 if (q->usb_status == USB_RET_NAK) {
1884 if (nakcnt) {
1885 nakcnt--;
1886 }
1887 } else {
1888 nakcnt = reload;
1889 }
1890 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1891 }
1892
1893 /* 4.10.5 */
1894 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1895 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1896 } else {
1897 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1898 }
1899
1900 again = 1;
1901
1902 out:
1903 ehci_flush_qh(q);
1904 return again;
1905 }
1906
1907
1908 static int ehci_state_writeback(EHCIQueue *q, int async)
1909 {
1910 int again = 0;
1911
1912 /* Write back the QTD from the QH area */
1913 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1914 put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd,
1915 sizeof(EHCIqtd) >> 2);
1916
1917 /*
1918 * EHCI specs say go horizontal here.
1919 *
1920 * We can also advance the queue here for performance reasons. We
1921 * need to take care to only take that shortcut in case we've
1922 * processed the qtd just written back without errors, i.e. halt
1923 * bit is clear.
1924 */
1925 if (q->qh.token & QTD_TOKEN_HALT) {
1926 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1927 again = 1;
1928 } else {
1929 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1930 again = 1;
1931 }
1932 return again;
1933 }
1934
1935 /*
1936 * This is the state machine that is common to both async and periodic
1937 */
1938
1939 static void ehci_advance_state(EHCIState *ehci,
1940 int async)
1941 {
1942 EHCIQueue *q = NULL;
1943 int again;
1944 int iter = 0;
1945
1946 do {
1947 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1948 iter++;
1949 /* if we are roaming a lot of QH without executing a qTD
1950 * something is wrong with the linked list. TO-DO: why is
1951 * this hack needed?
1952 */
1953 assert(iter < MAX_ITERATIONS);
1954 #if 0
1955 if (iter > MAX_ITERATIONS) {
1956 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1957 ehci_set_state(ehci, async, EST_ACTIVE);
1958 break;
1959 }
1960 #endif
1961 }
1962 switch(ehci_get_state(ehci, async)) {
1963 case EST_WAITLISTHEAD:
1964 again = ehci_state_waitlisthead(ehci, async);
1965 break;
1966
1967 case EST_FETCHENTRY:
1968 again = ehci_state_fetchentry(ehci, async);
1969 break;
1970
1971 case EST_FETCHQH:
1972 q = ehci_state_fetchqh(ehci, async);
1973 again = q ? 1 : 0;
1974 break;
1975
1976 case EST_FETCHITD:
1977 again = ehci_state_fetchitd(ehci, async);
1978 break;
1979
1980 case EST_ADVANCEQUEUE:
1981 again = ehci_state_advqueue(q, async);
1982 break;
1983
1984 case EST_FETCHQTD:
1985 again = ehci_state_fetchqtd(q, async);
1986 break;
1987
1988 case EST_HORIZONTALQH:
1989 again = ehci_state_horizqh(q, async);
1990 break;
1991
1992 case EST_EXECUTE:
1993 iter = 0;
1994 again = ehci_state_execute(q, async);
1995 break;
1996
1997 case EST_EXECUTING:
1998 assert(q != NULL);
1999 again = ehci_state_executing(q, async);
2000 break;
2001
2002 case EST_WRITEBACK:
2003 again = ehci_state_writeback(q, async);
2004 break;
2005
2006 default:
2007 fprintf(stderr, "Bad state!\n");
2008 again = -1;
2009 assert(0);
2010 break;
2011 }
2012
2013 if (again < 0) {
2014 fprintf(stderr, "processing error - resetting ehci HC\n");
2015 ehci_reset(ehci);
2016 again = 0;
2017 assert(0);
2018 }
2019 }
2020 while (again);
2021
2022 ehci_commit_interrupt(ehci);
2023 }
2024
2025 static void ehci_advance_async_state(EHCIState *ehci)
2026 {
2027 int async = 1;
2028
2029 switch(ehci_get_state(ehci, async)) {
2030 case EST_INACTIVE:
2031 if (!(ehci->usbcmd & USBCMD_ASE)) {
2032 break;
2033 }
2034 ehci_set_usbsts(ehci, USBSTS_ASS);
2035 ehci_set_state(ehci, async, EST_ACTIVE);
2036 // No break, fall through to ACTIVE
2037
2038 case EST_ACTIVE:
2039 if ( !(ehci->usbcmd & USBCMD_ASE)) {
2040 ehci_clear_usbsts(ehci, USBSTS_ASS);
2041 ehci_set_state(ehci, async, EST_INACTIVE);
2042 break;
2043 }
2044
2045 /* If the doorbell is set, the guest wants to make a change to the
2046 * schedule. The host controller needs to release cached data.
2047 * (section 4.8.2)
2048 */
2049 if (ehci->usbcmd & USBCMD_IAAD) {
2050 DPRINTF("ASYNC: doorbell request acknowledged\n");
2051 ehci->usbcmd &= ~USBCMD_IAAD;
2052 ehci_set_interrupt(ehci, USBSTS_IAA);
2053 break;
2054 }
2055
2056 /* make sure guest has acknowledged */
2057 /* TO-DO: is this really needed? */
2058 if (ehci->usbsts & USBSTS_IAA) {
2059 DPRINTF("IAA status bit still set.\n");
2060 break;
2061 }
2062
2063 /* check that address register has been set */
2064 if (ehci->asynclistaddr == 0) {
2065 break;
2066 }
2067
2068 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2069 ehci_advance_state(ehci, async);
2070 break;
2071
2072 default:
2073 /* this should only be due to a developer mistake */
2074 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2075 "Resetting to active\n", ehci->astate);
2076 assert(0);
2077 }
2078 }
2079
2080 static void ehci_advance_periodic_state(EHCIState *ehci)
2081 {
2082 uint32_t entry;
2083 uint32_t list;
2084 int async = 0;
2085
2086 // 4.6
2087
2088 switch(ehci_get_state(ehci, async)) {
2089 case EST_INACTIVE:
2090 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2091 ehci_set_usbsts(ehci, USBSTS_PSS);
2092 ehci_set_state(ehci, async, EST_ACTIVE);
2093 // No break, fall through to ACTIVE
2094 } else
2095 break;
2096
2097 case EST_ACTIVE:
2098 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2099 ehci_clear_usbsts(ehci, USBSTS_PSS);
2100 ehci_set_state(ehci, async, EST_INACTIVE);
2101 break;
2102 }
2103
2104 list = ehci->periodiclistbase & 0xfffff000;
2105 /* check that register has been set */
2106 if (list == 0) {
2107 break;
2108 }
2109 list |= ((ehci->frindex & 0x1ff8) >> 1);
2110
2111 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
2112 entry = le32_to_cpu(entry);
2113
2114 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2115 ehci->frindex / 8, list, entry);
2116 ehci_set_fetch_addr(ehci, async,entry);
2117 ehci_set_state(ehci, async, EST_FETCHENTRY);
2118 ehci_advance_state(ehci, async);
2119 break;
2120
2121 default:
2122 /* this should only be due to a developer mistake */
2123 fprintf(stderr, "ehci: Bad periodic state %d. "
2124 "Resetting to active\n", ehci->pstate);
2125 assert(0);
2126 }
2127 }
2128
2129 static void ehci_frame_timer(void *opaque)
2130 {
2131 EHCIState *ehci = opaque;
2132 int64_t expire_time, t_now;
2133 uint64_t ns_elapsed;
2134 int frames;
2135 int i;
2136 int skipped_frames = 0;
2137
2138 t_now = qemu_get_clock_ns(vm_clock);
2139 expire_time = t_now + (get_ticks_per_sec() / ehci->freq);
2140
2141 ns_elapsed = t_now - ehci->last_run_ns;
2142 frames = ns_elapsed / FRAME_TIMER_NS;
2143
2144 for (i = 0; i < frames; i++) {
2145 if ( !(ehci->usbsts & USBSTS_HALT)) {
2146 if (ehci->isoch_pause <= 0) {
2147 ehci->frindex += 8;
2148 }
2149
2150 if (ehci->frindex > 0x00001fff) {
2151 ehci->frindex = 0;
2152 ehci_set_interrupt(ehci, USBSTS_FLR);
2153 }
2154
2155 ehci->sofv = (ehci->frindex - 1) >> 3;
2156 ehci->sofv &= 0x000003ff;
2157 }
2158
2159 if (frames - i > ehci->maxframes) {
2160 skipped_frames++;
2161 } else {
2162 ehci_advance_periodic_state(ehci);
2163 }
2164
2165 ehci->last_run_ns += FRAME_TIMER_NS;
2166 }
2167
2168 #if 0
2169 if (skipped_frames) {
2170 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2171 }
2172 #endif
2173
2174 /* Async is not inside loop since it executes everything it can once
2175 * called
2176 */
2177 ehci_advance_async_state(ehci);
2178
2179 qemu_mod_timer(ehci->frame_timer, expire_time);
2180 }
2181
2182 static CPUReadMemoryFunc *ehci_readfn[3]={
2183 ehci_mem_readb,
2184 ehci_mem_readw,
2185 ehci_mem_readl
2186 };
2187
2188 static CPUWriteMemoryFunc *ehci_writefn[3]={
2189 ehci_mem_writeb,
2190 ehci_mem_writew,
2191 ehci_mem_writel
2192 };
2193
2194 static void ehci_map(PCIDevice *pci_dev, int region_num,
2195 pcibus_t addr, pcibus_t size, int type)
2196 {
2197 EHCIState *s =(EHCIState *)pci_dev;
2198
2199 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
2200 region_num, addr, size, s->mem);
2201 s->mem_base = addr;
2202 cpu_register_physical_memory(addr, size, s->mem);
2203 }
2204
2205 static int usb_ehci_initfn(PCIDevice *dev);
2206
2207 static USBPortOps ehci_port_ops = {
2208 .attach = ehci_attach,
2209 .detach = ehci_detach,
2210 .child_detach = ehci_child_detach,
2211 .wakeup = ehci_wakeup,
2212 .complete = ehci_async_complete_packet,
2213 };
2214
2215 static USBBusOps ehci_bus_ops = {
2216 .register_companion = ehci_register_companion,
2217 };
2218
2219 static const VMStateDescription vmstate_ehci = {
2220 .name = "ehci",
2221 .unmigratable = 1,
2222 };
2223
2224 static Property ehci_properties[] = {
2225 DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ),
2226 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2227 DEFINE_PROP_END_OF_LIST(),
2228 };
2229
2230 static PCIDeviceInfo ehci_info[] = {
2231 {
2232 .qdev.name = "usb-ehci",
2233 .qdev.size = sizeof(EHCIState),
2234 .qdev.vmsd = &vmstate_ehci,
2235 .init = usb_ehci_initfn,
2236 .vendor_id = PCI_VENDOR_ID_INTEL,
2237 .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */
2238 .revision = 0x10,
2239 .class_id = PCI_CLASS_SERIAL_USB,
2240 .qdev.props = ehci_properties,
2241 },{
2242 .qdev.name = "ich9-usb-ehci1",
2243 .qdev.size = sizeof(EHCIState),
2244 .qdev.vmsd = &vmstate_ehci,
2245 .init = usb_ehci_initfn,
2246 .vendor_id = PCI_VENDOR_ID_INTEL,
2247 .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1,
2248 .revision = 0x03,
2249 .class_id = PCI_CLASS_SERIAL_USB,
2250 .qdev.props = ehci_properties,
2251 },{
2252 /* end of list */
2253 }
2254 };
2255
2256 static int usb_ehci_initfn(PCIDevice *dev)
2257 {
2258 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2259 uint8_t *pci_conf = s->dev.config;
2260 int i;
2261
2262 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2263
2264 /* capabilities pointer */
2265 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2266 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2267
2268 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2269 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2270 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2271
2272 // pci_conf[0x50] = 0x01; // power management caps
2273
2274 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2275 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2276 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2277
2278 pci_conf[0x64] = 0x00;
2279 pci_conf[0x65] = 0x00;
2280 pci_conf[0x66] = 0x00;
2281 pci_conf[0x67] = 0x00;
2282 pci_conf[0x68] = 0x01;
2283 pci_conf[0x69] = 0x00;
2284 pci_conf[0x6a] = 0x00;
2285 pci_conf[0x6b] = 0x00; // USBLEGSUP
2286 pci_conf[0x6c] = 0x00;
2287 pci_conf[0x6d] = 0x00;
2288 pci_conf[0x6e] = 0x00;
2289 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2290
2291 // 2.2 host controller interface version
2292 s->mmio[0x00] = (uint8_t) OPREGBASE;
2293 s->mmio[0x01] = 0x00;
2294 s->mmio[0x02] = 0x00;
2295 s->mmio[0x03] = 0x01; // HC version
2296 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2297 s->mmio[0x05] = 0x00; // No companion ports at present
2298 s->mmio[0x06] = 0x00;
2299 s->mmio[0x07] = 0x00;
2300 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2301 s->mmio[0x09] = 0x68; // EECP
2302 s->mmio[0x0a] = 0x00;
2303 s->mmio[0x0b] = 0x00;
2304
2305 s->irq = s->dev.irq[3];
2306
2307 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2308 for(i = 0; i < NB_PORTS; i++) {
2309 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2310 USB_SPEED_MASK_HIGH);
2311 s->ports[i].dev = 0;
2312 }
2313
2314 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2315 QTAILQ_INIT(&s->queues);
2316
2317 qemu_register_reset(ehci_reset, s);
2318
2319 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2320 DEVICE_LITTLE_ENDIAN);
2321
2322 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2323 ehci_map);
2324
2325 fprintf(stderr, "*** EHCI support is under development ***\n");
2326
2327 return 0;
2328 }
2329
2330 static void ehci_register(void)
2331 {
2332 pci_qdev_register_many(ehci_info);
2333 }
2334 device_init(ehci_register);
2335
2336 /*
2337 * vim: expandtab ts=4
2338 */