Add i8042 back
[qemupp.git] / pci / pcidevice.cpp
blob5f8f623b7fa2bc038e6e9b7c56ff47cc0355dc93
1 class PCIDevice : public Device
3 public:
4 void rw_config(uint8_t addr, unsigned len, uint32_t *data, bool read);
6 protected:
7 uint16_t vendor_id;
8 uint16_t device_id;
9 uint16_t command;
10 uint16_t status;
11 uint8_t rid;
12 uint8_t prog_if;
13 uint8_t subclass_code;
14 uint8_t class_code;
15 uint8_t cls;
16 uint8_t mlt;
17 uint8_t headt;
18 uint8_t bist;
19 Array<uint32_t, 6> bar;
20 uint32_t ccp;
21 uint16_t subvendor_id;
22 uint16_t subdevice_id;
23 uint32_t rom_bar;
24 uint8_t cap;
25 uint8_t int_line;
26 uint8_t int_pin;
27 uint8_t min_gnt;
28 uint8_t max_lat;
31 void PCIDevice::config_rw(uint8_t addr, unsigned len, uint32_t *data, bool read)
33 RegisterIO reg(addr, len, data, read);
35 /* These are required to be implemented */
36 reg.io(&this->vendor_id, 0x00, READONLY);
37 reg.io(&this->device_id, 0x02, READONLY);
38 reg.io(&this->command, 0x04);
39 reg.io(&this->status, 0x06);
40 reg.io(&this->rid, 0x08, READONLY);
41 reg.io(&this->prog_if, 0x09, READONLY);
42 reg.io(&this->subclass_code, 0x0A, READONLY);
43 reg.io(&this->class_code, 0x0B, READONLY);
44 reg.io(&this->headt, 0x0E);
48 struct MemoryRegion
50 uint64_t start;
51 uint64_t size;