tools/reconos_upgrade_hwt_30_31.sh

   1 #!/bin/sh
   2 #
   3 #                                                        ____  _____
   4 #                            ________  _________  ____  / __ \/ ___/
   5 #                           / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
   6 #                          / /  /  __/ /__/ /_/ / / / / /_/ /___/ /
   7 #                         /_/   \___/\___/\____/_/ /_/\____//____/
   8 #
   9 # ======================================================================
  10 #
  11 #   project:      ReconOS
  12 #   author:       Christoph Rüthing, University of Paderborn
  13 #   description:  Script to upgrade a hardware thread written for
  14 #                 version 3.0 to version 3.1
  15 #
  16 # ======================================================================
  17
  18 MPD='/home/christoph/Documents/reconos/demos/sort_demo/hw/hwt_sort_demo_v1_00_c/data/hwt_sort_demo_v2_1_0.mpd'
  19 PAO='/home/christoph/Documents/reconos/demos/sort_demo/hw/hwt_sort_demo_v1_00_c/data/hwt_sort_demo_v2_1_0.pao'
  20 VHDL='/home/christoph/Documents/reconos/demos/sort_demo/hw/hwt_sort_demo_v1_00_c/hdl/vhdl/hwt_sort_demo.vhd'
  21
  22 ### Upgrade MPD
  23
  24 cp $MPD $MPD.bak
  25
  26 # remove all ReconOS v3.0 ports an busses
  27 sed -i '
  28 /^\s*BUS_INTERFACE\s*BUS\s*=\s*OS_SFSL.*/d
  29 /^\s*BUS_INTERFACE\s*BUS\s*=\s*OS_MFSL.*/d
  30 /^\s*BUS_INTERFACE\s*BUS\s*=\s*SFIFO32.*/d
  31 /^\s*BUS_INTERFACE\s*BUS\s*=\s*MFIFO32.*/d
  32
  33 /^\s*PORT\s*OSFSL_Clk.*/d
  34 /^\s*PORT\s*OSFSL_Rst.*/d
  35
  36 /^\s*PORT\s*OSFSL_S_Clk.*/d
  37 /^\s*PORT\s*OSFSL_S_Read.*/d
  38 /^\s*PORT\s*OSFSL_S_Data.*/d
  39 /^\s*PORT\s*OSFSL_S_Control.*/d
  40 /^\s*PORT\s*OSFSL_S_Exists.*/d
  41
  42 /^\s*PORT\s*OSFSL_M_Clk.*/d
  43 /^\s*PORT\s*OSFSL_M_Write.*/d
  44 /^\s*PORT\s*OSFSL_M_Data.*/d
  45 /^\s*PORT\s*OSFSL_M_Control.*/d
  46 /^\s*PORT\s*OSFSL_M_Full.*/d
  47
  48 /^\s*PORT\s*FIFO32_S_Clk.*/d
  49 /^\s*PORT\s*FIFO32_S_Data.*/d
  50 /^\s*PORT\s*FIFO32_S_Rd.*/d
  51 /^\s*PORT\s*FIFO32_S_Fill.*/d
  52
  53 /^\s*PORT\s*FIFO32_M_Clk.*/d
  54 /^\s*PORT\s*FIFO32_M_Data.*/d
  55 /^\s*PORT\s*FIFO32_M_Wr.*/d
  56 /^\s*PORT\s*FIFO32_M_Rem.*/d
  57
  58 /^\s*PORT\s*Rst.*/d
  59 /^\s*PORT\s*Clk.*/d
  60
  61 /^END/d
  62 ' $MPD
  63
  64 # Insert ReconOS v3.1 ports and busses
  65 cat >> $MPD.tmp << EOF
  66 ## ReconOS Ports UPGRADE
  67
  68 ## Bus Interfaces
  69 BUS_INTERFACE BUS=OSIF_FIFO_Sw2Hw, BUS_STD=S_FIFO, BUS_TYPE=INITIATOR
  70 BUS_INTERFACE BUS=OSIF_FIFO_Hw2Sw, BUS_STD=M_FIFO, BUS_TYPE=INITIATOR
  71 BUS_INTERFACE BUS=MEMIF_FIFO_Hwt2Mem, BUS_STD=M_FIFO, BUS_TYPE=INITIATOR
  72 BUS_INTERFACE BUS=MEMIF_FIFO_Mem2Hwt, BUS_STD=S_FIFO, BUS_TYPE=INITIATOR
  73
  74 ## Peripheral ports
  75 PORT OSIF_FIFO_Sw2Hw_Data = "S_FIFO_Data", DIR = I, VEC = [31:0], BUS = OSIF_FIFO_Sw2Hw
  76 PORT OSIF_FIFO_Sw2Hw_Fill = "S_FIFO_Fill", DIR = I, VEC = [15:0], BUS = OSIF_FIFO_Sw2Hw
  77 PORT OSIF_FIFO_Sw2Hw_Empty = "S_FIFO_Empty", DIR = I, BUS = OSIF_FIFO_Sw2Hw
  78 PORT OSIF_FIFO_Sw2Hw_RE = "S_FIFO_RE", DIR = O, BUS = OSIF_FIFO_Sw2Hw
  79
  80 PORT OSIF_FIFO_Hw2Sw_Data = "M_FIFO_Data", DIR = O, VEC = [31:0], BUS = OSIF_FIFO_Hw2Sw
  81 PORT OSIF_FIFO_Hw2Sw_Rem = "M_FIFO_Rem", DIR = I, VEC = [15:0], BUS = OSIF_FIFO_Hw2Sw
  82 PORT OSIF_FIFO_Hw2Sw_Full = "M_FIFO_Full", DIR = I, BUS = OSIF_FIFO_Hw2Sw
  83 PORT OSIF_FIFO_Hw2Sw_WE = "M_FIFO_WE", DIR = O, BUS = OSIF_FIFO_Hw2Sw
  84
  85 PORT MEMIF_FIFO_Hwt2Mem_Data = "M_FIFO_Data", DIR = O, VEC = [31:0], BUS = MEMIF_FIFO_Hwt2Mem
  86 PORT MEMIF_FIFO_Hwt2Mem_Rem = "M_FIFO_Rem", DIR = I, VEC = [15:0], BUS = MEMIF_FIFO_Hwt2Mem
  87 PORT MEMIF_FIFO_Hwt2Mem_Full = "M_FIFO_Full", DIR = I, BUS = MEMIF_FIFO_Hwt2Mem
  88 PORT MEMIF_FIFO_Hwt2Mem_WE = "M_FIFO_WE", DIR = O, BUS = MEMIF_FIFO_Hwt2Mem
  89
  90 PORT MEMIF_FIFO_Mem2Hwt_Data = "S_FIFO_Data", DIR = I, VEC = [31:0], BUS = MEMIF_FIFO_Mem2Hwt
  91 PORT MEMIF_FIFO_Mem2Hwt_Fill = "S_FIFO_Fill", DIR = I, VEC = [15:0], BUS = MEMIF_FIFO_Mem2Hwt
  92 PORT MEMIF_FIFO_Mem2Hwt_Empty = "S_FIFO_Empty", DIR = I, BUS = MEMIF_FIFO_Mem2Hwt
  93 PORT MEMIF_FIFO_Mem2Hwt_RE = "S_FIFO_RE", DIR = O, BUS = MEMIF_FIFO_Mem2Hwt
  94
  95 PORT HWT_Clk = "", DIR = I, SIGIS = Clk
  96 PORT HWT_Rst = "", DIR = I, SIGIS = Rst
  97
  98 END
  99 EOF
 100
 101
 102 ### Upgrade PAO
 103
 104 cp $PAO $PAO.bak
 105
 106 sed -i '
 107   s/reconos_v3_00_[ab]/reconos_v3_00_c/g
 108 ' $PAO
 109
 110
 111 ### Upgrade VHDL
 112
 113 cp $VHDL $VHDL.bak
 114
 115 sed -in '
 116   1h
 117   1!H
 118   $ {
 119     g
 120     s/fsl_setup([^)]*);/osif_setup(\
 121                 i_osif,\
 122                 o_osif,\
 123                 OSIF_FIFO_Sw2Hw_Data,\
 124                 OSIF_FIFO_Sw2Hw_Fill,\
 125                 OSIF_FIFO_Sw2Hw_Empty,\
 126                 OSIF_FIFO_Hw2Sw_Rem,\
 127                 OSIF_FIFO_Hw2Sw_Full,\
 128                 OSIF_FIFO_Sw2Hw_RE,\
 129                 OSIF_FIFO_Hw2Sw_Data,\
 130                 OSIF_FIFO_Hw2Sw_WE\
 131         );/g
 132
 133     s/memif_setup([^)]*);/memif_setup\
 134                 i_memif,\
 135                 o_memif,\
 136                 MEMIF_FIFO_Mem2Hwt_Data,\
 137                 MEMIF_FIFO_Mem2Hwt_Fill,\
 138                 MEMIF_FIFO_Mem2Hwt_Empty,\
 139                 MEMIF_FIFO_Hwt2Mem_Rem,\
 140                 MEMIF_FIFO_Hwt2Mem_Full,\
 141                 MEMIF_FIFO_Mem2Hwt_RE,\
 142                 MEMIF_FIFO_Hwt2Mem_Data,\
 143                 MEMIF_FIFO_Hwt2Mem_WE\
 144         );/g
 145     p
 146   }
 147 ' $VHDL
 148
 149 sed '
 150   s/reconos_v3_00_[ab]/reconos_v3_00_c/g
 151
 152   0,/OSFSL_Clk\s*:\s*in.*/{//d;}
 153 ' $VHDL
 154
 155 #  /OSFSL_Clk\s*:\s*in.*/d
 156 #  /OSFSL_Rst\s*:\s*in.*/d
 157 #  /OSFSL_S_Clk\s*:\s*out.*/d
 158 #  /OSFSL_S_Read\s*:\s*out.*/d
 159 #  /OSFSL_S_Data\s*:\s*in.*/d
 160 #  /OSFSL_S_Control\s*:\s*in.*/d
 161 #  /OSFSL_S_Exists\s*:\s*in.*/d
 162 #
 163 #  /OSFSL_M_Clk\s*:\s*out.*/d
 164 #  /OSFSL_M_Write\s*:\s*out.*/d
 165 #  /OSFSL_M_Data\s*:\s*out.*/d
 166 #  /OSFSL_M_Control\s*:\s*out.*/d
 167 #  /OSFSL_M_Full\s*:\s*in.*/d
 168 #
 169 #  /FIFO32_S_Data\s*:\s*in.*/d
 170 #  /FIFO32_S_Fill\s*:\s*in.*/d
 171 #  /FIFO32_S_Rd\s*:\s*out.*/d
 172 #
 173 #  /FIFO32_M_Data\s*:\s*out.*/d
 174 #  /FIFO32_M_Rem\s*:\s*in.*/d
 175 #  /FIFO32_M_Wr\s*:\s*out.*/d
 176 #
 177 #  /clk\s*:\s*in.*/d
 178 #  /rst\s*:\s*in.*/d
 179 #