?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
add support for building psp toolchain
[rofl0r-mmix-cross.git] / patches / binutils-2.23.2-psp.diff
blob758e5dfcaf90c4f6a8d70a963cc7e103e5e2e0c7
1 diff -NrU3 binutils-2.23.2/bfd/archures.c binutils-2.23.2-patched/bfd/archures.c
2 --- binutils-2.23.2/bfd/archures.c 2012-09-04 14:53:41.000000000 +0200
3 +++ binutils-2.23.2-patched/bfd/archures.c 2020-04-23 17:57:30.297522944 +0200
4 @@ -175,6 +175,7 @@
5 .#define bfd_mach_mips_loongson_2f 3002
6 .#define bfd_mach_mips_loongson_3a 3003
7 .#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
8 +.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31 *}
9 .#define bfd_mach_mips_octeon 6501
10 .#define bfd_mach_mips_octeonp 6601
11 .#define bfd_mach_mips_octeon2 6502
12 diff -NrU3 binutils-2.23.2/bfd/bfd-in2.h binutils-2.23.2-patched/bfd/bfd-in2.h
13 --- binutils-2.23.2/bfd/bfd-in2.h 2012-09-04 14:53:41.000000000 +0200
14 +++ binutils-2.23.2-patched/bfd/bfd-in2.h 2020-04-23 17:57:30.297522944 +0200
15 @@ -1904,6 +1904,7 @@
16 #define bfd_mach_mips_loongson_2f 3002
17 #define bfd_mach_mips_loongson_3a 3003
18 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
19 +#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31 */
20 #define bfd_mach_mips_octeon 6501
21 #define bfd_mach_mips_octeonp 6601
22 #define bfd_mach_mips_octeon2 6502
23 diff -NrU3 binutils-2.23.2/bfd/cpu-mips.c binutils-2.23.2-patched/bfd/cpu-mips.c
24 --- binutils-2.23.2/bfd/cpu-mips.c 2012-01-31 18:54:35.000000000 +0100
25 +++ binutils-2.23.2-patched/bfd/cpu-mips.c 2020-04-23 17:57:30.297522944 +0200
26 @@ -90,6 +90,7 @@
27 I_mipsisa64,
28 I_mipsisa64r2,
29 I_sb1,
30 + I_allegrex,
31 I_loongson_2e,
32 I_loongson_2f,
33 I_loongson_3a,
34 @@ -133,6 +134,7 @@
35 N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
36 N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
37 N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
38 + N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, NN(I_allegrex)),
39 N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
40 N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
41 N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
42 diff -NrU3 binutils-2.23.2/bfd/elfxx-mips.c binutils-2.23.2-patched/bfd/elfxx-mips.c
43 --- binutils-2.23.2/bfd/elfxx-mips.c 2013-03-25 09:06:20.000000000 +0100
44 +++ binutils-2.23.2-patched/bfd/elfxx-mips.c 2020-04-23 17:57:30.299522934 +0200
45 @@ -6271,14 +6271,19 @@
46 case E_MIPS_MACH_SB1:
47 return bfd_mach_mips_sb1;
48
49 + case E_MIPS_MACH_ALLEGREX:
50 + return bfd_mach_mips_allegrex;
51 +
52 case E_MIPS_MACH_LS2E:
53 return bfd_mach_mips_loongson_2e;
54
55 case E_MIPS_MACH_LS2F:
56 return bfd_mach_mips_loongson_2f;
57
58 + /*
59 case E_MIPS_MACH_LS3A:
60 return bfd_mach_mips_loongson_3a;
61 + */
62
63 case E_MIPS_MACH_OCTEON2:
64 return bfd_mach_mips_octeon2;
65 @@ -11027,6 +11032,10 @@
66 val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
67 break;
68
69 + case bfd_mach_mips_allegrex:
70 + val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX;
71 + break;
72 +
73 case bfd_mach_mips_loongson_3a:
74 val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
75 break;
76 @@ -13686,6 +13695,7 @@
77 /* MIPS II extensions. */
78 { bfd_mach_mips4000, bfd_mach_mips6000 },
79 { bfd_mach_mipsisa32, bfd_mach_mips6000 },
80 + { bfd_mach_mips_allegrex, bfd_mach_mips6000 },
81
82 /* MIPS I extensions. */
83 { bfd_mach_mips6000, bfd_mach_mips3000 },
84 diff -NrU3 binutils-2.23.2/binutils/readelf.c binutils-2.23.2-patched/binutils/readelf.c
85 --- binutils-2.23.2/binutils/readelf.c 2013-03-25 09:06:21.000000000 +0100
86 +++ binutils-2.23.2-patched/binutils/readelf.c 2020-04-23 17:57:30.299522934 +0200
87 @@ -2431,10 +2431,11 @@
88 case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
89 case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
90 case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
91 - case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break;
92 + /* case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break; */
93 case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
94 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
95 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
96 + case E_MIPS_MACH_ALLEGREX: strcat(buf, ", allegrex"); break;
97 case 0:
98 /* We simply ignore the field in this case to avoid confusion:
99 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
100 diff -NrU3 binutils-2.23.2/config.sub binutils-2.23.2-patched/config.sub
101 --- binutils-2.23.2/config.sub 2012-04-25 17:53:25.000000000 +0200
102 +++ binutils-2.23.2-patched/config.sub 2020-04-23 17:57:30.301522924 +0200
103 @@ -292,6 +292,7 @@
104 | mipsisa64sb1 | mipsisa64sb1el \
105 | mipsisa64sr71k | mipsisa64sr71kel \
106 | mipstx39 | mipstx39el \
107 + | mipsallegrex | mipsallegrexel \
108 | mn10200 | mn10300 \
109 | moxie \
110 | mt \
111 @@ -408,6 +409,7 @@
112 | mipsisa64sb1-* | mipsisa64sb1el-* \
113 | mipsisa64sr71k-* | mipsisa64sr71kel-* \
114 | mipstx39-* | mipstx39el-* \
115 + | mipsallegrex-* | mipsallegrexel-* \
116 | mmix-* \
117 | mt-* \
118 | msp430-* \
119 @@ -806,6 +808,10 @@
120 basic_machine=m68k-atari
121 os=-mint
122 ;;
123 + psp)
124 + basic_machine=mipsallegrexel-psp
125 + os=-elf
126 + ;;
127 mips3*-*)
128 basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
129 ;;
130 --- binutils-2.23.2/config.guess 2021-02-14 16:35:28.201894642 +0800
131 +++ binutils-2.23.2-patched/config.guess 2021-02-14 16:36:42.841894677 +0800
132 @@ -140,6 +140,27 @@
133 UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown
134 UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown
135
136 +case "${UNAME_SYSTEM}" in
137 +Linux|GNU|GNU/*)
138 + # If the system lacks a compiler, then just pick glibc.
139 + # We could probably try harder.
140 + LIBC=gnu
141 +
142 + eval $set_cc_for_build
143 + cat <<-EOF > $dummy.c
144 + #include <features.h>
145 + #if defined(__UCLIBC__)
146 + LIBC=uclibc
147 + #elif defined(__dietlibc__)
148 + LIBC=dietlibc
149 + #else
150 + LIBC=gnu
151 + #endif
152 + EOF
153 + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'`
154 + ;;
155 +esac
156 +
157 # Note: order is significant - the case branches are not exclusive.
158
159 case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
160 @@ -861,6 +882,13 @@
161 i*86:Minix:*:*)
162 echo ${UNAME_MACHINE}-pc-minix
163 exit ;;
164 + aarch64:Linux:*:*)
165 + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
166 + exit ;;
167 + aarch64_be:Linux:*:*)
168 + UNAME_MACHINE=aarch64_be
169 + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
170 + exit ;;
171 alpha:Linux:*:*)
172 case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
173 EV5) UNAME_MACHINE=alphaev5 ;;
174 diff -NrU3 binutils-2.23.2/configure binutils-2.23.2-patched/configure
175 --- binutils-2.23.2/configure 2012-06-28 13:50:52.000000000 +0200
176 +++ binutils-2.23.2-patched/configure 2020-04-23 17:57:30.323522816 +0200
177 @@ -2674,7 +2674,7 @@
178 # binutils, gas and ld appear in that order because it makes sense to run
179 # "make check" in that particular order.
180 # If --enable-gold is used, "gold" may replace "ld".
181 -host_tools="texinfo flex bison binutils gas ld fixincludes gcc cgen sid sim gdb gprof etc expect dejagnu m4 utils guile fastjar gnattools"
182 +host_tools="texinfo flex bison binutils gas ld fixincludes gcc cgen sid sim gdb etc expect dejagnu m4 utils guile fastjar gnattools"
183
184 # libgcj represents the runtime libraries only used by gcj.
185 libgcj="target-libffi \
186 @@ -3593,7 +3593,6 @@
187 mips*-*-linux*)
188 ;;
189 mips*-*-*)
190 - noconfigdirs="$noconfigdirs gprof"
191 ;;
192 sh-*-* | sh64-*-*)
193 case "${target}" in
194 diff -NrU3 binutils-2.23.2/gas/config/tc-mips.c binutils-2.23.2-patched/gas/config/tc-mips.c
195 --- binutils-2.23.2/gas/config/tc-mips.c 2012-09-04 16:21:03.000000000 +0200
196 +++ binutils-2.23.2-patched/gas/config/tc-mips.c 2020-04-23 17:57:30.325522805 +0200
197 @@ -91,8 +91,32 @@
198
199 #define ZERO 0
200 #define ATREG 1
201 +#define V0 2
202 +#define V1 3
203 +#define A0 4
204 +#define A1 5
205 +#define A2 6
206 +#define A3 7
207 +#define T0 8
208 +#define T1 9
209 +#define T2 10
210 +#define T3 11
211 +#define T4 12
212 +#define T5 13
213 +#define T6 14
214 +#define T7 15
215 #define S0 16
216 +#define S1 17
217 +#define S2 18
218 +#define S3 19
219 +#define S4 20
220 +#define S5 21
221 +#define S6 22
222 #define S7 23
223 +#define T8 24
224 +#define T9 25
225 +#define K0 26
226 +#define K1 27
227 #define TREG 24
228 #define PIC_CALL_REG 25
229 #define KT0 26
230 @@ -493,11 +517,14 @@
231 /* Return true if the given CPU supports the microMIPS ASE. */
232 #define CPU_HAS_MICROMIPS(cpu) 0
233
234 +/* True if the given CPU belongs to the Allegrex family. */
235 +#define CPU_IS_ALLEGREX(CPU) ((CPU) == CPU_ALLEGREX)
236 +
237 /* True if CPU has a dror instruction. */
238 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
239
240 /* True if CPU has a ror instruction. */
241 -#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
242 +#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) || CPU_IS_ALLEGREX (CPU)
243
244 /* True if CPU is in the Octeon family */
245 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
246 @@ -529,6 +556,7 @@
247 || mips_opts.arch == CPU_R16000 \
248 || mips_opts.arch == CPU_RM7000 \
249 || mips_opts.arch == CPU_VR5500 \
250 + || mips_opts.arch == CPU_ALLEGREX \
251 || mips_opts.micromips \
252 )
253
254 @@ -1559,6 +1587,8 @@
255 static expressionS imm_expr;
256 static expressionS imm2_expr;
257 static expressionS offset_expr;
258 +static expressionS vimm_expr[4];
259 +static expressionS voffset_expr[4];
260
261 /* Relocs associated with imm_expr and offset_expr. */
262
263 @@ -1567,6 +1597,15 @@
264 static bfd_reloc_code_real_type offset_reloc[3]
265 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
266
267 +/* set by vfpu code for prefix instructions */
268 +
269 +static bfd_boolean vfpu_dprefix;
270 +static char vfpu_dprefix_str[64];
271 +static bfd_boolean vfpu_sprefix;
272 +static char vfpu_sprefix_str[64];
273 +static bfd_boolean vfpu_tprefix;
274 +static char vfpu_tprefix_str[64];
275 +
276 /* This is set to the resulting size of the instruction to be produced
277 by mips16_ip if an explicit extension is used or by mips_ip if an
278 explicit size is supplied. */
279 @@ -2570,6 +2609,56 @@
280 return;
281 }
282
283 + /* If we've generated operands for a VFPU prefix instruction then we need
284 + to assemble and append the prefix instruction before emitting the
285 + instruction it prefixes. Note that in mips_ip prefix operands do not
286 + cause any side effects with imm_expr or offset_expr. If they did
287 + we'd have to save and restore them here. */
288 + if (CPU_IS_ALLEGREX (mips_opts.arch) && ((vfpu_dprefix || vfpu_sprefix || vfpu_tprefix)))
289 + {
290 +
291 + if (mips_opts.noreorder
292 + && ( history[0].insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
293 + | INSN_COND_BRANCH_DELAY
294 + | INSN_COND_BRANCH_LIKELY)))
295 + {
296 + as_bad (_("instruction with prefix cannot be used in branch delay slot"));
297 + }
298 +
299 + if (vfpu_dprefix)
300 + {
301 + struct mips_cl_insn prefix;
302 + char buf[256];
303 +
304 + sprintf (buf, "vpfxd %s", vfpu_dprefix_str);
305 + mips_ip (buf, &prefix);
306 + append_insn (&prefix, NULL, unused_reloc, FALSE);
307 + vfpu_dprefix = FALSE;
308 + }
309 +
310 + if (vfpu_sprefix)
311 + {
312 + struct mips_cl_insn prefix;
313 + char buf[256];
314 +
315 + sprintf (buf, "vpfxs %s", vfpu_sprefix_str);
316 + mips_ip (buf, &prefix);
317 + append_insn ( &prefix, NULL, unused_reloc, FALSE);
318 + vfpu_sprefix = FALSE;
319 + }
320 +
321 + if (vfpu_tprefix)
322 + {
323 + struct mips_cl_insn prefix;
324 + char buf[256];
325 +
326 + sprintf (buf, "vpfxt %s", vfpu_tprefix_str);
327 + mips_ip (buf, &prefix);
328 + append_insn (&prefix, NULL, unused_reloc, FALSE);
329 + vfpu_tprefix = FALSE;
330 + }
331 + }
332 +
333 if (insn.insn_mo->pinfo == INSN_MACRO)
334 {
335 macro_start ();
336 @@ -5083,6 +5172,55 @@
337 }
338 continue;
339
340 + /* VFPU fields */
341 + case '?':
342 + switch (*fmt++)
343 + {
344 + case 'o':
345 + *r = (bfd_reloc_code_real_type) va_arg (args, int);
346 + gas_assert (*r == BFD_RELOC_GPREL16
347 + || *r == BFD_RELOC_MIPS_LITERAL
348 + || *r == BFD_RELOC_MIPS_HIGHER
349 + || *r == BFD_RELOC_HI16_S
350 + || *r == BFD_RELOC_LO16
351 + || *r == BFD_RELOC_MIPS_GOT16
352 + || *r == BFD_RELOC_MIPS_CALL16
353 + || *r == BFD_RELOC_MIPS_GOT_DISP
354 + || *r == BFD_RELOC_MIPS_GOT_PAGE
355 + || *r == BFD_RELOC_MIPS_GOT_OFST
356 + || *r == BFD_RELOC_MIPS_GOT_LO16
357 + || *r == BFD_RELOC_MIPS_CALL_LO16);
358 + break;
359 + case 'd':
360 + insn.insn_opcode |= va_arg (args, int) << VF_SH_VD;
361 + fmt += 2;
362 + break;
363 + case 's':
364 + insn.insn_opcode |= va_arg (args, int) << VF_SH_VS;
365 + fmt += 2;
366 + break;
367 + case 'm':
368 + {
369 + int vtreg = va_arg (args, int);
370 + insn.insn_opcode |= (vtreg & VF_MASK_VML) << VF_SH_VML;
371 + insn.insn_opcode |= ((vtreg >> 5) & VF_MASK_VMH) << VF_SH_VMH;
372 + fmt += 2;
373 + }
374 + break;
375 + case 'n':
376 + {
377 + int vtreg = va_arg (args, int);
378 + insn.insn_opcode |= (vtreg & VF_MASK_VNL) << VF_SH_VNL;
379 + insn.insn_opcode |= ((vtreg >> 5) & VF_MASK_VNH) << VF_SH_VNH;
380 + fmt += 2;
381 + }
382 + break;
383 + case 'e':
384 + insn.insn_opcode |= va_arg (args, int) << VF_SH_MCOND;
385 + break;
386 + }
387 + continue;
388 +
389 default:
390 internalError ();
391 }
392 @@ -6239,6 +6377,7 @@
393 macro (struct mips_cl_insn *ip)
394 {
395 unsigned int treg, sreg, dreg, breg;
396 + int vsreg, vtreg, vdreg, vmreg, vwb;
397 unsigned int tempreg;
398 int mask;
399 int used_at = 0;
400 @@ -6271,6 +6410,13 @@
401 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
402 mask = ip->insn_mo->mask;
403
404 + vmreg = ((ip->insn_opcode >> 16) & 0x1f)
405 + | ((ip->insn_opcode << 5) & 0x60);
406 + vtreg = (ip->insn_opcode >> 16) & 0x7f;
407 + vsreg = (ip->insn_opcode >> 8) & 0x7f;
408 + vdreg = (ip->insn_opcode >> 0) & 0x7f;
409 + vwb = (ip->insn_opcode >> 1) & 0x1;
410 +
411 label_expr.X_op = O_constant;
412 label_expr.X_op_symbol = NULL;
413 label_expr.X_add_symbol = NULL;
414 @@ -7968,6 +8114,34 @@
415 /* Itbl support may require additional care here. */
416 coproc = 1;
417 goto ld_st;
418 + case M_LV_S_AB:
419 + s = "lv.s";
420 + /* Itbl support may require additional care here. */
421 + coproc = 1;
422 + fmt = "?m0x,?o(b)";
423 + treg = vmreg;
424 + goto ld;
425 + case M_LV_Q_AB:
426 + s = "lv.q";
427 + /* Itbl support may require additional care here. */
428 + coproc = 1;
429 + fmt = "?n3x,?o(b)";
430 + treg = vmreg;
431 + goto ld;
432 + case M_LVL_Q_AB:
433 + s = "lvl.q";
434 + /* Itbl support may require additional care here. */
435 + coproc = 1;
436 + fmt = "?n3x,?o(b)";
437 + treg = vmreg;
438 + goto ld;
439 + case M_LVR_Q_AB:
440 + s = "lvr.q";
441 + /* Itbl support may require additional care here. */
442 + coproc = 1;
443 + fmt = "?n3x,?o(b)";
444 + treg = vmreg;
445 + goto ld;
446 case M_LWL_AB:
447 ab = 1;
448 case M_LWL_OB:
449 @@ -8129,6 +8303,37 @@
450 /* Itbl support may require additional care here. */
451 coproc = 1;
452 goto ld_st;
453 + case M_SV_S_AB:
454 + s = "sv.s";
455 + /* Itbl support may require additional care here. */
456 + coproc = 1;
457 + fmt = "?m0x,?o(b)";
458 + treg = vmreg;
459 + goto ld_st;
460 + case M_SV_Q_AB:
461 + if (vwb)
462 + s = "vwb.q";
463 + else
464 + s = "sv.q";
465 + /* Itbl support may require additional care here. */
466 + coproc = 1;
467 + fmt = "?n3x,?o(b)";
468 + treg = vmreg;
469 + goto ld_st;
470 + case M_SVL_Q_AB:
471 + s = "svl.q";
472 + /* Itbl support may require additional care here. */
473 + coproc = 1;
474 + fmt = "?n3x,?o(b)";
475 + treg = vmreg;
476 + goto ld_st;
477 + case M_SVR_Q_AB:
478 + s = "svr.q";
479 + /* Itbl support may require additional care here. */
480 + coproc = 1;
481 + fmt = "?n3x,?o(b)";
482 + treg = vmreg;
483 + goto ld_st;
484 case M_SWL_AB:
485 ab = 1;
486 case M_SWL_OB:
487 @@ -8661,6 +8866,138 @@
488 break;
489 }
490
491 + case M_LVI_S_SS:
492 + case M_LVI_P_SS:
493 + case M_LVI_T_SS:
494 + case M_LVI_Q_SS:
495 + {
496 + int mtx = (vtreg >> VF_SH_MR_MTX) & VF_MASK_MR_MTX;
497 + int idx = (vtreg >> VF_SH_MR_IDX) & VF_MASK_MR_IDX;
498 + int fsl = 0;
499 + int rxc = 0;
500 + int vtreg_s = 0;
501 + int vnum = 0;
502 + int vat = 0;
503 + int i;
504 +
505 + switch (mask)
506 + {
507 + case M_LVI_S_SS:
508 + vnum = 1;
509 + fsl = (vtreg >> VF_SH_MR_FSL) & VF_MASK_MR_FSL;
510 + rxc = 0;
511 + break;
512 + case M_LVI_P_SS:
513 + vnum = 2;
514 + fsl = ((vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL) << 1;
515 + rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
516 + break;
517 + case M_LVI_T_SS:
518 + vnum = 3;
519 + fsl = (vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL;
520 + rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
521 + break;
522 + case M_LVI_Q_SS:
523 + vnum = 4;
524 + fsl = 0;
525 + rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
526 + break;
527 + }
528 + if (rxc)
529 + vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_FSL)
530 + | (fsl << VF_SH_MR_IDX);
531 + else
532 + vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_IDX)
533 + | (fsl << VF_SH_MR_FSL);
534 +
535 + for (i = 0; i < vnum; i++) {
536 + imm_expr = vimm_expr[i];
537 + offset_expr = voffset_expr[i];
538 +
539 + if (imm_expr.X_op == O_constant)
540 + {
541 + load_register (AT, &imm_expr, 0);
542 + macro_build ((expressionS *) NULL,
543 + "mtv", "t,?d0z", AT, vtreg_s);
544 + vat = 1;
545 + }
546 + else
547 + {
548 + gas_assert (offset_expr.X_op == O_symbol
549 + && strcmp (segment_name (S_GET_SEGMENT
550 + (offset_expr.X_add_symbol)),
551 + ".lit4") == 0
552 + && offset_expr.X_add_number == 0);
553 + macro_build (&offset_expr,
554 + "lv.s", "?m0x,?o(b)", vtreg_s,
555 + (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
556 + }
557 +
558 + if (rxc)
559 + vtreg_s += (1 << VF_SH_MR_IDX);
560 + else
561 + vtreg_s += (1 << VF_SH_MR_FSL);
562 + }
563 +
564 + if (vat)
565 + break;
566 + else
567 + return;
568 + }
569 +
570 + case M_LVHI_S_SS:
571 + case M_LVHI_P_SS:
572 + {
573 + int mtx = (vtreg >> VF_SH_MR_MTX) & VF_MASK_MR_MTX;
574 + int idx = (vtreg >> VF_SH_MR_IDX) & VF_MASK_MR_IDX;
575 + int fsl = 0;
576 + int rxc = 0;
577 + int vtreg_s = 0;
578 + int vnum = 0;
579 + int i;
580 + unsigned int f16v;
581 + char f16v_str[16];
582 +
583 + switch (mask)
584 + {
585 + case M_LVHI_S_SS:
586 + vnum = 2;
587 + fsl = (vtreg >> VF_SH_MR_FSL) & VF_MASK_MR_FSL;
588 + rxc = 0;
589 + break;
590 + case M_LVHI_P_SS:
591 + vnum = 4;
592 + fsl = ((vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL) << 1;
593 + rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
594 + break;
595 + }
596 + if (rxc)
597 + vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_FSL)
598 + | (fsl << VF_SH_MR_IDX);
599 + else
600 + vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_IDX)
601 + | (fsl << VF_SH_MR_FSL);
602 +
603 +
604 + for (i = 0; i < vnum; i += 2) {
605 + f16v = ((vimm_expr[i + 1].X_add_number & 0xffff) << 16)
606 + | (vimm_expr[i].X_add_number & 0xffff);
607 + sprintf(f16v_str, "0x%08x", f16v);
608 + my_getExpression (&imm_expr, f16v_str);
609 +
610 + load_register (AT, &imm_expr, 0);
611 + macro_build ((expressionS *) NULL,
612 + "mtv", "t,?d0z", AT, vtreg_s);
613 +
614 + if (rxc)
615 + vtreg_s += (1 << VF_SH_MR_IDX);
616 + else
617 + vtreg_s += (1 << VF_SH_MR_FSL);
618 + }
619 +
620 + break;
621 + }
622 +
623 case M_LI_D:
624 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
625 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
626 @@ -9179,6 +9516,27 @@
627 move_register (dreg, sreg);
628 break;
629
630 + case M_VCMOV_S:
631 + s = "vcmovt.s";
632 + fmt = "?d0d,?s0s,?e";
633 + goto vcmov;
634 + case M_VCMOV_P:
635 + s = "vcmovt.p";
636 + fmt = "?d1d,?s1s,?e";
637 + goto vcmov;
638 + case M_VCMOV_T:
639 + s = "vcmovt.t";
640 + fmt = "?d2d,?s2s,?e";
641 + goto vcmov;
642 + case M_VCMOV_Q:
643 + s = "vcmovt.q";
644 + fmt = "?d3d,?s3s,?e";
645 + vcmov:
646 + macro_build ((expressionS *) NULL, s, fmt,
647 + vdreg, vsreg,
648 + (ip->insn_opcode >> VF_SH_MCOND) & VF_MASK_MCOND);
649 + return;
650 +
651 case M_DMUL:
652 dbl = 1;
653 case M_MUL:
654 @@ -9794,6 +10152,40 @@
655 off12 = mips_opts.micromips;
656 off = 3;
657 goto uld_st;
658 +
659 + case M_ULV_S:
660 + if (mips_opts.arch == CPU_ALLEGREX)
661 + as_bad (_("opcode not supported on this processor"));
662 + off = 3;
663 + if (offset_expr.X_add_number >= 0x8000 - off)
664 + as_bad (_("operand overflow"));
665 + if (! target_big_endian)
666 + offset_expr.X_add_number += off;
667 + macro_build (&offset_expr, "lwl", "t,o(b)",
668 + AT, (int) BFD_RELOC_LO16, breg);
669 + if (! target_big_endian)
670 + offset_expr.X_add_number -= off;
671 + else
672 + offset_expr.X_add_number += off;
673 + macro_build (&offset_expr, "lwr", "t,o(b)",
674 + AT, (int) BFD_RELOC_LO16, breg);
675 +
676 + macro_build ((expressionS *) NULL, "mtv", "t,?d0z",
677 + AT, vmreg);
678 + break;
679 +
680 + case M_ULV_Q:
681 + off = 12;
682 + if (offset_expr.X_add_number >= 0x8000 - off)
683 + as_bad (_("operand overflow"));
684 + offset_expr.X_add_number += off;
685 + macro_build (&offset_expr, "lvl.q", "?n3x,?o(b)",
686 + vmreg, (int) BFD_RELOC_LO16, breg);
687 + offset_expr.X_add_number -= off;
688 + macro_build (&offset_expr, "lvr.q", "?n3x,?o(b)",
689 + vmreg, (int) BFD_RELOC_LO16, breg);
690 + return;
691 +
692 case M_ULD_A:
693 ab = 1;
694 case M_ULD:
695 @@ -9819,6 +10211,56 @@
696 off = 3;
697 ust = 1;
698 goto uld_st;
699 +
700 + case M_USV_S:
701 + off = 3;
702 + if (offset_expr.X_add_number >= 0x8000 - off)
703 + as_bad (_("operand overflow"));
704 + macro_build ((expressionS *) NULL, "mfv", "t,?d0z",
705 + AT, vmreg);
706 + if (mips_opts.arch != CPU_ALLEGREX)
707 + {
708 + if (! target_big_endian)
709 + offset_expr.X_add_number += off;
710 + macro_build (&offset_expr, "swl", "t,o(b)",
711 + AT, (int) BFD_RELOC_LO16, breg);
712 + if (! target_big_endian)
713 + offset_expr.X_add_number -= off;
714 + else
715 + offset_expr.X_add_number += off;
716 + macro_build (&offset_expr, "swr", "t,o(b)",
717 + AT, (int) BFD_RELOC_LO16, breg);
718 + }
719 + else
720 + {
721 + if (target_big_endian)
722 + offset_expr.X_add_number += off;
723 + while (off-- >= 0)
724 + {
725 + macro_build (&offset_expr, "sb", "t,o(b)",
726 + AT, (int) BFD_RELOC_LO16, breg);
727 + macro_build ((expressionS *) NULL, "ror",
728 + "d,w,<", AT, AT, 8);
729 + if (target_big_endian)
730 + --offset_expr.X_add_number;
731 + else
732 + ++offset_expr.X_add_number;
733 + }
734 + }
735 + break;
736 +
737 + case M_USV_Q:
738 + off = 12;
739 + if (offset_expr.X_add_number >= 0x8000 - off)
740 + as_bad (_("operand overflow"));
741 + offset_expr.X_add_number += off;
742 + macro_build (&offset_expr, "svl.q", "?n3x,?o(b)",
743 + vmreg, (int) BFD_RELOC_LO16, breg);
744 + offset_expr.X_add_number -= off;
745 + macro_build (&offset_expr, "svr.q", "?n3x,?o(b)",
746 + vmreg, (int) BFD_RELOC_LO16, breg);
747 + return;
748 +
749 case M_USD_A:
750 ab = 1;
751 case M_USD:
752 @@ -10294,6 +10736,103 @@
753 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
754 case '[': break;
755 case ']': break;
756 +
757 + /* VFPU fields */
758 + case '?':
759 + switch (c = *p++)
760 + {
761 + case '[': break;
762 + case ']': break;
763 + case 'y':
764 + {
765 + if ((*p != '0') && (*p != '1') && (*p != '2') && (*p != '3'))
766 + {
767 + as_bad (_("internal: bad mips opcode : %s %s"),
768 + opc->name, opc->args);
769 + return 0;
770 + }
771 + p++;
772 + }
773 + break;
774 +
775 + case 'o': USE_BITS (VF_MASK_OFFSET, VF_SH_OFFSET); break;
776 +
777 + case 's':
778 + case 't':
779 + case 'd':
780 + case 'v':
781 + case 'x':
782 + case 'm':
783 + case 'n':
784 + {
785 + if ((*p != '0') && (*p != '1') && (*p != '2') && (*p != '3')
786 + && (*p != '5') && (*p != '6') && (*p != '7'))
787 + {
788 + as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"),
789 + *p, opc->name, opc->args);
790 + return 0;
791 + }
792 + p++;
793 +
794 + if ((*p != 's') && (*p != 't') && (*p != 'd')
795 + && (*p != 'y') && (*p != 'x') && (*p != 'z')
796 + && (*p != 'w') && (*p != 'm'))
797 + {
798 + as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"),
799 + *(p - 1), opc->name, opc->args);
800 + }
801 + p++;
802 +
803 + switch (c)
804 + {
805 + case 's': USE_BITS (VF_MASK_VS, VF_SH_VS); break;
806 + case 't': USE_BITS (VF_MASK_VT, VF_SH_VT); break;
807 + case 'd':
808 + case 'v':
809 + case 'x': USE_BITS (VF_MASK_VD, VF_SH_VD); break;
810 + case 'm': USE_BITS (VF_MASK_VML, VF_SH_VML);
811 + USE_BITS (VF_MASK_VMH, VF_SH_VMH); break;
812 + case 'n': USE_BITS (VF_MASK_VNL, VF_SH_VNL);
813 + USE_BITS (VF_MASK_VNH, VF_SH_VNH); break;
814 + }
815 + }
816 + break;
817 +
818 + case 'f': USE_BITS (VF_MASK_CC, VF_SH_CC);
819 + p++; break;
820 +
821 + case 'a': USE_BITS (VF_MASK_CONST, VF_SH_CONST); break;
822 + case 'b': USE_BITS (VF_MASK_SCALE, VF_SH_SCALE); break;
823 + case 'c': USE_BITS (VF_MASK_BCOND, VF_SH_BCOND); break;
824 + case 'e': USE_BITS (VF_MASK_MCOND, VF_SH_MCOND); break;
825 +
826 + case 'i': USE_BITS (VF_MASK_WRAP, VF_SH_WRAP); break;
827 +
828 + case 'q': USE_BITS (VF_MASK_VCD, VF_SH_VCD); break;
829 + case 'r': USE_BITS (VF_MASK_VCS, VF_SH_VCS); break;
830 +
831 + case 'u': USE_BITS (VF_MASK_HFLOAT, VF_SH_HFLOAT); break;
832 +
833 + case 'w': USE_BITS (VF_MASK_ROT, VF_SH_ROT); break;
834 + case 'z': USE_BITS (VF_MASK_RWB, VF_SH_RWB); break;
835 +
836 + case '0': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
837 + case '1': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
838 + case '2': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
839 + case '3': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
840 + case '4': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
841 + case '5': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
842 + case '6': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
843 + case '7': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break;
844 +
845 + default:
846 + as_bad (_("internal: bad mips opcode (unknown extension operand type `?%c'): %s %s"),
847 + c, opc->name, opc->args);
848 + return 0;
849 +
850 + }
851 + break;
852 +
853 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
854 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
855 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
856 @@ -10610,7 +11149,7 @@
857 char c = 0;
858 struct mips_opcode *insn;
859 char *argsStart;
860 - unsigned int regno;
861 + unsigned int regno = 0;
862 unsigned int lastregno;
863 unsigned int destregno = 0;
864 unsigned int lastpos = 0;
865 @@ -10623,6 +11162,9 @@
866 unsigned int rtype;
867 char *dot;
868 long end;
869 + unsigned int vdregno = 0xffff;
870 + char vdregt = 0;
871 + char vdregl = 0;
872
873 insn_error = NULL;
874
875 @@ -11755,6 +12297,1151 @@
876 case 'y': /* ALNV.PS source register. */
877 gas_assert (mips_opts.micromips);
878 goto do_reg;
879 +
880 + /* VFPU fields */
881 + case '?':
882 + switch (*++args)
883 + {
884 + case '[':
885 + case ']':
886 + if (*s++ == *args)
887 + continue;
888 + break;
889 +
890 + case 'y': /* immediate separator */
891 + ++args;
892 + vimm_expr[*args - '0'] = imm_expr;
893 + voffset_expr[*args - '0'] = offset_expr;
894 +
895 + imm_expr.X_op = O_absent;
896 + offset_expr.X_op = O_absent;
897 + imm_reloc[0] = BFD_RELOC_UNUSED;
898 + imm_reloc[1] = BFD_RELOC_UNUSED;
899 + imm_reloc[2] = BFD_RELOC_UNUSED;
900 + offset_reloc[0] = BFD_RELOC_UNUSED;
901 + offset_reloc[1] = BFD_RELOC_UNUSED;
902 + offset_reloc[2] = BFD_RELOC_UNUSED;
903 +
904 + continue;
905 +
906 + case 'o': /* 16 bit offset */
907 + /* Check whether there is only a single bracketed expression
908 + left. If so, it must be the base register and the
909 + constant must be zero. */
910 + if (*s == '(' && strchr (s + 1, '(') == 0)
911 + {
912 + offset_expr.X_op = O_constant;
913 + offset_expr.X_add_number = 0;
914 + continue;
915 + }
916 +
917 + /* If this value won't fit into a 16 bit offset, then go
918 + find a macro that will generate the 32 bit offset
919 + code pattern. */
920 + if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
921 + && (offset_expr.X_op != O_constant
922 + || offset_expr.X_add_number >= 0x8000
923 + || offset_expr.X_add_number < -0x8000))
924 + break;
925 +
926 + s = expr_end;
927 + continue;
928 +
929 + case 's': /* VFPU source register */
930 + case 't': /* VFPU target register */
931 + case 'd': /* VFPU destination register */
932 + case 'v': /* VFPU destination register */
933 + case 'x': /* VFPU destination register */
934 + case 'm': /* VFPU target regsiter (load/store) */
935 + case 'n': /* VFPU target regsiter (load/store) */
936 + {
937 + int dtype_err = 0;
938 + int dnum_err = 0;
939 + int dlen = 0;
940 + char dtype = s[0];
941 + char regtype = *(args + 1);
942 +
943 + int mtx = 0;
944 + int idx = 0;
945 + int rxc = 0;
946 + int fsl = 0;
947 + int vidx = 0;
948 + int vfsl = 0;
949 +
950 + if (ISDIGIT (s[1]))
951 + {
952 + int num = 0;
953 + s++;
954 + do
955 + {
956 + num *= 10;
957 + num += *s - '0';
958 + dlen++;
959 + s++;
960 + }
961 + while (ISDIGIT (*s));
962 +
963 + if ((s[0] == '.')
964 + && (s[1] == 's' || s[1] == 'p'
965 + || s[1] == 't' || s[1] == 'q'))
966 + s += 2;
967 +
968 + if (ISUPPER(dtype))
969 + dtype -= 'A' - 'a';
970 +
971 + if (dtype == '$')
972 + {
973 + regno = num;
974 + if (regno > VF_MAX_MR)
975 + as_bad (_("Invalid VFPU register number (%d)"),
976 + regno);
977 +
978 + idx = (num >> VF_SH_MR_IDX) & VF_MASK_MR_IDX;
979 + vfsl = (num >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL;
980 + switch (regtype)
981 + {
982 + case '0': /* single word */
983 + break;
984 + case '1': /* pare word */
985 + dnum_err = (vfsl & 0x1);
986 + break;
987 + case '2': /* triple word */
988 + dnum_err = (vfsl > 1);
989 + break;
990 + case '3': /* quad word */
991 + dnum_err = (vfsl > 0);
992 + break;
993 + case '5': /* 2x2 word */
994 + dnum_err = (vfsl & 0x1) || (idx & 0x1);
995 + break;
996 + case '6': /* 3x3 word */
997 + dnum_err = (vfsl > 1) || (idx > 1);
998 + break;
999 + case '7': /* 4x4 word */
1000 + dnum_err = (vfsl > 0) || (idx > 0);
1001 + break;
1002 + }
1003 +
1004 + if (dnum_err)
1005 + as_bad (_("Improper VFPU register number (%d)"),
1006 + regno);
1007 +
1008 + }
1009 + else if ((dlen == 3)
1010 + && ((dtype == 's')
1011 + || (dtype == 'c') || (dtype == 'r')
1012 + || (dtype == 'm') || (dtype == 'e')))
1013 + {
1014 + mtx = num / 100;
1015 + if ((dtype == 'r') || (dtype == 'e'))
1016 + {
1017 + vfsl = (num / 10) % 10;
1018 + vidx = num % 10;
1019 + rxc = 1;
1020 + }
1021 + else
1022 + {
1023 + vidx = (num / 10) % 10;
1024 + vfsl = num % 10;
1025 + rxc = 0;
1026 + }
1027 +
1028 + switch (regtype)
1029 + {
1030 + case '0': /* single word */
1031 + idx = vidx;
1032 + fsl = vfsl;
1033 + dtype_err = (dtype != 's');
1034 + break;
1035 + case '1': /* pare word */
1036 + idx = vidx;
1037 + fsl = (vfsl & 0x2) | rxc;
1038 + dnum_err = (vfsl & 0x1);
1039 + dtype_err = (dtype != 'c') && (dtype != 'r');
1040 + break;
1041 + case '2': /* triple word */
1042 + idx = vidx;
1043 + fsl = ((vfsl & 0x1) << 1) | rxc;
1044 + dnum_err = (vfsl > 1);
1045 + dtype_err = (dtype != 'c') && (dtype != 'r');
1046 + break;
1047 + case '3': /* quad word */
1048 + idx = vidx;
1049 + fsl = rxc;
1050 + dnum_err = (vfsl > 0);
1051 + dtype_err = (dtype != 'c') && (dtype != 'r');
1052 + break;
1053 + case '5': /* 2x2 word */
1054 + idx = vidx & 0x2;
1055 + fsl = (vfsl & 0x2) | rxc;
1056 + dnum_err = (vfsl & 0x1) || (vidx & 0x1);
1057 + dtype_err = (dtype != 'm') && (dtype != 'e');
1058 + break;
1059 + case '6': /* 3x3 word */
1060 + idx = vidx & 0x1;
1061 + fsl = ((vfsl & 0x1) << 1) | rxc;
1062 + dnum_err = (vfsl > 1) || (vidx > 1);
1063 + dtype_err = (dtype != 'm') && (dtype != 'e');
1064 + break;
1065 + case '7': /* 4x4 word */
1066 + idx = 0;
1067 + fsl = rxc;
1068 + dnum_err = (vfsl > 0) || (vidx > 0);
1069 + dtype_err = (dtype != 'm') && (dtype != 'e');
1070 + break;
1071 + }
1072 +
1073 + if (dtype_err)
1074 + as_bad (_("Improper VFPU register prefix '%c'"),
1075 + dtype);
1076 + if (dnum_err)
1077 + as_bad (_("Improper VFPU register number (%03d)"),
1078 + num);
1079 +
1080 + if (mtx > VF_MAX_MR_MTX)
1081 + as_bad (_("VFPU matrix range over %d"), mtx);
1082 + if (vidx > VF_MAX_MR_IDX)
1083 + as_bad (_("VFPU index range over %d"), idx);
1084 + if (vfsl > VF_MAX_MR_FSL)
1085 + as_bad (_("VFPU field select range over %d"), fsl);
1086 +
1087 + regno = ((fsl & VF_MASK_MR_FSL) << VF_SH_MR_FSL)
1088 + | ((mtx & VF_MASK_MR_MTX) << VF_SH_MR_MTX)
1089 + | ((idx & VF_MASK_MR_IDX) << VF_SH_MR_IDX);
1090 + }
1091 + else
1092 + {
1093 + as_bad (_("Improper VFPU register prefix '%c'"),
1094 + dtype);
1095 + }
1096 + }
1097 + else
1098 + {
1099 + as_bad (_("bad operand %s"), s);
1100 + }
1101 +
1102 + if ((*args == 'v') || (*args == 'x'))
1103 + {
1104 + vdregno = regno;
1105 + vdregt = regtype;
1106 + vdregl = (*args == 'v');
1107 + }
1108 + else if (vdregno <= VF_MAX_MR)
1109 + {
1110 + static unsigned short used_vreg[8][16] = {
1111 + { 0x0001, 0x0010, 0x0100, 0x1000,
1112 + 0x0002, 0x0020, 0x0200, 0x2000,
1113 + 0x0004, 0x0040, 0x0400, 0x4000,
1114 + 0x0008, 0x0080, 0x0800, 0x8000 },
1115 + { 0x0003, 0x0030, 0x0300, 0x3000,
1116 + 0x0011, 0x0022, 0x0044, 0x0088,
1117 + 0x000c, 0x00c0, 0x0c00, 0xc000,
1118 + 0x1100, 0x2200, 0x4400, 0x8800 },
1119 + { 0x0007, 0x0070, 0x0700, 0x7000,
1120 + 0x0111, 0x0222, 0x0444, 0x0888,
1121 + 0x000e, 0x00e0, 0x0e00, 0xe000,
1122 + 0x1110, 0x2220, 0x4440, 0x8880 },
1123 + { 0x000f, 0x00f0, 0x0f00, 0xf000,
1124 + 0x1111, 0x2222, 0x4444, 0x8888,
1125 + 0x000f, 0x00f0, 0x0f00, 0xf000,
1126 + 0x1111, 0x2222, 0x4444, 0x8888 },
1127 + { 0x0000, 0x0000, 0x0000, 0x0000,
1128 + 0x0000, 0x0000, 0x0000, 0x0000,
1129 + 0x0000, 0x0000, 0x0000, 0x0000,
1130 + 0x0000, 0x0000, 0x0000, 0x0000 },
1131 + { 0x0033, 0x0033, 0x3300, 0x3300,
1132 + 0x0033, 0x0033, 0x00cc, 0x00cc,
1133 + 0x00cc, 0x00cc, 0xcc00, 0xcc00,
1134 + 0x3300, 0x3300, 0xcc00, 0xcc00 },
1135 + { 0x0777, 0x7770, 0x0777, 0x7770,
1136 + 0x0777, 0x0eee, 0x0777, 0x0eee,
1137 + 0x0eee, 0xeee0, 0x0eee, 0xeee0,
1138 + 0x7770, 0xeee0, 0x7770, 0xeee0 },
1139 + { 0xffff, 0xffff, 0xffff, 0xffff,
1140 + 0xffff, 0xffff, 0xffff, 0xffff,
1141 + 0xffff, 0xffff, 0xffff, 0xffff,
1142 + 0xffff, 0xffff, 0xffff, 0xffff },
1143 + };
1144 + int dmtx, smtx;
1145 + int dfsl, sfsl;
1146 + int didx, sidx;
1147 + int drxc, srxc;
1148 +
1149 + dmtx = (vdregno >> VF_SH_MR_MTX) & VF_MASK_MR_MTX;
1150 + smtx = (regno >> VF_SH_MR_MTX) & VF_MASK_MR_MTX;
1151 +
1152 + if (dmtx == smtx)
1153 + {
1154 + unsigned short dused, sused;
1155 + int dtype2, stype;
1156 +
1157 + dfsl = (vdregno >> VF_SH_MR_FSL) & VF_MASK_MR_FSL;
1158 + didx = (vdregno >> VF_SH_MR_IDX) & VF_MASK_MR_IDX;
1159 + drxc = (vdregno >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
1160 + sfsl = (regno >> VF_SH_MR_FSL) & VF_MASK_MR_FSL;
1161 + sidx = (regno >> VF_SH_MR_IDX) & VF_MASK_MR_IDX;
1162 + srxc = (regno >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
1163 +
1164 + dtype2 = vdregt - '0';
1165 + stype = regtype - '0';
1166 + dused = used_vreg[dtype2][(dfsl << 2) + didx];
1167 + sused = used_vreg[stype][(sfsl << 2) + sidx];
1168 +
1169 + if ((dused & sused)
1170 + && (vdregl || (dused ^ sused) || (drxc != srxc)))
1171 + {
1172 + int dvfsl;
1173 + dvfsl = (vdregno >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL;
1174 + switch (vdregt)
1175 + {
1176 + case '1':
1177 + dvfsl <<= 1;
1178 + case '2':
1179 + case '3':
1180 + if (drxc)
1181 + as_bad (_("VFPU register conflict(R%d%d%d)"),
1182 + dmtx, dvfsl, didx);
1183 + else
1184 + as_bad (_("VFPU register conflict(C%d%d%d)"),
1185 + dmtx, didx, dvfsl);
1186 + break;
1187 + case '5':
1188 + dvfsl <<= 1;
1189 + case '6':
1190 + case '7':
1191 + if (drxc)
1192 + as_bad (_("VFPU register conflict(E%d%d%d)"),
1193 + dmtx, dvfsl, didx);
1194 + else
1195 + as_bad (_("VFPU register conflict(M%d%d%d)"),
1196 + dmtx, didx, dvfsl);
1197 + break;
1198 + }
1199 + }
1200 + }
1201 + }
1202 +
1203 + switch (*args++)
1204 + {
1205 + case 's':
1206 + if (
1207 + (ip->insn_opcode
1208 + & VFPU_MASK_RPT_MMUL) == VFPU_INST_RPT_MMUL)
1209 + {
1210 + if (regno & (VF_MASK_MR_RXC << VF_SH_MR_RXC))
1211 + regno &= ~(VF_MASK_MR_RXC << VF_SH_MR_RXC);
1212 + else
1213 + regno |= (VF_MASK_MR_RXC << VF_SH_MR_RXC);
1214 + }
1215 + ip->insn_opcode |= (regno & VF_MASK_VS) << VF_SH_VS;
1216 + break;
1217 + case 't':
1218 + ip->insn_opcode |= (regno & VF_MASK_VT) << VF_SH_VT;
1219 + break;
1220 + case 'd':
1221 + case 'v':
1222 + case 'x':
1223 + ip->insn_opcode |= (regno & VF_MASK_VD) << VF_SH_VD;
1224 + break;
1225 + case 'm':
1226 + {
1227 + int vmregL = (regno >> 0) & VF_MASK_VML;
1228 + int vmregH = (regno >> 5) & VF_MASK_VMH;
1229 + ip->insn_opcode |= (vmregL << VF_SH_VML)
1230 + | (vmregH << VF_SH_VMH);
1231 + }
1232 + break;
1233 + case 'n':
1234 + {
1235 + int vmregL = (regno >> 0) & VF_MASK_VNL;
1236 + int vmregH = (regno >> 5) & VF_MASK_VNH;
1237 + ip->insn_opcode |= (vmregL << VF_SH_VNL)
1238 + | (vmregH << VF_SH_VNH);
1239 + }
1240 + break;
1241 + }
1242 + args++;
1243 +
1244 + /* now check for vfpu prefixes if necessary */
1245 + if (*s == '[')
1246 + {
1247 + char *prefix_out = NULL;
1248 + bfd_boolean *prefix_bool = NULL;
1249 + char *prefix_type = NULL;
1250 + int num_args = 0;
1251 + char *ob = ++s;
1252 + bfd_boolean has_w = FALSE;
1253 + bfd_boolean has_z = FALSE;
1254 + bfd_boolean has_y = FALSE;
1255 + bfd_boolean has_operator = FALSE;
1256 + bfd_boolean has_saturater = FALSE;
1257 +
1258 + switch (*args)
1259 + {
1260 + case 'w': /* only swizzle */
1261 + case 's': /* source prefix */
1262 + prefix_bool = &vfpu_sprefix;
1263 + prefix_out = vfpu_sprefix_str;
1264 + prefix_type = "source";
1265 + break;
1266 + case 't': /* target prefix */
1267 + prefix_bool = &vfpu_tprefix;
1268 + prefix_out = vfpu_tprefix_str;
1269 + prefix_type = "target";
1270 + break;
1271 + case 'm': /* only write mask */
1272 + case 'd': /* destination prefix */
1273 + prefix_bool = &vfpu_dprefix;
1274 + prefix_out = vfpu_dprefix_str;
1275 + prefix_type = "destination";
1276 + break;
1277 + case 'y': /* inhibit */
1278 + prefix_bool = NULL;
1279 + prefix_type = "source";
1280 + break;
1281 + case 'x': /* inhibit */
1282 + prefix_bool = NULL;
1283 + prefix_type = "target";
1284 + break;
1285 + case 'z': /* inhibit */
1286 + prefix_bool = NULL;
1287 + prefix_type = "destination";
1288 + break;
1289 + }
1290 +
1291 + for ( ; *s != '\0' && *s != ']'; s++)
1292 + {
1293 + switch (*s)
1294 + {
1295 + case ',':
1296 + /* count no. of params for syntax check */
1297 + num_args++;
1298 + break;
1299 + case ' ':
1300 + case '\t':
1301 + break;
1302 + case 'm':
1303 + case 'M':
1304 + case 'x':
1305 + case 'X':
1306 + break;
1307 + case 'y':
1308 + case 'Y':
1309 + has_y = TRUE;
1310 + break;
1311 + case 'z':
1312 + case 'Z':
1313 + has_z = TRUE;
1314 + break;
1315 + case 'w':
1316 + case 'W':
1317 + has_w = TRUE;
1318 + break;
1319 + default:
1320 + if (*args == 'w')
1321 + has_operator = TRUE;
1322 + if (*args == 'm')
1323 + has_saturater = TRUE;
1324 + }
1325 + }
1326 +
1327 + if (*s == ']')
1328 + {
1329 + if (prefix_bool)
1330 + {
1331 + *prefix_bool = TRUE;
1332 + strncpy (prefix_out, ob, s - ob);
1333 + prefix_out[s - ob] = '\0';
1334 + s++;
1335 + }
1336 + else
1337 + {
1338 + as_bad (_("%s cannot use %s prefix"),
1339 + insn->name, prefix_type);
1340 + s++;
1341 + continue;
1342 + }
1343 + }
1344 + else
1345 + {
1346 + as_bad (_("parse error (%s)"), ob - 1);
1347 + return;
1348 + }
1349 +
1350 + if (num_args != regtype - '0')
1351 + {
1352 + as_bad (_("%s prefix specification requires %d parameters - [%s]"),
1353 + prefix_type, regtype - '0' + 1,
1354 + prefix_out);
1355 + }
1356 + else
1357 + {
1358 + int i = 8 - ((3 - num_args) * 2);
1359 + char dummy_d[] = " m,m,m,m";
1360 + char dummy_st[] = " x,y,z,w";
1361 +
1362 + if (*args == 'd' || *args == 'm')
1363 + {
1364 + strcat (prefix_out, dummy_d + i);
1365 + if (has_saturater)
1366 + {
1367 + as_bad (_("%s is restricted to mask destination prefixes only"),
1368 + insn->name);
1369 + }
1370 + }
1371 + else
1372 + {
1373 + strcat (prefix_out, dummy_st + i);
1374 + if (has_operator)
1375 + {
1376 + as_bad (_("%s is restricted to swizzle %s prefixes only"),
1377 + insn->name, prefix_type);
1378 + }
1379 + /* semantic check, w can't be specified for
1380 + s, p, or t instructions same goes for
1381 + z for p and s, and y for scalars */
1382 + if ((has_y && num_args == 0)
1383 + || (has_z && num_args < 2)
1384 + || (has_w && num_args < 3))
1385 + {
1386 + as_bad (_("%s swizzle operand is out of range in [%s]"),
1387 + prefix_type, prefix_out);
1388 + }
1389 + }
1390 + }
1391 + }
1392 +
1393 + continue;
1394 + }
1395 + break;
1396 +
1397 + case 'q': /* VFPU destination control register */
1398 + case 'r': /* VFPU source control register */
1399 + {
1400 + if ((s[0] == '$') && ISDIGIT (s[1]))
1401 + {
1402 + s++;
1403 + regno = 0;
1404 + do
1405 + {
1406 + regno *= 10;
1407 + regno += *s - '0';
1408 + ++s;
1409 + }
1410 + while (ISDIGIT (*s));
1411 +
1412 + if ((regno < VF_MIN_CR) || (regno > VF_MAX_CR))
1413 + as_bad (_("Invalid VFPU control register number (%d)"),
1414 + regno);
1415 +
1416 + else if (!((regno >= VF_MIN_VCR) && (regno <= VF_MAX_VCR)))
1417 + as_bad (_("Improper VFPU control register number (%d)"),
1418 + regno);
1419 +
1420 + switch (*args)
1421 + {
1422 + case 'q':
1423 + ip->insn_opcode |= (regno & VF_MASK_VCD) << VF_SH_VCD;
1424 + break;
1425 + case 'r':
1426 + ip->insn_opcode |= (regno & VF_MASK_VCS) << VF_SH_VCS;
1427 + break;
1428 + }
1429 + }
1430 + else
1431 + {
1432 + as_bad (_("Invalid VFPU control register name (%s)"), s);
1433 + }
1434 +
1435 + continue;
1436 + }
1437 + break;
1438 +
1439 + case 'f': /* condition code */
1440 + {
1441 + int cond = 0;
1442 + if (ISDIGIT (s[0]))
1443 + {
1444 + my_getExpression (&imm_expr, s);
1445 + check_absolute_expr (ip, &imm_expr);
1446 + cond = imm_expr.X_add_number;
1447 + if ((cond < VF_MIN_CC) || (cond > VF_MAX_CC))
1448 + as_bad (_("Invalid VFPU condition code (%d)"), cond);
1449 + imm_expr.X_op = O_absent;
1450 + s = expr_end;
1451 + }
1452 + else
1453 + {
1454 + static const char * const vfpu_cond_names[] = {
1455 + "FL", "EQ", "LT", "LE",
1456 + "TR", "NE", "GE", "GT",
1457 + "EZ", "EN", "EI", "ES",
1458 + "NZ", "NN", "NI", "NS" };
1459 + for (cond = VF_MIN_CC; cond <= VF_MAX_CC; cond++)
1460 + {
1461 + if (strncasecmp(vfpu_cond_names[cond], s, 2) == 0)
1462 + break;
1463 + }
1464 + if ((cond < VF_MIN_CC) || (cond > VF_MAX_CC))
1465 + as_bad (_("Invalid VFPU condition code (%s)"), s);
1466 +
1467 + s += 2;
1468 + }
1469 +
1470 + args++;
1471 + if ((cond == 0) || (cond == 4))
1472 + {
1473 + }
1474 + else if (cond & 0x8)
1475 + {
1476 + if (*args - '0' < 1)
1477 + as_bad (_("Invalid VFPU condition oparetion"));
1478 + }
1479 + else
1480 + {
1481 + if (*args - '0' < 2)
1482 + as_bad (_("Invalid VFPU condition oparetion"));
1483 + }
1484 +
1485 + ip->insn_opcode |= (cond & VF_MASK_CC) << VF_SH_CC;
1486 + continue;
1487 + }
1488 + break;
1489 +
1490 + case 'a': /* constant code */
1491 + {
1492 + int cst = 0;
1493 + if (ISDIGIT (s[0]))
1494 + {
1495 + my_getExpression (&imm_expr, s);
1496 + check_absolute_expr (ip, &imm_expr);
1497 + cst = imm_expr.X_add_number;
1498 + if ((cst < VF_MIN_CONST) || (cst > VF_MAX_CONST))
1499 + {
1500 + as_bad (_("Improper constant code (%d)"), cst);
1501 + cst &= VF_MASK_CONST;
1502 + }
1503 + imm_expr.X_op = O_absent;
1504 + s = expr_end;
1505 + }
1506 + else
1507 + {
1508 + static const char * const vfpu_const_names[] = {
1509 + "", "VFPU_HUGE", "VFPU_SQRT2", "VFPU_SQRT1_2",
1510 + "VFPU_2_SQRTPI", "VFPU_2_PI", "VFPU_1_PI", "VFPU_PI_4",
1511 + "VFPU_PI_2", "VFPU_PI", "VFPU_E", "VFPU_LOG2E",
1512 + "VFPU_LOG10E", "VFPU_LN2", "VFPU_LN10", "VFPU_2PI",
1513 + "VFPU_PI_6", "VFPU_LOG10TWO", "VFPU_LOG2TEN",
1514 + "VFPU_SQRT3_2"};
1515 + for (cst = VF_MIN_CONST; cst <= VF_MAX_CONST; cst++)
1516 + {
1517 + if (strcasecmp(vfpu_const_names[cst], s) == 0)
1518 + break;
1519 + }
1520 + if ((cst < VF_MIN_CONST) || (cst > VF_MAX_CONST))
1521 + as_bad (_("Invalid constant code (%s)"), s);
1522 + else
1523 + s += strlen(vfpu_const_names[cst]);
1524 + }
1525 +
1526 + ip->insn_opcode |= cst << VF_SH_CONST;
1527 + }
1528 + continue;
1529 +
1530 + case 'b': /* scale exponent */
1531 + my_getExpression (&imm_expr, s);
1532 + check_absolute_expr (ip, &imm_expr);
1533 + if ((unsigned long) imm_expr.X_add_number > VF_MAX_SCALE)
1534 + {
1535 + as_bad (_("Improper scale (%lu)"),
1536 + (unsigned long) imm_expr.X_add_number);
1537 + imm_expr.X_add_number &= VF_MASK_SCALE;
1538 + }
1539 + ip->insn_opcode |= imm_expr.X_add_number << VF_SH_SCALE;
1540 + imm_expr.X_op = O_absent;
1541 + s = expr_end;
1542 + continue;
1543 +
1544 + case 'c': /* branch condition code bit */
1545 + my_getExpression (&imm_expr, s);
1546 + check_absolute_expr (ip, &imm_expr);
1547 + if ((unsigned long) imm_expr.X_add_number > VF_MAX_BCOND)
1548 + {
1549 + as_bad (_("Improper condition bit (%lu)"),
1550 + (unsigned long) imm_expr.X_add_number);
1551 + imm_expr.X_add_number &= VF_MASK_BCOND;
1552 + }
1553 + ip->insn_opcode |= imm_expr.X_add_number << VF_SH_BCOND;
1554 + imm_expr.X_op = O_absent;
1555 + s = expr_end;
1556 + continue;
1557 +
1558 + case 'e': /* move condition code bit */
1559 + my_getExpression (&imm_expr, s);
1560 + check_absolute_expr (ip, &imm_expr);
1561 + if ((unsigned long) imm_expr.X_add_number > VF_MAX_MCOND)
1562 + {
1563 + as_bad (_("Improper condition bit (%lu)"),
1564 + (unsigned long) imm_expr.X_add_number);
1565 + imm_expr.X_add_number &= VF_MASK_MCOND;
1566 + }
1567 + ip->insn_opcode |= imm_expr.X_add_number << VF_SH_MCOND;
1568 + imm_expr.X_op = O_absent;
1569 + s = expr_end;
1570 + continue;
1571 +
1572 + case 'i': /* wrap exponent */
1573 + my_getExpression (&imm_expr, s);
1574 + check_absolute_expr (ip, &imm_expr);
1575 + if ((unsigned long) imm_expr.X_add_number > VF_MAX_WRAP)
1576 + {
1577 + as_bad (_("Improper wrap (%lu)"),
1578 + (unsigned long) imm_expr.X_add_number);
1579 + imm_expr.X_add_number &= VF_MASK_WRAP;
1580 + }
1581 + ip->insn_opcode |= imm_expr.X_add_number << VF_SH_WRAP;
1582 + imm_expr.X_op = O_absent;
1583 + s = expr_end;
1584 + continue;
1585 +
1586 + case 'w': /* rotation code */
1587 + if (s[0] == '[')
1588 + {
1589 + char *rot_str = s;
1590 + int rot_idx = 0;
1591 + int rot_neg = 0;
1592 + int rot_sin = 3;
1593 + int rot_cos = 3;
1594 + int rot_err = 0;
1595 + int rot_n;
1596 + int rot_neg_n = 0;
1597 + int rot_sin_n = 0;
1598 + int rot_cos_n = 0;
1599 + int rot_code;
1600 +
1601 + if ((ip->insn_opcode & VFPU_MASK_DTYPE) == VFPU_PAIR)
1602 + rot_n = 2;
1603 + else if ((ip->insn_opcode & VFPU_MASK_DTYPE) == VFPU_TRIPLE)
1604 + rot_n = 3;
1605 + else if ((ip->insn_opcode & VFPU_MASK_DTYPE) == VFPU_QUAD)
1606 + rot_n = 4;
1607 + else
1608 + rot_n = 0;
1609 +
1610 + s++;
1611 + while ((s[0] != ']') && (s[0] != '\0'))
1612 + {
1613 + if (s[0] == '-')
1614 + {
1615 + if ((s[1] != 's') && (s[1] != 'S'))
1616 + {
1617 + rot_err = 1;
1618 + break;
1619 + }
1620 + rot_neg = 1;
1621 + rot_neg_n++;
1622 + s++;
1623 + }
1624 +
1625 + if (s[0] == ',')
1626 + rot_idx++;
1627 + else if ((s[0] == 'c') || (s[0] == 'C'))
1628 + {
1629 + rot_cos = rot_idx;
1630 + rot_cos_n++;
1631 + }
1632 + else if ((s[0] == 's') || (s[0] == 'S'))
1633 + {
1634 + rot_sin = rot_idx;
1635 + rot_sin_n++;
1636 + }
1637 + else if (ISSPACE(s[0]) || (s[0] == '0'))
1638 + ;
1639 + else
1640 + {
1641 + rot_err = 1;
1642 + break;
1643 + }
1644 +
1645 + s++;
1646 + }
1647 +
1648 + if (s[0] == ']')
1649 + rot_idx++;
1650 + else
1651 + rot_err = 1;
1652 + s++;
1653 +
1654 + if ((rot_sin_n == 0) && (rot_cos_n == 0))
1655 + {
1656 + if (rot_n == 2)
1657 + rot_sin = 2;
1658 + else if ((rot_n == 4) || (rot_n == 3))
1659 + rot_err = 1;
1660 + }
1661 +
1662 + if (rot_cos_n > 1)
1663 + rot_err = 1;
1664 +
1665 + if (rot_sin_n > 1)
1666 + {
1667 + if (((rot_sin_n + rot_cos_n) != rot_n)
1668 + || ((rot_n == 4) && (rot_cos_n == 0)))
1669 + rot_err = 1;
1670 + }
1671 +
1672 + if (rot_neg && (rot_neg_n != rot_sin_n))
1673 + rot_err = 1;
1674 +
1675 + if (rot_sin_n > 1)
1676 + rot_sin = rot_cos;
1677 +
1678 + if (rot_err || (rot_n != rot_idx))
1679 + as_bad (_("Invalid rotation code (%s)"), rot_str);
1680 +
1681 + rot_code = ((rot_neg & VF_MASK_ROT_NEG) << VF_SH_ROT_NEG)
1682 + | ((rot_cos & VF_MASK_ROT_COS) << VF_SH_ROT_COS)
1683 + | ((rot_sin & VF_MASK_ROT_SIN) << VF_SH_ROT_SIN);
1684 + ip->insn_opcode |= rot_code << VF_SH_ROT;
1685 + }
1686 + else
1687 + {
1688 + my_getExpression (&imm_expr, s);
1689 + check_absolute_expr (ip, &imm_expr);
1690 + if ((unsigned long) imm_expr.X_add_number > VF_MAX_ROT)
1691 + {
1692 + as_bad (_("Improper rotation code (%lu)"),
1693 + (unsigned long) imm_expr.X_add_number);
1694 + imm_expr.X_add_number &= VF_MASK_ROT;
1695 + }
1696 + ip->insn_opcode |= imm_expr.X_add_number << VF_SH_ROT;
1697 + imm_expr.X_op = O_absent;
1698 + s = expr_end;
1699 + }
1700 + continue;
1701 +
1702 + case 'u': /* half float */
1703 + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
1704 + {
1705 + my_getExpression (&imm_expr, s);
1706 + check_absolute_expr (ip, &imm_expr);
1707 + if ((unsigned long) imm_expr.X_add_number > VF_MAX_HFLOAT)
1708 + {
1709 + as_bad (_("Improper half floating point constant: (%lu)"),
1710 + (unsigned long) imm_expr.X_add_number);
1711 + imm_expr.X_add_number &= VF_MASK_HFLOAT;
1712 + }
1713 + ip->insn_opcode |= imm_expr.X_add_number << VF_SH_HFLOAT;
1714 + imm_expr.X_op = O_absent;
1715 + s = expr_end;
1716 + continue;
1717 + }
1718 + else
1719 + {
1720 + char *save_in;
1721 + char *err;
1722 + int len;
1723 + unsigned char temp[8];
1724 + unsigned int f32, f16;
1725 + int exponent32, exponent16;
1726 + int fraction32, fraction16;
1727 + int sign;
1728 + char f16_str[8];
1729 +
1730 + save_in = input_line_pointer;
1731 + input_line_pointer = s;
1732 + err = md_atof ('f', (char *) temp, &len);
1733 + s = input_line_pointer;
1734 + input_line_pointer = save_in;
1735 + if (err != NULL && *err != '\0')
1736 + {
1737 + as_bad (_("Bad half floating point constant: %s"), err);
1738 + memset (temp, '\0', sizeof temp);
1739 + }
1740 +
1741 + if (! target_big_endian)
1742 + f32 = bfd_getl32 (temp);
1743 + else
1744 + f32 = bfd_getb32 (temp);
1745 +
1746 + sign = (f32 >> VF_SH_F32_SIGN) & VF_MASK_F32_SIGN;
1747 + exponent32 = (f32 >> VF_SH_F32_EXP) & VF_MASK_F32_EXP;
1748 + fraction32 = (f32 >> VF_SH_F32_FRA) & VF_MASK_F32_FRA;
1749 + exponent16 = exponent32
1750 + - VF_BIAS_F32_EXP + VF_BIAS_F16_EXP;
1751 +
1752 + if (exponent16 < VF_MIN_F16_EXP)
1753 + {
1754 + if ((exponent32 == VF_MIN_F32_EXP)
1755 + && (fraction32 == 0))
1756 + { // zero
1757 + exponent16 = VF_MIN_F16_EXP;
1758 + fraction16 = 0;
1759 + }
1760 + else
1761 + { // underflow
1762 + float* p;
1763 + p = (float*) &f32;
1764 + as_warn (_("Half floating point underflow: %g"),
1765 + *p);
1766 + exponent16 = VF_MIN_F16_EXP;
1767 + fraction16 = 0;
1768 + }
1769 + }
1770 + else if (exponent16 > VF_MAX_F16_EXP)
1771 + {
1772 + if (exponent32 != VF_MAX_F32_EXP)
1773 + { // overflow
1774 + float* p;
1775 + p = (float*) &f32;
1776 + as_warn (_("Half floating point overflow: %g"),
1777 + *p);
1778 + exponent16 = VF_MAX_F16_EXP;
1779 + fraction16 = 0;
1780 + }
1781 + else
1782 + {
1783 + if (fraction32 == 0)
1784 + { // infinity
1785 + exponent16 = VF_MAX_F16_EXP;
1786 + fraction16 = 0;
1787 + }
1788 + else
1789 + { // NaN
1790 + exponent16 = VF_MAX_F16_EXP;
1791 + fraction16 = 1;
1792 + }
1793 + }
1794 + }
1795 + else
1796 + {
1797 + fraction16 = (f32 >> (VF_SH_F32_EXP - VF_SH_F16_EXP))
1798 + & VF_MASK_F16_FRA;
1799 + }
1800 +
1801 + f16 = (sign << VF_SH_F16_SIGN)
1802 + | (exponent16 << VF_SH_F16_EXP)
1803 + | (fraction16 << VF_SH_F16_FRA);
1804 + ip->insn_opcode |= (f16 & VF_MASK_HFLOAT) << VF_SH_HFLOAT;
1805 +
1806 + sprintf(f16_str, "0x%04x", f16);
1807 + my_getExpression (&imm_expr, f16_str);
1808 +
1809 + continue;
1810 + }
1811 + break;
1812 +
1813 + case 'z': /* read/write access code */
1814 + {
1815 + int rwb = 0;
1816 +
1817 + if (strncasecmp (s, "WT", 2) == 0)
1818 + rwb = 0x0;
1819 + else if (strncasecmp (s, "WB", 2) == 0)
1820 + rwb = 0x1;
1821 + else
1822 + as_bad (_("Invalid memory access type (%s)"), s);
1823 +
1824 + s += 2;
1825 + ip->insn_opcode |= (rwb & VF_MASK_RWB) << VF_SH_RWB;
1826 +
1827 + continue;
1828 + }
1829 +
1830 + case '0': /* source or target prefix code (X) */
1831 + case '1': /* source or target prefix code (Y) */
1832 + case '2': /* source or target prefix code (Z) */
1833 + case '3': /* source or target prefix code (W) */
1834 + {
1835 + int operand;
1836 + int shift;
1837 +
1838 + int pfx_neg = 0;
1839 + int pfx_cst = 0;
1840 + int pfx_abs = 0;
1841 + int pfx_swz = 0;
1842 + int pfx_err = 0;
1843 + int cst = 0;
1844 + char *pfx_str = s;
1845 +
1846 + if (s[0] == '-')
1847 + { // sign code
1848 + pfx_neg = 1;
1849 + s++;
1850 + }
1851 +
1852 + if (ISDIGIT (s[0]))
1853 + { // constant
1854 + pfx_cst = 1;
1855 +
1856 + if (s[0] == '0')
1857 + cst = 0;
1858 + else if (s[0] == '1')
1859 + {
1860 + if (s[1] == '/')
1861 + {
1862 + s += 2;
1863 + if (s[0] == '2')
1864 + cst = 3;
1865 + else if (s[0] == '3')
1866 + cst = 5;
1867 + else if (s[0] == '4')
1868 + cst = 6;
1869 + else if (s[0] == '6')
1870 + cst = 7;
1871 + else
1872 + pfx_err = 1;
1873 + }
1874 + else
1875 + {
1876 + cst = 1;
1877 + }
1878 + }
1879 + else if (s[0] == '2')
1880 + cst = 2;
1881 + else if (s[0] == '3')
1882 + cst = 4;
1883 + else
1884 + pfx_err = 1;
1885 +
1886 + pfx_abs = (cst >> 2) & 0x1;
1887 + pfx_swz = (cst >> 0) & 0x3;
1888 + s++;
1889 + }
1890 + else
1891 + { // variable
1892 +
1893 + if (s[0] == '|')
1894 + { // abs
1895 + pfx_abs = 1;
1896 + s++;
1897 + }
1898 +
1899 + if ((s[0] == 'X') || (s[0] == 'x'))
1900 + {
1901 + pfx_swz = 0;
1902 + s++;
1903 + }
1904 + else if ((s[0] == 'Y') || (s[0] == 'y'))
1905 + {
1906 + pfx_swz = 1;
1907 + s++;
1908 + }
1909 + else if ((s[0] == 'Z') || (s[0] == 'z'))
1910 + {
1911 + pfx_swz = 2;
1912 + s++;
1913 + }
1914 + else if ((s[0] == 'W') || (s[0] == 'w'))
1915 + {
1916 + pfx_swz = 3;
1917 + s++;
1918 + }
1919 + else if ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])
1920 + || (s[0] == '|'))
1921 + {
1922 + pfx_swz = *args - '0';
1923 + }
1924 + else
1925 + pfx_err = 1;
1926 +
1927 + if (pfx_err == 0)
1928 + {
1929 + if (s[0] == '|')
1930 + {
1931 + s++;
1932 + if (pfx_abs == 0)
1933 + pfx_err = 1;
1934 + }
1935 + else
1936 + {
1937 + if (pfx_abs == 1)
1938 + pfx_err = 1;
1939 + }
1940 + }
1941 + }
1942 +
1943 + if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])))
1944 + pfx_err = 1;
1945 +
1946 + if (pfx_err)
1947 + as_bad (_("Invalid prefix format (%s)"), pfx_str);
1948 +
1949 + shift = *args - '0';
1950 +
1951 + operand = (pfx_neg << (VF_SH_PFX_NEG + shift))
1952 + | (pfx_cst << (VF_SH_PFX_CST + shift))
1953 + | (pfx_abs << (VF_SH_PFX_ABS + shift))
1954 + | (pfx_swz << (VF_SH_PFX_SWZ + shift * 2));
1955 +
1956 + ip->insn_opcode |= operand;
1957 + continue;
1958 + }
1959 +
1960 + case '4': /* destination prefix code (X) */
1961 + case '5': /* destination prefix code (Y) */
1962 + case '6': /* destination prefix code (Z) */
1963 + case '7': /* destination prefix code (W) */
1964 + {
1965 + int operand;
1966 + int shift;
1967 + static const char order[] = "xyzwXYZW";
1968 +
1969 + int pfx_msk = 0;
1970 + int pfx_sat = 0;
1971 + char *pfx_str = s;
1972 +
1973 + if (s[0] == '[')
1974 + s++;
1975 + if (s[0] == '-') /* -1:1, skip the minus symbol */
1976 + s++;
1977 +
1978 + if ((s[0] == 'm') || (s[0] == 'M'))
1979 + {
1980 + pfx_msk = 1;
1981 + s++;
1982 + }
1983 + else if (s[0] == '0') /* 0:1 */
1984 + {
1985 + pfx_sat = 1;
1986 + s++;
1987 + }
1988 + else if (s[0] == '1') /* -1:1 or -1:+1 */
1989 + {
1990 + pfx_sat = 3;
1991 + s++;
1992 + }
1993 + else if ((s[0] == order[(*args) - '4'])
1994 + || (s[0] == order[(*args) - '4' + 4]))
1995 + {
1996 + pfx_sat = 0;
1997 + s++;
1998 + }
1999 +
2000 + if (s[0] == ':') /* skip the :1 or :+1 part of the expression */
2001 + {
2002 + s++;
2003 + if (s[0] == '+')
2004 + s++;
2005 + if (s[0] == '1')
2006 + s++;
2007 + }
2008 + if (s[0] == ']')
2009 + s++;
2010 +
2011 + if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])))
2012 + as_bad (_("Invalid prefix format (%s)"), pfx_str);
2013 +
2014 + shift = *args - '4';
2015 + operand = (pfx_msk << (VF_SH_PFX_MSK + shift))
2016 + | (pfx_sat << (VF_SH_PFX_SAT + shift * 2));
2017 +
2018 + ip->insn_opcode |= operand;
2019 + continue;
2020 + }
2021 + }
2022 + break;
2023 +
2024 case 'x': /* Ignore register name. */
2025 case 'U': /* Destination register (CLO/CLZ). */
2026 case 'g': /* Coprocessor destination register. */
2027 @@ -11949,6 +13636,7 @@
2028 {
2029 if ((regno & 1) != 0
2030 && HAVE_32BIT_FPRS
2031 + && ! CPU_IS_ALLEGREX (mips_opts.arch)
2032 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
2033 as_warn (_("Float register should be even, was %d"),
2034 regno);
2035 @@ -19045,6 +20733,8 @@
2036
2037 /* MIPS II */
2038 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
2039 + /* Sony PSP "Allegrex" CPU core */
2040 + { "allegrex", 0, ISA_MIPS2, CPU_ALLEGREX },
2041
2042 /* MIPS III */
2043 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
2044 diff -NrU3 binutils-2.23.2/gas/configure binutils-2.23.2-patched/gas/configure
2045 --- binutils-2.23.2/gas/configure 2012-06-18 06:43:06.000000000 +0200
2046 +++ binutils-2.23.2-patched/gas/configure 2020-04-23 17:57:30.327522796 +0200
2047 @@ -12046,6 +12046,9 @@
2048 mips64vr | mips64vrel)
2049 mips_cpu=vr4100
2050 ;;
2051 + mipsallegrex | mipsallegrexel)
2052 + mips_cpu=allegrex
2053 + ;;
2054 mipsisa32r2* | mipsisa64r2*)
2055 mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
2056 ;;
2057 diff -NrU3 binutils-2.23.2/gas/configure.in binutils-2.23.2-patched/gas/configure.in
2058 --- binutils-2.23.2/gas/configure.in 2012-11-05 17:27:44.000000000 +0100
2059 +++ binutils-2.23.2-patched/gas/configure.in 2020-04-23 17:57:30.327522796 +0200
2060 @@ -222,6 +222,9 @@
2061 mips64vr | mips64vrel)
2062 mips_cpu=vr4100
2063 ;;
2064 + mipsallegrex | mipsallegrexel)
2065 + mips_cpu=allegrex
2066 + ;;
2067 mipsisa32r2* | mipsisa64r2*)
2068 changequote(,)dnl
2069 mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
2070 diff -NrU3 binutils-2.23.2/gas/testsuite/gas/mips/mips.exp binutils-2.23.2-patched/gas/testsuite/gas/mips/mips.exp
2071 --- binutils-2.23.2/gas/testsuite/gas/mips/mips.exp 2012-09-04 16:17:13.000000000 +0200
2072 +++ binutils-2.23.2-patched/gas/testsuite/gas/mips/mips.exp 2020-04-23 17:57:30.327522796 +0200
2073 @@ -432,6 +432,9 @@
2074 mips_arch_create sb1 64 mips64 { mips3d } \
2075 { -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
2076 { mipsisa64sb1-*-* mipsisa64sb1el-*-* }
2077 +mips_arch_create allegrex 32 mips2 { ror } \
2078 + { -march=allegrex -mtune=allegrex } { -mmips:allegrex } \
2079 + { mipsallegrex-*-* mipsallegrexel-*-* }
2080 mips_arch_create octeon 64 mips64r2 {} \
2081 { -march=octeon -mtune=octeon } { -mmips:octeon } \
2082 { mips64octeon*-*-* }
2083 diff -NrU3 binutils-2.23.2/include/elf/common.h binutils-2.23.2-patched/include/elf/common.h
2084 --- binutils-2.23.2/include/elf/common.h 2012-09-04 14:53:47.000000000 +0200
2085 +++ binutils-2.23.2-patched/include/elf/common.h 2020-04-23 17:57:30.327522796 +0200
2086 @@ -96,6 +96,7 @@
2087 #define ET_HIOS 0xFEFF /* Operating system-specific */
2088 #define ET_LOPROC 0xFF00 /* Processor-specific */
2089 #define ET_HIPROC 0xFFFF /* Processor-specific */
2090 +#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */
2091
2092 /* Values for e_machine, which identifies the architecture. These numbers
2093 are officially assigned by registry@sco.com. See below for a list of
2094 diff -NrU3 binutils-2.23.2/include/elf/mips.h binutils-2.23.2-patched/include/elf/mips.h
2095 --- binutils-2.23.2/include/elf/mips.h 2011-12-19 08:58:02.000000000 +0100
2096 +++ binutils-2.23.2-patched/include/elf/mips.h 2020-04-23 17:57:30.327522796 +0200
2097 @@ -272,6 +272,7 @@
2098 #define E_MIPS_MACH_5400 0x00910000
2099 #define E_MIPS_MACH_5500 0x00980000
2100 #define E_MIPS_MACH_9000 0x00990000
2101 +#define E_MIPS_MACH_ALLEGREX 0x00A20000
2102 #define E_MIPS_MACH_LS2E 0x00A00000
2103 #define E_MIPS_MACH_LS2F 0x00A10000
2104 #define E_MIPS_MACH_LS3A 0x00A20000
2105 diff -NrU3 binutils-2.23.2/include/opcode/mips.h binutils-2.23.2-patched/include/opcode/mips.h
2106 --- binutils-2.23.2/include/opcode/mips.h 2012-09-04 16:21:05.000000000 +0200
2107 +++ binutils-2.23.2-patched/include/opcode/mips.h 2020-04-23 17:57:30.327522796 +0200
2108 @@ -218,6 +218,228 @@
2109 #define MDMX_FMTSEL_VEC_QH 0x15
2110 #define MDMX_FMTSEL_VEC_OB 0x16
2111
2112 +#include "vfpu.h"
2113 +
2114 +#define VF_MASK_VT 0x7f
2115 +#define VF_SH_VT 16
2116 +#define VF_MASK_VS 0x7f
2117 +#define VF_SH_VS 8
2118 +#define VF_MASK_VD 0x7f
2119 +#define VF_SH_VD 0
2120 +#define VF_MASK_VML 0x1f
2121 +#define VF_SH_VML 16
2122 +#define VF_MASK_VMH 0x3
2123 +#define VF_SH_VMH 0
2124 +#define VF_MASK_VNL 0x1f
2125 +#define VF_SH_VNL 16
2126 +#define VF_MASK_VNH 0x1
2127 +#define VF_SH_VNH 0
2128 +#define VF_MASK_OFFSET 0x3fff
2129 +#define VF_SH_OFFSET 2
2130 +#define VF_MASK_CC 0xf
2131 +#define VF_SH_CC 0
2132 +#define VF_MASK_CONST 0x1f
2133 +#define VF_SH_CONST 16
2134 +#define VF_MASK_SCALE 0x1f
2135 +#define VF_SH_SCALE 16
2136 +#define VF_MASK_BCOND 0x7
2137 +#define VF_SH_BCOND 18
2138 +#define VF_MASK_MCOND 0x7
2139 +#define VF_SH_MCOND 16
2140 +#define VF_MASK_VCD 0xff
2141 +#define VF_SH_VCD 0
2142 +#define VF_MASK_VCS 0xff
2143 +#define VF_SH_VCS 8
2144 +#define VF_MASK_ROT 0x1f
2145 +#define VF_SH_ROT 16
2146 +#define VF_MASK_WRAP 0xff
2147 +#define VF_SH_WRAP 16
2148 +#define VF_MASK_TSIGN 0x1
2149 +#define VF_SH_TSIGN 5
2150 +#define VF_MASK_BMCOND 0x1f
2151 +#define VF_SH_BMCOND 0
2152 +#define VF_MASK_HFLOAT 0xffff
2153 +#define VF_SH_HFLOAT 0
2154 +#define VF_MASK_PFX 0xffffff
2155 +#define VF_SH_PFX 0
2156 +#define VF_MASK_RWB 0x1
2157 +#define VF_SH_RWB 1
2158 +
2159 +#define VF_MASK_PFX_SWZ 0x3
2160 +#define VF_SH_PFX_SWZ 0
2161 +#define VF_MASK_PFX_ABS 0x1
2162 +#define VF_SH_PFX_ABS 8
2163 +#define VF_MASK_PFX_CST 0x1
2164 +#define VF_SH_PFX_CST 12
2165 +#define VF_MASK_PFX_NEG 0x1
2166 +#define VF_SH_PFX_NEG 16
2167 +#define VF_MASK_PFX_SAT 0x3
2168 +#define VF_SH_PFX_SAT 0
2169 +#define VF_MASK_PFX_MSK 0x1
2170 +#define VF_SH_PFX_MSK 8
2171 +
2172 +#define VF_MASK_ROT_COS 0x3
2173 +#define VF_SH_ROT_COS 0
2174 +#define VF_MASK_ROT_SIN 0x3
2175 +#define VF_SH_ROT_SIN 2
2176 +#define VF_MASK_ROT_NEG 0x1
2177 +#define VF_SH_ROT_NEG 4
2178 +
2179 +#define VF_MASK_MR_MTX 0x7
2180 +#define VF_SH_MR_MTX 2
2181 +#define VF_MASK_MR_IDX 0x3
2182 +#define VF_SH_MR_IDX 0
2183 +#define VF_MASK_MR_FSL 0x3
2184 +#define VF_SH_MR_FSL 5
2185 +#define VF_MASK_MR_RXC 0x1
2186 +#define VF_SH_MR_RXC 5
2187 +#define VF_MASK_MR_VFSL 0x1
2188 +#define VF_SH_MR_VFSL 6
2189 +
2190 +#define VF_MAX_MR_MTX 7
2191 +#define VF_MAX_MR_IDX 3
2192 +#define VF_MAX_MR_FSL 3
2193 +#define VF_MAX_MR_VIDX 1
2194 +#define VF_MAX_MR_VFSL 1
2195 +
2196 +#define VF_MIN_MR 0
2197 +#define VF_MAX_MR 127
2198 +#define VF_MIN_CR 128
2199 +#define VF_MAX_CR 255
2200 +#define VF_MIN_VCR 128
2201 +#define VF_MAX_VCR 143
2202 +#define VF_MIN_CC 0
2203 +#define VF_MAX_CC 15
2204 +#define VF_MIN_CONST 1
2205 +#define VF_MAX_CONST 19
2206 +#define VF_MIN_SCALE 0
2207 +#define VF_MAX_SCALE 31
2208 +#define VF_MIN_BCOND 0
2209 +#define VF_MAX_BCOND 5
2210 +#define VF_MIN_MCOND 0
2211 +#define VF_MAX_MCOND 6
2212 +#define VF_MIN_WRAP 0
2213 +#define VF_MAX_WRAP 255
2214 +#define VF_MIN_ROT 0
2215 +#define VF_MAX_ROT 31
2216 +#define VF_MIN_TSIGN 0
2217 +#define VF_MAX_TSIGN 1
2218 +#define VF_MIN_BMCOND 0
2219 +#define VF_MAX_BMCOND 31
2220 +#define VF_MIN_HFLOAT 0
2221 +#define VF_MAX_HFLOAT 0xffff
2222 +
2223 +#define VF_MASK_F32_SIGN 0x1
2224 +#define VF_SH_F32_SIGN 31
2225 +#define VF_MASK_F32_EXP 0xff
2226 +#define VF_SH_F32_EXP 23
2227 +#define VF_MASK_F32_FRA 0x7fffff
2228 +#define VF_SH_F32_FRA 0
2229 +#define VF_MASK_F16_SIGN 0x1
2230 +#define VF_SH_F16_SIGN 15
2231 +#define VF_MASK_F16_EXP 0x1f
2232 +#define VF_SH_F16_EXP 10
2233 +#define VF_MASK_F16_FRA 0x3ff
2234 +#define VF_SH_F16_FRA 0
2235 +
2236 +#define VF_MIN_F32_EXP 0
2237 +#define VF_MAX_F32_EXP 255
2238 +#define VF_BIAS_F32_EXP 127
2239 +#define VF_MIN_F16_EXP 0
2240 +#define VF_MAX_F16_EXP 31
2241 +#define VF_BIAS_F16_EXP 15
2242 +
2243 +#define OP_SH_VFPU_DELTA 0
2244 +#define OP_MASK_VFPU_DELTA 0xfffc
2245 +#define OP_SH_VFPU_IMM3 16
2246 +#define OP_MASK_VFPU_IMM3 0x7
2247 +#define OP_SH_VFPU_IMM5 16
2248 +#define OP_MASK_VFPU_IMM5 0x1f
2249 +#define OP_SH_VFPU_IMM8 16
2250 +#define OP_MASK_VFPU_IMM8 0xff
2251 +#define OP_SH_VFPU_CC 18 /* Condition code. */
2252 +#define OP_MASK_VFPU_CC 0x7
2253 +#define OP_SH_VFPU_CONST 16
2254 +#define OP_MASK_VFPU_CONST 0x1f
2255 +#define OP_SH_VFPU_COND 0 /* Conditional compare. */
2256 +#define OP_MASK_VFPU_COND 0xf
2257 +#define OP_SH_VFPU_VMTVC 0
2258 +#define OP_MASK_VFPU_VMTVC 0xff
2259 +#define OP_SH_VFPU_VMFVC 8
2260 +#define OP_MASK_VFPU_VMFVC 0xff
2261 +#define OP_SH_VFPU_RWB 1
2262 +#define OP_MASK_VFPU_RWB 0x1
2263 +#define OP_SH_VFPU_ROT 16 /* Rotators used in vrot. */
2264 +#define OP_MASK_VFPU_ROT 0x1f
2265 +#define OP_SH_VFPU_FLOAT16 0
2266 +#define OP_MASK_VFPU_FLOAT16 0xffff
2267 +
2268 +/* VFPU registers. */
2269 +#define OP_SH_VFPU_VD 0
2270 +#define OP_MASK_VFPU_VD 0x7f
2271 +#define OP_SH_VFPU_VS 8
2272 +#define OP_MASK_VFPU_VS 0x7f
2273 +#define OP_SH_VFPU_VT 16
2274 +#define OP_MASK_VFPU_VT 0x7f
2275 +#define OP_SH_VFPU_VT_LO 16 /* Bits 0-4 of vt. */
2276 +#define OP_MASK_VFPU_VT_LO 0x1f
2277 +#define OP_SH_VFPU_VT_HI 5 /* Right-shifted. */
2278 +#define OP_MASK_VFPU_VT_HI1 0x1 /* Bit 5 of vt. */
2279 +#define OP_MASK_VFPU_VT_HI2 0x3 /* Bits 5-6 of vt. */
2280 +/* Special handling of vs in vmmul instructions. */
2281 +#define VFPU_OP_VT_VS_VD 0xff800000
2282 +#define VFPU_OPCODE_VMMUL 0xf0000000
2283 +
2284 +/* VFPU condition codes. FL and TR accept no arguments, while any conditions
2285 + above and including EZ only accept one argument. The rest require two
2286 + arguments. */
2287 +enum
2288 +{
2289 + VFPU_COND_FL, VFPU_COND_EQ, VFPU_COND_LT, VFPU_COND_LE,
2290 + VFPU_COND_TR, VFPU_COND_NE, VFPU_COND_GE, VFPU_COND_GT,
2291 + VFPU_COND_EZ, VFPU_COND_EN, VFPU_COND_EI, VFPU_COND_ES,
2292 + VFPU_COND_NZ, VFPU_COND_NN, VFPU_COND_NI, VFPU_COND_NS,
2293 + VFPU_NUM_CONDS
2294 +};
2295 +
2296 +/* VFPU prefix instruction operands. The *_SH_* values really specify where
2297 + the bitfield begins, as VFPU prefix instructions have four operands
2298 + encoded within the immediate field. */
2299 +#define VFPU_SH_PFX_NEG 16
2300 +#define VFPU_MASK_PFX_NEG 0x1 /* Negation. */
2301 +#define VFPU_SH_PFX_CST 12
2302 +#define VFPU_MASK_PFX_CST 0x1 /* Constant. */
2303 +#define VFPU_SH_PFX_ABS_CSTHI 8
2304 +#define VFPU_MASK_PFX_ABS_CSTHI 0x1 /* Abs/Constant (bit 2). */
2305 +#define VFPU_SH_PFX_SWZ_CSTLO 0
2306 +#define VFPU_MASK_PFX_SWZ_CSTLO 0x3 /* Swizzle/Constant (bits 0-1). */
2307 +#define VFPU_SH_PFX_MASK 8
2308 +#define VFPU_MASK_PFX_MASK 0x1 /* Mask. */
2309 +#define VFPU_SH_PFX_SAT 0
2310 +#define VFPU_MASK_PFX_SAT 0x3 /* Saturation. */
2311 +
2312 +/* Special handling of the vrot instructions. */
2313 +#define VFPU_MASK_OP_SIZE 0x8080 /* Masks the operand size (pair, triple, quad). */
2314 +#define VFPU_OP_SIZE_PAIR 0x80
2315 +#define VFPU_OP_SIZE_TRIPLE 0x8000
2316 +#define VFPU_OP_SIZE_QUAD 0x8080
2317 +/* Note that these are within the rotators field, and not the full opcode. */
2318 +#define VFPU_SH_ROT_HI 2
2319 +#define VFPU_MASK_ROT_HI 0x3
2320 +#define VFPU_SH_ROT_LO 0
2321 +#define VFPU_MASK_ROT_LO 0x3
2322 +#define VFPU_SH_ROT_NEG 4 /* Negation. */
2323 +#define VFPU_MASK_ROT_NEG 0x1
2324 +
2325 +/* VFPU 16-bit floating-point format. */
2326 +#define VFPU_FLOAT16_EXP_MAX 0x1f
2327 +#define VFPU_SH_FLOAT16_SIGN 15
2328 +#define VFPU_MASK_FLOAT16_SIGN 0x1
2329 +#define VFPU_SH_FLOAT16_EXP 10
2330 +#define VFPU_MASK_FLOAT16_EXP 0x1f
2331 +#define VFPU_SH_FLOAT16_FRAC 0
2332 +#define VFPU_MASK_FLOAT16_FRAC 0x3ff
2333 +
2334 /* UDI */
2335 #define OP_SH_UDI1 6
2336 #define OP_MASK_UDI1 0x1f
2337 @@ -421,6 +643,29 @@
2338 Requires that "+A" or "+E" occur first to set position.
2339 Enforces: 32 < (pos+size) <= 64.
2340
2341 + Sony Allegrex VFPU instructions:
2342 + "?o"
2343 + "?0" - "?3"
2344 + "?4" - "?7"
2345 + "?a"
2346 + "?b"
2347 + "?c"
2348 + "?e"
2349 + "?f"
2350 + "?i"
2351 + "?q"
2352 + "?r"
2353 + "?u"
2354 + "?w"
2355 + "?d"
2356 + "?m"
2357 + "?n"
2358 + "?s"
2359 + "?t"
2360 + "?v"
2361 + "?x"
2362 + "?z"
2363 +
2364 Floating point instructions:
2365 "D" 5 bit destination register (OP_*_FD)
2366 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
2367 @@ -757,6 +1002,8 @@
2368 #define INSN_5400 0x01000000
2369 /* NEC VR5500 instruction. */
2370 #define INSN_5500 0x02000000
2371 +/* Sony Allegrex instruction. */
2372 +#define INSN_ALLEGREX 0x10000000
2373
2374 /* MDMX ASE */
2375 #define INSN_MDMX 0x04000000
2376 @@ -826,12 +1073,13 @@
2377 #define CPU_MIPS64 64
2378 #define CPU_MIPS64R2 65
2379 #define CPU_SB1 12310201 /* octal 'SB', 01. */
2380 +#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */
2381 #define CPU_LOONGSON_2E 3001
2382 #define CPU_LOONGSON_2F 3002
2383 #define CPU_LOONGSON_3A 3003
2384 #define CPU_OCTEON 6501
2385 -#define CPU_OCTEONP 6601
2386 -#define CPU_OCTEON2 6502
2387 +#define CPU_OCTEONP 6601
2388 +#define CPU_OCTEON2 6502
2389 #define CPU_XLR 887682 /* decimal 'XLR' */
2390
2391 /* Return true if the given CPU is included in INSN_* mask MASK. */
2392 @@ -876,6 +1124,9 @@
2393 case CPU_VR5500:
2394 return (mask & INSN_5500) != 0;
2395
2396 + case CPU_ALLEGREX:
2397 + return (mask & INSN_ALLEGREX) != 0;
2398 +
2399 case CPU_LOONGSON_2E:
2400 return (mask & INSN_LOONGSON_2E) != 0;
2401
2402 @@ -1074,11 +1325,27 @@
2403 M_LI_DD,
2404 M_LI_S,
2405 M_LI_SS,
2406 + M_LVHI_S_SS,
2407 + M_LVHI_P_SS,
2408 + M_LVI_S_SS,
2409 + M_LVI_P_SS,
2410 + M_LVI_T_SS,
2411 + M_LVI_Q_SS,
2412 M_LL_AB,
2413 M_LL_OB,
2414 M_LLD_AB,
2415 M_LLD_OB,
2416 M_LS_A,
2417 + M_LVHI_P,
2418 + M_LVHI_S,
2419 + M_LVI_P,
2420 + M_LVI_Q,
2421 + M_LVI_S,
2422 + M_LVI_T,
2423 + M_LVL_Q_AB,
2424 + M_LVR_Q_AB,
2425 + M_LV_Q_AB,
2426 + M_LV_Q_AB_2,
2427 M_LW_A,
2428 M_LW_AB,
2429 M_LWC0_A,
2430 @@ -1090,6 +1357,7 @@
2431 M_LWC2_OB,
2432 M_LWC3_A,
2433 M_LWC3_AB,
2434 + M_LV_S_AB,
2435 M_LWL_A,
2436 M_LWL_AB,
2437 M_LWL_OB,
2438 @@ -1203,6 +1471,10 @@
2439 M_SUB_I,
2440 M_SUBU_I,
2441 M_SUBU_I_2,
2442 + M_SVL_Q_AB,
2443 + M_SV_Q_AB,
2444 + M_SVR_Q_AB,
2445 + M_SV_S_AB,
2446 M_TEQ_I,
2447 M_TGE_I,
2448 M_TGEU_I,
2449 @@ -1217,14 +1489,24 @@
2450 M_ULH_A,
2451 M_ULHU,
2452 M_ULHU_A,
2453 + M_ULV_Q,
2454 + M_ULV_Q_AB,
2455 + M_ULV_S,
2456 M_ULW,
2457 M_ULW_A,
2458 M_USH,
2459 M_USH_A,
2460 + M_USV_Q,
2461 + M_USV_Q_AB,
2462 + M_USV_S,
2463 M_USW,
2464 M_USW_A,
2465 M_USD,
2466 M_USD_A,
2467 + M_VCMOV_P,
2468 + M_VCMOV_Q,
2469 + M_VCMOV_S,
2470 + M_VCMOV_T,
2471 M_XOR_I,
2472 M_COP0,
2473 M_COP1,
2474 diff -NrU3 binutils-2.23.2/include/opcode/vfpu.h binutils-2.23.2-patched/include/opcode/vfpu.h
2475 --- binutils-2.23.2/include/opcode/vfpu.h 1970-01-01 01:00:00.000000000 +0100
2476 +++ binutils-2.23.2-patched/include/opcode/vfpu.h 2020-04-23 17:57:30.329522786 +0200
2477 @@ -0,0 +1,261 @@
2478 +#ifndef _VFPU_H_
2479 +#define _VFPU_H_
2480 +
2481 +////////////////////////////////////
2482 +// data type
2483 +#define VFPU_MASK_DTYPE 0x8080
2484 +#define VFPU_QUAD 0x8080
2485 +#define VFPU_TRIPLE 0x8000
2486 +#define VFPU_PAIR 0x0080
2487 +#define VFPU_SINGLE 0x0000
2488 +
2489 +////////////////////////////////////
2490 +// register index
2491 +#define VFPU_MASK_VT 0x7f0000
2492 +#define VFPU_MASK_VS 0x007f00
2493 +#define VFPU_MASK_VD 0x00007f
2494 +
2495 +////////////////////////////////////
2496 +// condition and comapre inst
2497 +#define VFPU_PADD_BIN_CMP 0x70
2498 +
2499 +////////////////////////////////////
2500 +// load/store left/right
2501 +#define VFPU_MASK_LDST_LR 0x2
2502 +#define VFPU_LDST_L 0x0
2503 +#define VFPU_LDST_R 0x2
2504 +
2505 +////////////////////////////////////
2506 +// load/store memory/buffer
2507 +#define VFPU_MASK_LDST_MB 0x2
2508 +#define VFPU_LDST_M 0x0
2509 +#define VFPU_LDST_B 0x2
2510 +
2511 +////////////////////////////////////
2512 +// coprocessor move
2513 +#define VFPU_MASK_COP_MV 0xff80
2514 +#define VFPU_MASK_COP_MVC 0xff00
2515 +
2516 +////////////////////////////////////
2517 +// sync code
2518 +#define VFPU_MASK_SYNC_CODE 0xffff
2519 +#define VFPU_SYNC_CODE_DEFAULT 0x0320
2520 +#define VFPU_SYNC_CODE_NOP 0x0000
2521 +#define VFPU_SYNC_CODE_FLUSH 0x040d
2522 +
2523 +////////////////////////////////////
2524 +#define VFPU_INST_BR_F 0x49000000
2525 +#define VFPU_MASK_BR_F 0xffe30000
2526 +#define VFPU_INST_BR_FL 0x49020000
2527 +#define VFPU_MASK_BR_FL 0xffe30000
2528 +#define VFPU_INST_BR_T 0x49010000
2529 +#define VFPU_MASK_BR_T 0xffe30000
2530 +#define VFPU_INST_BR_TL 0x49030000
2531 +#define VFPU_MASK_BR_TL 0xffe30000
2532 +
2533 +#define VFPU_INST_COP_LD_S 0xc8000000
2534 +#define VFPU_MASK_COP_LD_S 0xfc000000
2535 +#define VFPU_INST_COP_ST_S 0xe8000000
2536 +#define VFPU_MASK_COP_ST_S 0xfc000000
2537 +#define VFPU_INST_COP_LD_Q 0xd8000000
2538 +#define VFPU_MASK_COP_LD_Q 0xfc000000
2539 +#define VFPU_INST_COP_ST_Q 0xf8000000
2540 +#define VFPU_MASK_COP_ST_Q 0xfc000000
2541 +#define VFPU_INST_COP_LD_U 0xd4000000
2542 +#define VFPU_MASK_COP_LD_U 0xfc000000
2543 +#define VFPU_INST_COP_ST_U 0xf4000000
2544 +#define VFPU_MASK_COP_ST_U 0xfc000000
2545 +#define VFPU_INST_COP_MF 0x48600000
2546 +#define VFPU_MASK_COP_MF 0xffe00000
2547 +#define VFPU_INST_COP_MT 0x48e00000
2548 +#define VFPU_MASK_COP_MT 0xffe00000
2549 +
2550 +#define VFPU_INST_BIN_ADD 0x60000000
2551 +#define VFPU_MASK_BIN_ADD 0xff800000
2552 +#define VFPU_INST_BIN_SUB 0x60800000
2553 +#define VFPU_MASK_BIN_SUB 0xff800000
2554 +#define VFPU_INST_BIN_SBN 0x61000000
2555 +#define VFPU_MASK_BIN_SBN 0xff800000
2556 +#define VFPU_INST_BIN_DIV 0x63800000
2557 +#define VFPU_MASK_BIN_DIV 0xff800000
2558 +#define VFPU_INST_BIN_MUL 0x64000000
2559 +#define VFPU_MASK_BIN_MUL 0xff800000
2560 +#define VFPU_INST_BIN_DOT 0x64800000
2561 +#define VFPU_MASK_BIN_DOT 0xff800000
2562 +#define VFPU_INST_BIN_SCL 0x65000000
2563 +#define VFPU_MASK_BIN_SCL 0xff800000
2564 +#define VFPU_INST_BIN_HDP 0x66000000
2565 +#define VFPU_MASK_BIN_HDP 0xff800000
2566 +#define VFPU_INST_BIN_CRS 0x66800000
2567 +#define VFPU_MASK_BIN_CRS 0xff800000
2568 +#define VFPU_INST_BIN_DET 0x67000000
2569 +#define VFPU_MASK_BIN_DET 0xff800000
2570 +#define VFPU_INST_BIN_CMP 0x6c000000
2571 +#define VFPU_MASK_BIN_CMP 0xff800000
2572 +#define VFPU_INST_BIN_MIN 0x6d000000
2573 +#define VFPU_MASK_BIN_MIN 0xff800000
2574 +#define VFPU_INST_BIN_MAX 0x6d800000
2575 +#define VFPU_MASK_BIN_MAX 0xff800000
2576 +#define VFPU_INST_BIN_SCMP 0x6e800000
2577 +#define VFPU_MASK_BIN_SCMP 0xff800000
2578 +#define VFPU_INST_BIN_SGE 0x6f000000
2579 +#define VFPU_MASK_BIN_SGE 0xff800000
2580 +#define VFPU_INST_BIN_SLT 0x6f800000
2581 +#define VFPU_MASK_BIN_SLT 0xff800000
2582 +
2583 +#define VFPU_INST_UNR_MOV 0xd0000000
2584 +#define VFPU_MASK_UNR_MOV 0xffff0000
2585 +#define VFPU_INST_UNR_ABS 0xd0010000
2586 +#define VFPU_MASK_UNR_ABS 0xffff0000
2587 +#define VFPU_INST_UNR_NEG 0xd0020000
2588 +#define VFPU_MASK_UNR_NEG 0xffff0000
2589 +#define VFPU_INST_UNR_IDT 0xd0030000
2590 +#define VFPU_MASK_UNR_IDT 0xffff0000
2591 +#define VFPU_INST_UNR_SAT0 0xd0040000
2592 +#define VFPU_MASK_UNR_SAT0 0xffff0000
2593 +#define VFPU_INST_UNR_SAT1 0xd0050000
2594 +#define VFPU_MASK_UNR_SAT1 0xffff0000
2595 +#define VFPU_INST_UNR_ZERO 0xd0060000
2596 +#define VFPU_MASK_UNR_ZERO 0xffff0000
2597 +#define VFPU_INST_UNR_ONE 0xd0070000
2598 +#define VFPU_MASK_UNR_ONE 0xffff0000
2599 +#define VFPU_INST_UNR_RCP 0xd0100000
2600 +#define VFPU_MASK_UNR_RCP 0xffff0000
2601 +#define VFPU_INST_UNR_RSQ 0xd0110000
2602 +#define VFPU_MASK_UNR_RSQ 0xffff0000
2603 +#define VFPU_INST_UNR_SIN 0xd0120000
2604 +#define VFPU_MASK_UNR_SIN 0xffff0000
2605 +#define VFPU_INST_UNR_COS 0xd0130000
2606 +#define VFPU_MASK_UNR_COS 0xffff0000
2607 +#define VFPU_INST_UNR_EXP2 0xd0140000
2608 +#define VFPU_MASK_UNR_EXP2 0xffff0000
2609 +#define VFPU_INST_UNR_LOG2 0xd0150000
2610 +#define VFPU_MASK_UNR_LOG2 0xffff0000
2611 +#define VFPU_INST_UNR_SQR 0xd0160000
2612 +#define VFPU_MASK_UNR_SQR 0xffff0000
2613 +#define VFPU_INST_UNR_ASIN 0xd0170000
2614 +#define VFPU_MASK_UNR_ASIN 0xffff0000
2615 +#define VFPU_INST_UNR_NRCP 0xd0180000
2616 +#define VFPU_MASK_UNR_NRCP 0xffff0000
2617 +#define VFPU_INST_UNR_NSIN 0xd01a0000
2618 +#define VFPU_MASK_UNR_NSIN 0xffff0000
2619 +#define VFPU_INST_UNR_REXP2 0xd01c0000
2620 +#define VFPU_MASK_UNR_REXP2 0xffff0000
2621 +#define VFPU_INST_UNR_RNDS 0xd0200000
2622 +#define VFPU_MASK_UNR_RNDS 0xffff0000
2623 +#define VFPU_INST_UNR_RNDI 0xd0210000
2624 +#define VFPU_MASK_UNR_RNDI 0xffff0000
2625 +#define VFPU_INST_UNR_RNDF1 0xd0220000
2626 +#define VFPU_MASK_UNR_RNDF1 0xffff0000
2627 +#define VFPU_INST_UNR_RNDF2 0xd0230000
2628 +#define VFPU_MASK_UNR_RNDF2 0xffff0000
2629 +#define VFPU_INST_UNR_F2H 0xd0320000
2630 +#define VFPU_MASK_UNR_F2H 0xffff0000
2631 +#define VFPU_INST_UNR_H2F 0xd0330000
2632 +#define VFPU_MASK_UNR_H2F 0xffff0000
2633 +#define VFPU_INST_UNR_SBZ 0xd0360000
2634 +#define VFPU_MASK_UNR_SBZ 0xffff0000
2635 +#define VFPU_INST_UNR_LGB 0xd0370000
2636 +#define VFPU_MASK_UNR_LGB 0xffff0000
2637 +#define VFPU_INST_UNR_US2I 0xd03a0000
2638 +#define VFPU_MASK_UNR_US2I 0xffff0000
2639 +#define VFPU_INST_UNR_S2I 0xd03b0000
2640 +#define VFPU_MASK_UNR_S2I 0xffff0000
2641 +#define VFPU_INST_UNR_I2UC 0xd03c0000
2642 +#define VFPU_MASK_UNR_I2UC 0xffff0000
2643 +#define VFPU_INST_UNR_I2C 0xd03d0000
2644 +#define VFPU_MASK_UNR_I2C 0xffff0000
2645 +#define VFPU_INST_UNR_I2US 0xd03e0000
2646 +#define VFPU_MASK_UNR_I2US 0xffff0000
2647 +#define VFPU_INST_UNR_I2S 0xd03f0000
2648 +#define VFPU_MASK_UNR_I2S 0xffff0000
2649 +#define VFPU_INST_UNR_SRT1 0xd0400000
2650 +#define VFPU_MASK_UNR_SRT1 0xffff0000
2651 +#define VFPU_INST_UNR_SRT2 0xd0410000
2652 +#define VFPU_MASK_UNR_SRT2 0xffff0000
2653 +#define VFPU_INST_UNR_BFY1 0xd0420000
2654 +#define VFPU_MASK_UNR_BFY1 0xffff0000
2655 +#define VFPU_INST_UNR_BFY2 0xd0430000
2656 +#define VFPU_MASK_UNR_BFY2 0xffff0000
2657 +#define VFPU_INST_UNR_OCP 0xd0440000
2658 +#define VFPU_MASK_UNR_OCP 0xffff0000
2659 +#define VFPU_INST_UNR_SOCP 0xd0450000
2660 +#define VFPU_MASK_UNR_SOCP 0xffff0000
2661 +#define VFPU_INST_UNR_FAD 0xd0460000
2662 +#define VFPU_MASK_UNR_FAD 0xffff0000
2663 +#define VFPU_INST_UNR_AVG 0xd0470000
2664 +#define VFPU_MASK_UNR_AVG 0xffff0000
2665 +#define VFPU_INST_UNR_SRT3 0xd0480000
2666 +#define VFPU_MASK_UNR_SRT3 0xffff0000
2667 +#define VFPU_INST_UNR_SRT4 0xd0490000
2668 +#define VFPU_MASK_UNR_SRT4 0xffff0000
2669 +#define VFPU_INST_UNR_SGN 0xd04a0000
2670 +#define VFPU_MASK_UNR_SGN 0xffff0000
2671 +#define VFPU_INST_UNR_CF 0xd0500000
2672 +#define VFPU_MASK_UNR_CF 0xffff0080
2673 +#define VFPU_INST_UNR_CT 0xd0510000
2674 +#define VFPU_MASK_UNR_CT 0xffff8000
2675 +#define VFPU_INST_UNR_T4444 0xd0590000
2676 +#define VFPU_MASK_UNR_T4444 0xffff0000
2677 +#define VFPU_INST_UNR_T5551 0xd05a0000
2678 +#define VFPU_MASK_UNR_T5551 0xffff0000
2679 +#define VFPU_INST_UNR_T5650 0xd05b0000
2680 +#define VFPU_MASK_UNR_T5650 0xffff0000
2681 +#define VFPU_INST_UNR_CST 0xd0600000
2682 +#define VFPU_MASK_UNR_CST 0xffe00000
2683 +
2684 +#define VFPU_INST_UNRI_F2I_N 0xd2000000
2685 +#define VFPU_MASK_UNRI_F2I_N 0xffe00000
2686 +#define VFPU_INST_UNRI_F2I_Z 0xd2200000
2687 +#define VFPU_MASK_UNRI_F2I_Z 0xffe00000
2688 +#define VFPU_INST_UNRI_F2I_U 0xd2400000
2689 +#define VFPU_MASK_UNRI_F2I_U 0xffe00000
2690 +#define VFPU_INST_UNRI_F2I_D 0xd2600000
2691 +#define VFPU_MASK_UNRI_F2I_D 0xffe00000
2692 +#define VFPU_INST_UNRI_I2F 0xd2800000
2693 +#define VFPU_MASK_UNRI_I2F 0xffe00000
2694 +#define VFPU_INST_UNRI_CMOV_T 0xd2a00000
2695 +#define VFPU_MASK_UNRI_CMOV_T 0xfff80000
2696 +#define VFPU_INST_UNRI_CMOV_F 0xd2a80000
2697 +#define VFPU_MASK_UNRI_CMOV_F 0xfff80000
2698 +#define VFPU_INST_UNRI_WBN 0xd3000000
2699 +#define VFPU_MASK_UNRI_WBN 0xff000000
2700 +
2701 +#define VFPU_INST_PFX_RA 0xdc000000
2702 +#define VFPU_MASK_PFX_RA 0xff000000
2703 +#define VFPU_INST_PFX_RB 0xdd000000
2704 +#define VFPU_MASK_PFX_RB 0xff000000
2705 +#define VFPU_INST_PFX_W 0xde000000
2706 +#define VFPU_MASK_PFX_W 0xff000000
2707 +#define VFPU_INST_IIM 0xdf000000
2708 +#define VFPU_MASK_IIM 0xff800000
2709 +#define VFPU_INST_FIM 0xdf800000
2710 +#define VFPU_MASK_FIM 0xff800000
2711 +
2712 +#define VFPU_INST_RPT_MMUL 0xf0000000
2713 +#define VFPU_MASK_RPT_MMUL 0xff800000
2714 +#define VFPU_INST_RPT_TFM2 0xf0800000
2715 +#define VFPU_MASK_RPT_TFM2 0xff800000
2716 +#define VFPU_INST_RPT_TFM3 0xf1000000
2717 +#define VFPU_MASK_RPT_TFM3 0xff800000
2718 +#define VFPU_INST_RPT_TFM4 0xf1800000
2719 +#define VFPU_MASK_RPT_TFM4 0xff800000
2720 +#define VFPU_INST_RPT_MSCL 0xf2000000
2721 +#define VFPU_MASK_RPT_MSCL 0xff800000
2722 +#define VFPU_INST_RPT_QMUL 0xf2800000
2723 +#define VFPU_MASK_RPT_QMUL 0xff800000
2724 +#define VFPU_INST_RPT_MMOV 0xf3800000
2725 +#define VFPU_MASK_RPT_MMOV 0xffff0000
2726 +#define VFPU_INST_RPT_MIDT 0xf3830000
2727 +#define VFPU_MASK_RPT_MIDT 0xffff0000
2728 +#define VFPU_INST_RPT_MZERO 0xf3860000
2729 +#define VFPU_MASK_RPT_MZERO 0xffff0000
2730 +#define VFPU_INST_RPT_MONE 0xf3870000
2731 +#define VFPU_MASK_RPT_MONE 0xffff0000
2732 +#define VFPU_INST_RPT_ROT 0xf3a00000
2733 +#define VFPU_MASK_RPT_ROT 0xffe00000
2734 +
2735 +#define VFPU_INST_SYNC 0xffff0000
2736 +#define VFPU_MASK_SYNC 0xffff0000
2737 +
2738 +#endif /* _VFPU_H_ */
2739 diff -NrU3 binutils-2.23.2/ld/configure.tgt binutils-2.23.2-patched/ld/configure.tgt
2740 --- binutils-2.23.2/ld/configure.tgt 2012-09-04 14:53:47.000000000 +0200
2741 +++ binutils-2.23.2-patched/ld/configure.tgt 2020-04-23 17:57:30.329522786 +0200
2742 @@ -422,6 +422,8 @@
2743 mips*vr4100-*-elf*) targ_emul=elf32b4300 ;;
2744 mips*vr5000el-*-elf*) targ_emul=elf32l4300 ;;
2745 mips*vr5000-*-elf*) targ_emul=elf32b4300 ;;
2746 +mips*allegrexel-psp-elf*) targ_emul=elf_mipsallegrexel_psp
2747 + targ_extra_emuls="elf32elmip" ;;
2748 mips*el-sde-elf*) targ_emul=elf32ltsmip
2749 targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" ;;
2750 mips*-sde-elf*) targ_emul=elf32btsmip
2751 diff -NrU3 binutils-2.23.2/ld/emulparams/elf_mipsallegrexel_psp.sh binutils-2.23.2-patched/ld/emulparams/elf_mipsallegrexel_psp.sh
2752 --- binutils-2.23.2/ld/emulparams/elf_mipsallegrexel_psp.sh 1970-01-01 01:00:00.000000000 +0100
2753 +++ binutils-2.23.2-patched/ld/emulparams/elf_mipsallegrexel_psp.sh 2020-04-23 17:57:30.329522786 +0200
2754 @@ -0,0 +1,22 @@
2755 +# Based off of the default elf32 MIPS target. However, we use a seperate
2756 +# script template because the PSP architecture defines sections that normally
2757 +# cannot be overriden here and would normally get absorbed (i.e.
2758 +# .rodata.sceModuleInfo would be absorbed into .rodata).
2759 +
2760 +EMBEDDED=yes
2761 +. ${srcdir}/emulparams/elf32lmip.sh
2762 +unset NONPAGED_TEXT_START_ADDR
2763 +unset SHLIB_TEXT_START_ADDR
2764 +unset COMMONPAGESIZE
2765 +
2766 +SCRIPT_NAME=elf_psp
2767 +TEXT_START_ADDR=0x08900000
2768 +MAXPAGESIZE=256
2769 +ARCH="mips:allegrex"
2770 +MACHINE=
2771 +TEMPLATE_NAME=elf32
2772 +GENERATE_SHLIB_SCRIPT=yes
2773 +DYNAMIC_LINK=FALSE
2774 +
2775 +# Discard the .comment and .pdr sections.
2776 +OTHER_SECTIONS="/DISCARD/ : { *(.comment) *(.pdr) }"
2777 diff -NrU3 binutils-2.23.2/ld/Makefile.am binutils-2.23.2-patched/ld/Makefile.am
2778 --- binutils-2.23.2/ld/Makefile.am 2013-03-25 09:06:23.000000000 +0100
2779 +++ binutils-2.23.2-patched/ld/Makefile.am 2020-04-23 17:57:30.329522786 +0200
2780 @@ -268,6 +268,7 @@
2781 eelf_i386_nacl.c \
2782 eelf_i386_sol2.c \
2783 eelf_i386_vxworks.c \
2784 + eelf_mipsallegrexel_psp.o \
2785 eelf_s390.c \
2786 egld960.c \
2787 egld960coff.c \
2788 @@ -1242,6 +1243,9 @@
2789 $(srcdir)/emulparams/vxworks.sh $(srcdir)/emultempl/vxworks.em \
2790 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
2791 ${GENSCRIPTS} elf_i386_vxworks "$(tdir_elf_i386_vxworks)"
2792 +eelf_mipsallegrexel_psp.c: $(srcdir)/emulparams/elf_mipsallegrexel_psp.sh \
2793 + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf_psp.sc ${GEN_DEPENDS}
2794 + ${GENSCRIPTS} elf_mipsallegrexel_psp "$(tdir_elf_mipsallegrexel_psp)"
2795 eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \
2796 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
2797 ${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)"
2798 diff -NrU3 binutils-2.23.2/ld/Makefile.in binutils-2.23.2-patched/ld/Makefile.in
2799 --- binutils-2.23.2/ld/Makefile.in 2013-03-25 09:06:23.000000000 +0100
2800 +++ binutils-2.23.2-patched/ld/Makefile.in 2020-04-23 17:57:30.329522786 +0200
2801 @@ -575,6 +575,7 @@
2802 eelf_i386_nacl.c \
2803 eelf_i386_sol2.c \
2804 eelf_i386_vxworks.c \
2805 + eelf_mipsallegrexel_psp.o \
2806 eelf_s390.c \
2807 egld960.c \
2808 egld960coff.c \
2809 @@ -2712,6 +2713,9 @@
2810 $(srcdir)/emulparams/vxworks.sh $(srcdir)/emultempl/vxworks.em \
2811 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
2812 ${GENSCRIPTS} elf_i386_vxworks "$(tdir_elf_i386_vxworks)"
2813 +eelf_mipsallegrexel_psp.c: $(srcdir)/emulparams/elf_mipsallegrexel_psp.sh \
2814 + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf_psp.sc ${GEN_DEPENDS}
2815 + ${GENSCRIPTS} elf_mipsallegrexel_psp "$(tdir_elf_mipsallegrexel_psp)"
2816 eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \
2817 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
2818 ${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)"
2819 diff -NrU3 binutils-2.23.2/ld/scripttempl/elf_psp.sc binutils-2.23.2-patched/ld/scripttempl/elf_psp.sc
2820 --- binutils-2.23.2/ld/scripttempl/elf_psp.sc 1970-01-01 01:00:00.000000000 +0100
2821 +++ binutils-2.23.2-patched/ld/scripttempl/elf_psp.sc 2020-04-23 17:57:30.329522786 +0200
2822 @@ -0,0 +1,496 @@
2823 +#
2824 +# Unusual variables checked by this code:
2825 +# NOP - four byte opcode for no-op (defaults to 0)
2826 +# NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
2827 +# empty.
2828 +# SMALL_DATA_CTOR - .ctors contains small data.
2829 +# SMALL_DATA_DTOR - .dtors contains small data.
2830 +# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
2831 +# INITIAL_READONLY_SECTIONS - at start of text segment
2832 +# OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
2833 +# (e.g., .PARISC.milli)
2834 +# OTHER_TEXT_SECTIONS - these get put in .text when relocating
2835 +# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
2836 +# (e.g., .PARISC.global)
2837 +# OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
2838 +# (e.g. PPC32 .fixup, .got[12])
2839 +# OTHER_BSS_SECTIONS - other than .bss .sbss ...
2840 +# OTHER_SECTIONS - at the end
2841 +# EXECUTABLE_SYMBOLS - symbols that must be defined for an
2842 +# executable (e.g., _DYNAMIC_LINK)
2843 +# TEXT_START_ADDR - the first byte of the text segment, after any
2844 +# headers.
2845 +# TEXT_BASE_ADDRESS - the first byte of the text segment.
2846 +# TEXT_START_SYMBOLS - symbols that appear at the start of the
2847 +# .text section.
2848 +# DATA_START_SYMBOLS - symbols that appear at the start of the
2849 +# .data section.
2850 +# OTHER_GOT_SYMBOLS - symbols defined just before .got.
2851 +# OTHER_GOT_SECTIONS - sections just after .got.
2852 +# OTHER_SDATA_SECTIONS - sections just after .sdata.
2853 +# OTHER_BSS_SYMBOLS - symbols that appear at the start of the
2854 +# .bss section besides __bss_start.
2855 +# DATA_PLT - .plt should be in data segment, not text segment.
2856 +# PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement.
2857 +# BSS_PLT - .plt should be in bss segment
2858 +# TEXT_DYNAMIC - .dynamic in text segment, not data segment.
2859 +# EMBEDDED - whether this is for an embedded system.
2860 +# SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
2861 +# start address of shared library.
2862 +# INPUT_FILES - INPUT command of files to always include
2863 +# WRITABLE_RODATA - if set, the .rodata section should be writable
2864 +# INIT_START, INIT_END - statements just before and just after
2865 +# combination of .init sections.
2866 +# FINI_START, FINI_END - statements just before and just after
2867 +# combination of .fini sections.
2868 +# STACK_ADDR - start of a .stack section.
2869 +# OTHER_END_SYMBOLS - symbols to place right at the end of the script.
2870 +# SEPARATE_GOTPLT - if set, .got.plt should be separate output section,
2871 +# so that .got can be in the RELRO area. It should be set to
2872 +# the number of bytes in the beginning of .got.plt which can be
2873 +# in the RELRO area as well.
2874 +#
2875 +# When adding sections, do note that the names of some sections are used
2876 +# when specifying the start address of the next.
2877 +#
2878 +
2879 +# Many sections come in three flavours. There is the 'real' section,
2880 +# like ".data". Then there are the per-procedure or per-variable
2881 +# sections, generated by -ffunction-sections and -fdata-sections in GCC,
2882 +# and useful for --gc-sections, which for a variable "foo" might be
2883 +# ".data.foo". Then there are the linkonce sections, for which the linker
2884 +# eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
2885 +# The exact correspondences are:
2886 +#
2887 +# Section Linkonce section
2888 +# .text .gnu.linkonce.t.foo
2889 +# .rodata .gnu.linkonce.r.foo
2890 +# .data .gnu.linkonce.d.foo
2891 +# .bss .gnu.linkonce.b.foo
2892 +# .sdata .gnu.linkonce.s.foo
2893 +# .sbss .gnu.linkonce.sb.foo
2894 +# .sdata2 .gnu.linkonce.s2.foo
2895 +# .sbss2 .gnu.linkonce.sb2.foo
2896 +# .debug_info .gnu.linkonce.wi.foo
2897 +# .tdata .gnu.linkonce.td.foo
2898 +# .tbss .gnu.linkonce.tb.foo
2899 +#
2900 +# Each of these can also have corresponding .rel.* and .rela.* sections.
2901 +
2902 +test -z "$ENTRY" && ENTRY=_start
2903 +test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
2904 +test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
2905 +if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
2906 +test -z "${ELFSIZE}" && ELFSIZE=32
2907 +test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
2908 +test "$LD_FLAG" = "N" && DATA_ADDR=.
2909 +test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
2910 +test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
2911 +test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT
2912 +DATA_SEGMENT_ALIGN="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))"
2913 +DATA_SEGMENT_RELRO_END=""
2914 +DATA_SEGMENT_RELRO_GOTPLT_END=""
2915 +DATA_SEGMENT_END=""
2916 +if test -n "${COMMONPAGESIZE}"; then
2917 + DATA_SEGMENT_ALIGN="ALIGN (${SEGMENT_SIZE}) - ((${MAXPAGESIZE} - .) & (${MAXPAGESIZE} - 1)); . = DATA_SEGMENT_ALIGN (${MAXPAGESIZE}, ${COMMONPAGESIZE})"
2918 + DATA_SEGMENT_END=". = DATA_SEGMENT_END (.);"
2919 + if test -n "${SEPARATE_GOTPLT}"; then
2920 + DATA_SEGMENT_RELRO_GOTPLT_END=". = DATA_SEGMENT_RELRO_END (${SEPARATE_GOTPLT}, .);"
2921 + else
2922 + DATA_SEGMENT_RELRO_END=". = DATA_SEGMENT_RELRO_END (0, .);"
2923 + fi
2924 +fi
2925 +INTERP=".interp ${RELOCATING-0} : { *(.interp) }"
2926 +PLT=".plt ${RELOCATING-0} : { *(.plt) }"
2927 +if test -z "$GOT"; then
2928 + if test -z "$SEPARATE_GOTPLT"; then
2929 + GOT=".got ${RELOCATING-0} : { *(.got.plt) *(.got) }"
2930 + else
2931 + GOT=".got ${RELOCATING-0} : { *(.got) }"
2932 + GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}}
2933 + .got.plt ${RELOCATING-0} : { *(.got.plt) }"
2934 + fi
2935 +fi
2936 +DYNAMIC=".dynamic ${RELOCATING-0} : { *(.dynamic) }"
2937 +RODATA=".rodata ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
2938 +DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }"
2939 +STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
2940 +if test -z "${NO_SMALL_DATA}"; then
2941 + SBSS=".sbss ${RELOCATING-0} :
2942 + {
2943 + ${RELOCATING+PROVIDE (__sbss_start = .);}
2944 + ${RELOCATING+PROVIDE (___sbss_start = .);}
2945 + ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)}
2946 + *(.dynsbss)
2947 + *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
2948 + *(.scommon)
2949 + ${RELOCATING+PROVIDE (__sbss_end = .);}
2950 + ${RELOCATING+PROVIDE (___sbss_end = .);}
2951 + }"
2952 + SBSS2=".sbss2 ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }"
2953 + SDATA="/* We want the small data sections together, so single-instruction offsets
2954 + can access them all, and initialized data all before uninitialized, so
2955 + we can shorten the on-disk segment size. */
2956 + .sdata ${RELOCATING-0} :
2957 + {
2958 + ${RELOCATING+${SDATA_START_SYMBOLS}}
2959 + ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)}
2960 + *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
2961 + }"
2962 + SDATA2=".sdata2 ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }"
2963 + REL_SDATA=".rel.sdata ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }
2964 + .rela.sdata ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
2965 + REL_SBSS=".rel.sbss ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }
2966 + .rela.sbss ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }"
2967 + REL_SDATA2=".rel.sdata2 ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }
2968 + .rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }"
2969 + REL_SBSS2=".rel.sbss2 ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }
2970 + .rela.sbss2 ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }"
2971 +else
2972 + NO_SMALL_DATA=" "
2973 +fi
2974 +test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" "
2975 +CTOR=".ctors ${CONSTRUCTING-0} :
2976 + {
2977 + ${CONSTRUCTING+${CTOR_START}}
2978 + /* gcc uses crtbegin.o to find the start of
2979 + the constructors, so we make sure it is
2980 + first. Because this is a wildcard, it
2981 + doesn't matter if the user does not
2982 + actually link against crtbegin.o; the
2983 + linker won't look for a file to match a
2984 + wildcard. The wildcard also means that it
2985 + doesn't matter which directory crtbegin.o
2986 + is in. */
2987 +
2988 + KEEP (*crtbegin*.o(.ctors))
2989 +
2990 + /* We don't want to include the .ctor section from
2991 + from the crtend.o file until after the sorted ctors.
2992 + The .ctor section from the crtend file contains the
2993 + end of ctors marker and it must be last */
2994 +
2995 + KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
2996 + KEEP (*(SORT(.ctors.*)))
2997 + KEEP (*(.ctors))
2998 + ${CONSTRUCTING+${CTOR_END}}
2999 + }"
3000 +DTOR=".dtors ${CONSTRUCTING-0} :
3001 + {
3002 + ${CONSTRUCTING+${DTOR_START}}
3003 + KEEP (*crtbegin*.o(.dtors))
3004 + KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
3005 + KEEP (*(SORT(.dtors.*)))
3006 + KEEP (*(.dtors))
3007 + ${CONSTRUCTING+${DTOR_END}}
3008 + }"
3009 +STACK=" .stack ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
3010 + {
3011 + ${RELOCATING+_stack = .;}
3012 + *(.stack)
3013 + }"
3014 +
3015 +# if this is for an embedded system, don't add SIZEOF_HEADERS.
3016 +if [ -z "$EMBEDDED" ]; then
3017 + test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
3018 +else
3019 + test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
3020 +fi
3021 +
3022 +cat <<EOF
3023 +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
3024 + "${LITTLE_OUTPUT_FORMAT}")
3025 +OUTPUT_ARCH(${OUTPUT_ARCH})
3026 +ENTRY(${ENTRY})
3027 +
3028 +${RELOCATING+${LIB_SEARCH_DIRS}}
3029 +${RELOCATING+/* Do we need any of these for elf?
3030 + __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}} */}
3031 +${RELOCATING+${EXECUTABLE_SYMBOLS}}
3032 +${RELOCATING+${INPUT_FILES}}
3033 +${RELOCATING- /* For some reason, the Solaris linker makes bad executables
3034 + if gld -r is used and the intermediate file has sections starting
3035 + at non-zero addresses. Could be a Solaris ld bug, could be a GNU ld
3036 + bug. But for now assigning the zero vmas works. */}
3037 +
3038 +SECTIONS
3039 +{
3040 + /* Read-only sections, merged into text segment: */
3041 + ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
3042 + ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
3043 + ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
3044 + ${CREATE_SHLIB-${INTERP}}
3045 + ${INITIAL_READONLY_SECTIONS}
3046 + ${TEXT_DYNAMIC+${DYNAMIC}}
3047 + .hash ${RELOCATING-0} : { *(.hash) }
3048 + .dynsym ${RELOCATING-0} : { *(.dynsym) }
3049 + .dynstr ${RELOCATING-0} : { *(.dynstr) }
3050 + .gnu.version ${RELOCATING-0} : { *(.gnu.version) }
3051 + .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }
3052 + .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }
3053 +
3054 +EOF
3055 +if [ "x$COMBRELOC" = x ]; then
3056 + COMBRELOCCAT=cat
3057 +else
3058 + COMBRELOCCAT="cat > $COMBRELOC"
3059 +fi
3060 +eval $COMBRELOCCAT <<EOF
3061 + .rel.init ${RELOCATING-0} : { *(.rel.init) }
3062 + .rela.init ${RELOCATING-0} : { *(.rela.init) }
3063 + .rel.text ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }
3064 + .rela.text ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }
3065 + .rel.fini ${RELOCATING-0} : { *(.rel.fini) }
3066 + .rela.fini ${RELOCATING-0} : { *(.rela.fini) }
3067 +
3068 + /* PSP-specific relocations. */
3069 + .rel.sceStub.text ${RELOCATING-0} : { *(.rel.sceStub.text) *(SORT(.rel.sceStub.text.*)) }
3070 + .rel.lib.ent.top ${RELOCATING-0} : { *(.rel.lib.ent.top) }
3071 + .rel.lib.ent ${RELOCATING-0} : { *(.rel.lib.ent) }
3072 + .rel.lib.ent.btm ${RELOCATING-0} : { *(.rel.lib.ent.btm) }
3073 + .rel.lib.stub.top ${RELOCATING-0} : { *(.rel.lib.stub.top) }
3074 + .rel.lib.stub ${RELOCATING-0} : { *(.rel.lib.stub) }
3075 + .rel.lib.stub.btm ${RELOCATING-0} : { *(.rel.lib.stub.btm) }
3076 + .rel.rodata.sceModuleInfo ${RELOCATING-0} : { *(.rel.rodata.sceModuleInfo) }
3077 + .rel.rodata.sceResident ${RELOCATING-0} : { *(.rel.rodata.sceResident) }
3078 + .rel.rodata.sceNid ${RELOCATING-0} : { *(.rel.rodata.sceNid) }
3079 + .rel.rodata.sceVstub ${RELOCATING-0} : { *(.rel.rodata.sceVstub) *(SORT(.rel.rodata.sceVstub.*)) }
3080 +
3081 + .rel.rodata ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }
3082 + .rela.rodata ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }
3083 + ${OTHER_READONLY_RELOC_SECTIONS}
3084 + .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }
3085 + .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }
3086 + .rel.data ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }
3087 + .rela.data ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }
3088 + .rel.tdata ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }
3089 + .rela.tdata ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }
3090 + .rel.tbss ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }
3091 + .rela.tbss ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }
3092 + .rel.ctors ${RELOCATING-0} : { *(.rel.ctors) }
3093 + .rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }
3094 + .rel.dtors ${RELOCATING-0} : { *(.rel.dtors) }
3095 + .rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }
3096 + .rel.got ${RELOCATING-0} : { *(.rel.got) }
3097 + .rela.got ${RELOCATING-0} : { *(.rela.got) }
3098 + ${OTHER_GOT_RELOC_SECTIONS}
3099 + ${REL_SDATA}
3100 + ${REL_SBSS}
3101 + ${REL_SDATA2}
3102 + ${REL_SBSS2}
3103 + .rel.bss ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }
3104 + .rela.bss ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }
3105 +EOF
3106 +if [ -n "$COMBRELOC" ]; then
3107 +cat <<EOF
3108 + .rel.dyn ${RELOCATING-0} :
3109 + {
3110 +EOF
3111 +sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/ \1/' $COMBRELOC
3112 +cat <<EOF
3113 + }
3114 + .rela.dyn ${RELOCATING-0} :
3115 + {
3116 +EOF
3117 +sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/ \1/' $COMBRELOC
3118 +cat <<EOF
3119 + }
3120 +EOF
3121 +fi
3122 +cat <<EOF
3123 + .rel.plt ${RELOCATING-0} : { *(.rel.plt) }
3124 + .rela.plt ${RELOCATING-0} : { *(.rela.plt) }
3125 + ${OTHER_PLT_RELOC_SECTIONS}
3126 +
3127 + .init ${RELOCATING-0} :
3128 + {
3129 + ${RELOCATING+${INIT_START}}
3130 + KEEP (*(.init))
3131 + ${RELOCATING+${INIT_END}}
3132 + } =${NOP-0}
3133 +
3134 + ${DATA_PLT-${BSS_PLT-${PLT}}}
3135 + .text ${RELOCATING-0} :
3136 + {
3137 + ${RELOCATING+${TEXT_START_SYMBOLS}}
3138 + *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
3139 + KEEP (*(.text.*personality*))
3140 + /* .gnu.warning sections are handled specially by elf32.em. */
3141 + *(.gnu.warning)
3142 + ${RELOCATING+${OTHER_TEXT_SECTIONS}}
3143 + } =${NOP-0}
3144 + .fini ${RELOCATING-0} :
3145 + {
3146 + ${RELOCATING+${FINI_START}}
3147 + KEEP (*(.fini))
3148 + ${RELOCATING+${FINI_END}}
3149 + } =${NOP-0}
3150 +
3151 + /* PSP library stub functions. */
3152 + .sceStub.text ${RELOCATING-0} : { *(.sceStub.text) *(SORT(.sceStub.text.*)) }
3153 +
3154 + ${RELOCATING+PROVIDE (__etext = .);}
3155 + ${RELOCATING+PROVIDE (_etext = .);}
3156 + ${RELOCATING+PROVIDE (etext = .);}
3157 +
3158 + /* PSP library entry table and library stub table. */
3159 + .lib.ent.top ${RELOCATING-0} : { *(.lib.ent.top) }
3160 + .lib.ent ${RELOCATING-0} : { *(.lib.ent) }
3161 + .lib.ent.btm ${RELOCATING-0} : { *(.lib.ent.btm) }
3162 +
3163 + .lib.stub.top ${RELOCATING-0} : { *(.lib.stub.top) }
3164 + .lib.stub ${RELOCATING-0} : { *(.lib.stub) }
3165 + .lib.stub.btm ${RELOCATING-0} : { *(.lib.stub.btm) }
3166 +
3167 + /* PSP read-only data for module info, NIDs, and Vstubs. The
3168 + .rodata.sceModuleInfo section must appear before the .rodata section
3169 + otherwise it would get absorbed into .rodata and the PSP bootloader
3170 + would be unable to locate the module info structure. */
3171 + .rodata.sceModuleInfo ${RELOCATING-0} : { *(.rodata.sceModuleInfo) }
3172 + .rodata.sceResident ${RELOCATING-0} : { *(.rodata.sceResident) }
3173 + .rodata.sceNid ${RELOCATING-0} : { *(.rodata.sceNid) }
3174 + .rodata.sceVstub ${RELOCATING-0} : { *(.rodata.sceVstub) *(SORT(.rodata.sceVstub.*)) }
3175 +
3176 + ${WRITABLE_RODATA-${RODATA}}
3177 + .rodata1 ${RELOCATING-0} : { *(.rodata1) }
3178 + ${CREATE_SHLIB-${SDATA2}}
3179 + ${CREATE_SHLIB-${SBSS2}}
3180 + ${OTHER_READONLY_SECTIONS}
3181 + .eh_frame_hdr : { *(.eh_frame_hdr) }
3182 + .eh_frame ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }
3183 + .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
3184 +
3185 + /* Adjust the address for the data segment. We want to adjust up to
3186 + the same address within the page on the next page up. */
3187 + ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}}
3188 + ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
3189 + ${CREATE_PIE+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
3190 +
3191 + /* Exception handling */
3192 + .eh_frame ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }
3193 + .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
3194 +
3195 + /* Thread Local Storage sections */
3196 + .tdata ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }
3197 + .tbss ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }
3198 +
3199 + /* Ensure the __preinit_array_start label is properly aligned. We
3200 + could instead move the label definition inside the section, but
3201 + the linker would then create the section even if it turns out to
3202 + be empty, which isn't pretty. */
3203 + ${RELOCATING+. = ALIGN(${ALIGNMENT});}
3204 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = .);}}
3205 + .preinit_array ${RELOCATING-0} : { KEEP (*(.preinit_array)) }
3206 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
3207 +
3208 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
3209 + .init_array ${RELOCATING-0} : { KEEP (*(.init_array)) }
3210 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
3211 +
3212 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
3213 + .fini_array ${RELOCATING-0} : { KEEP (*(.fini_array)) }
3214 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
3215 +
3216 + ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}}}
3217 + ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}}}
3218 + .jcr ${RELOCATING-0} : { KEEP (*(.jcr)) }
3219 +
3220 + ${RELOCATING+${DATARELRO}}
3221 + ${OTHER_RELRO_SECTIONS}
3222 + ${TEXT_DYNAMIC-${DYNAMIC}}
3223 + ${NO_SMALL_DATA+${RELRO_NOW+${GOT}}}
3224 + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}}}}
3225 + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}}}}
3226 + ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
3227 + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}}}}
3228 +
3229 + ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}}}
3230 +
3231 + .data ${RELOCATING-0} :
3232 + {
3233 + ${RELOCATING+${DATA_START_SYMBOLS}}
3234 + *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
3235 + KEEP (*(.gnu.linkonce.d.*personality*))
3236 + ${CONSTRUCTING+SORT(CONSTRUCTORS)}
3237 + }
3238 + .data1 ${RELOCATING-0} : { *(.data1) }
3239 + ${WRITABLE_RODATA+${RODATA}}
3240 + ${OTHER_READWRITE_SECTIONS}
3241 + ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}}}
3242 + ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}}}
3243 + ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}}}
3244 + ${RELOCATING+${OTHER_GOT_SYMBOLS}}
3245 + ${NO_SMALL_DATA-${GOT}}
3246 + ${OTHER_GOT_SECTIONS}
3247 + ${SDATA}
3248 + ${OTHER_SDATA_SECTIONS}
3249 + ${RELOCATING+_edata = .;}
3250 + ${RELOCATING+PROVIDE (edata = .);}
3251 + ${RELOCATING+__bss_start = .;}
3252 + ${RELOCATING+${OTHER_BSS_SYMBOLS}}
3253 + ${SBSS}
3254 + ${BSS_PLT+${PLT}}
3255 + .bss ${RELOCATING-0} :
3256 + {
3257 + *(.dynbss)
3258 + *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
3259 + *(COMMON)
3260 + /* Align here to ensure that the .bss section occupies space up to
3261 + _end. Align after .bss to ensure correct alignment even if the
3262 + .bss section disappears because there are no input sections. */
3263 + ${RELOCATING+. = ALIGN(${ALIGNMENT});}
3264 + }
3265 + ${OTHER_BSS_SECTIONS}
3266 + ${RELOCATING+. = ALIGN(${ALIGNMENT});}
3267 + ${RELOCATING+_end = .;}
3268 + ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
3269 + ${RELOCATING+PROVIDE (end = .);}
3270 + ${RELOCATING+${DATA_SEGMENT_END}}
3271 +
3272 + /* Stabs debugging sections. */
3273 + .stab 0 : { *(.stab) }
3274 + .stabstr 0 : { *(.stabstr) }
3275 + .stab.excl 0 : { *(.stab.excl) }
3276 + .stab.exclstr 0 : { *(.stab.exclstr) }
3277 + .stab.index 0 : { *(.stab.index) }
3278 + .stab.indexstr 0 : { *(.stab.indexstr) }
3279 +
3280 + .comment 0 : { *(.comment) }
3281 +
3282 + /* DWARF debug sections.
3283 + Symbols in the DWARF debugging sections are relative to the beginning
3284 + of the section so we begin them at 0. */
3285 +
3286 + /* DWARF 1 */
3287 + .debug 0 : { *(.debug) }
3288 + .line 0 : { *(.line) }
3289 +
3290 + /* GNU DWARF 1 extensions */
3291 + .debug_srcinfo 0 : { *(.debug_srcinfo) }
3292 + .debug_sfnames 0 : { *(.debug_sfnames) }
3293 +
3294 + /* DWARF 1.1 and DWARF 2 */
3295 + .debug_aranges 0 : { *(.debug_aranges) }
3296 + .debug_pubnames 0 : { *(.debug_pubnames) }
3297 +
3298 + /* DWARF 2 */
3299 + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
3300 + .debug_abbrev 0 : { *(.debug_abbrev) }
3301 + .debug_line 0 : { *(.debug_line) }
3302 + .debug_frame 0 : { *(.debug_frame) }
3303 + .debug_str 0 : { *(.debug_str) }
3304 + .debug_loc 0 : { *(.debug_loc) }
3305 + .debug_macinfo 0 : { *(.debug_macinfo) }
3306 +
3307 + /* SGI/MIPS DWARF 2 extensions */
3308 + .debug_weaknames 0 : { *(.debug_weaknames) }
3309 + .debug_funcnames 0 : { *(.debug_funcnames) }
3310 + .debug_typenames 0 : { *(.debug_typenames) }
3311 + .debug_varnames 0 : { *(.debug_varnames) }
3312 +
3313 + ${STACK_ADDR+${STACK}}
3314 + ${OTHER_SECTIONS}
3315 + ${RELOCATING+${OTHER_END_SYMBOLS}}
3316 + ${RELOCATING+${STACKNOTE}}
3317 +}
3318 +EOF
3319 diff -NrU3 binutils-2.23.2/opcodes/mips-dis.c binutils-2.23.2-patched/opcodes/mips-dis.c
3320 --- binutils-2.23.2/opcodes/mips-dis.c 2012-09-04 16:23:13.000000000 +0200
3321 +++ binutils-2.23.2-patched/opcodes/mips-dis.c 2020-04-23 17:57:30.329522786 +0200
3322 @@ -245,6 +245,139 @@
3323 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
3324 };
3325
3326 +static const char * const vfpu_sreg_names[128] = {
3327 + "S000", "S010", "S020", "S030", "S100", "S110", "S120", "S130",
3328 + "S200", "S210", "S220", "S230", "S300", "S310", "S320", "S330",
3329 + "S400", "S410", "S420", "S430", "S500", "S510", "S520", "S530",
3330 + "S600", "S610", "S620", "S630", "S700", "S710", "S720", "S730",
3331 + "S001", "S011", "S021", "S031", "S101", "S111", "S121", "S131",
3332 + "S201", "S211", "S221", "S231", "S301", "S311", "S321", "S331",
3333 + "S401", "S411", "S421", "S431", "S501", "S511", "S521", "S531",
3334 + "S601", "S611", "S621", "S631", "S701", "S711", "S721", "S731",
3335 + "S002", "S012", "S022", "S032", "S102", "S112", "S122", "S132",
3336 + "S202", "S212", "S222", "S232", "S302", "S312", "S322", "S332",
3337 + "S402", "S412", "S422", "S432", "S502", "S512", "S522", "S532",
3338 + "S602", "S612", "S622", "S632", "S702", "S712", "S722", "S732",
3339 + "S003", "S013", "S023", "S033", "S103", "S113", "S123", "S133",
3340 + "S203", "S213", "S223", "S233", "S303", "S313", "S323", "S333",
3341 + "S403", "S413", "S423", "S433", "S503", "S513", "S523", "S533",
3342 + "S603", "S613", "S623", "S633", "S703", "S713", "S723", "S733"
3343 +};
3344 +
3345 +static const char * const vfpu_vpreg_names[128] = {
3346 + "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130",
3347 + "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330",
3348 + "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530",
3349 + "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730",
3350 + "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103",
3351 + "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303",
3352 + "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503",
3353 + "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703",
3354 + "C002", "C012", "C022", "C032", "C102", "C112", "C122", "C132",
3355 + "C202", "C212", "C222", "C232", "C302", "C312", "C322", "C332",
3356 + "C402", "C412", "C422", "C432", "C502", "C512", "C522", "C532",
3357 + "C602", "C612", "C622", "C632", "C702", "C712", "C722", "C732",
3358 + "R020", "R021", "R022", "R023", "R120", "R121", "R122", "R123",
3359 + "R220", "R221", "R222", "R223", "R320", "R321", "R322", "R323",
3360 + "R420", "R421", "R422", "R423", "R520", "R521", "R522", "R523",
3361 + "R620", "R621", "R622", "R623", "R720", "R721", "R722", "R723"
3362 +};
3363 +
3364 +static const char * const vfpu_vtreg_names[128] = {
3365 + "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130",
3366 + "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330",
3367 + "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530",
3368 + "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730",
3369 + "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103",
3370 + "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303",
3371 + "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503",
3372 + "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703",
3373 + "C001", "C011", "C021", "C031", "C101", "C111", "C121", "C131",
3374 + "C201", "C211", "C221", "C231", "C301", "C311", "C321", "C331",
3375 + "C401", "C411", "C421", "C431", "C501", "C511", "C521", "C531",
3376 + "C601", "C611", "C621", "C631", "C701", "C711", "C721", "C731",
3377 + "R010", "R011", "R012", "R013", "R110", "R111", "R112", "R113",
3378 + "R210", "R211", "R212", "R213", "R310", "R311", "R312", "R313",
3379 + "R410", "R411", "R412", "R413", "R510", "R511", "R512", "R513",
3380 + "R610", "R611", "R612", "R613", "R710", "R711", "R712", "R713"
3381 +};
3382 +
3383 +static const char * const vfpu_vqreg_names[128] = {
3384 + "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130",
3385 + "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330",
3386 + "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530",
3387 + "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730",
3388 + "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103",
3389 + "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303",
3390 + "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503",
3391 + "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703",
3392 + "", "", "", "", "", "", "", "",
3393 + "", "", "", "", "", "", "", "",
3394 + "", "", "", "", "", "", "", "",
3395 + "", "", "", "", "", "", "", "",
3396 + "", "", "", "", "", "", "", "",
3397 + "", "", "", "", "", "", "", "",
3398 + "", "", "", "", "", "", "", "",
3399 + "", "", "", "", "", "", "", ""
3400 +};
3401 +
3402 +static const char * const vfpu_mpreg_names[128] = {
3403 + "M000", "", "M020", "", "M100", "", "M120", "",
3404 + "M200", "", "M220", "", "M300", "", "M320", "",
3405 + "M400", "", "M420", "", "M500", "", "M520", "",
3406 + "M600", "", "M620", "", "M700", "", "M720", "",
3407 + "E000", "", "E002", "", "E100", "", "E102", "",
3408 + "E200", "", "E202", "", "E300", "", "E302", "",
3409 + "E400", "", "E402", "", "E500", "", "E502", "",
3410 + "E600", "", "E602", "", "E700", "", "E702", "",
3411 + "M002", "", "M022", "", "M102", "", "M122", "",
3412 + "M202", "", "M222", "", "M302", "", "M322", "",
3413 + "M402", "", "M422", "", "M502", "", "M522", "",
3414 + "M602", "", "M622", "", "M702", "", "M722", "",
3415 + "E020", "", "E022", "", "E120", "", "E122", "",
3416 + "E220", "", "E222", "", "E320", "", "E322", "",
3417 + "E420", "", "E422", "", "E520", "", "E522", "",
3418 + "E620", "", "E622", "", "E720", "", "E722", ""
3419 +};
3420 +
3421 +static const char * const vfpu_mtreg_names[128] = {
3422 + "M000", "M010", "", "", "M100", "M110", "", "",
3423 + "M200", "M210", "", "", "M300", "M310", "", "",
3424 + "M400", "M410", "", "", "M500", "M510", "", "",
3425 + "M600", "M610", "", "", "M700", "M710", "", "",
3426 + "E000", "E001", "", "", "E100", "E101", "", "",
3427 + "E200", "E201", "", "", "E300", "E301", "", "",
3428 + "E400", "E401", "", "", "E500", "E501", "", "",
3429 + "E600", "E601", "", "", "E700", "E701", "", "",
3430 + "M001", "M011", "", "", "M101", "M111", "", "",
3431 + "M201", "M211", "", "", "M301", "M311", "", "",
3432 + "M401", "M411", "", "", "M501", "M511", "", "",
3433 + "M601", "M611", "", "", "M701", "M711", "", "",
3434 + "E010", "E011", "", "", "E110", "E111", "", "",
3435 + "E210", "E211", "", "", "E310", "E311", "", "",
3436 + "E410", "E411", "", "", "E510", "E511", "", "",
3437 + "E610", "E611", "", "", "E710", "E711", "", ""
3438 +};
3439 +
3440 +static const char * const vfpu_mqreg_names[128] = {
3441 + "M000", "", "", "", "M100", "", "", "",
3442 + "M200", "", "", "", "M300", "", "", "",
3443 + "M400", "", "", "", "M500", "", "", "",
3444 + "M600", "", "", "", "M700", "", "", "",
3445 + "E000", "", "", "", "E100", "", "", "",
3446 + "E200", "", "", "", "E300", "", "", "",
3447 + "E400", "", "", "", "E500", "", "", "",
3448 + "E600", "", "", "", "E700", "", "", "",
3449 + "", "", "", "", "", "", "", "",
3450 + "", "", "", "", "", "", "", "",
3451 + "", "", "", "", "", "", "", "",
3452 + "", "", "", "", "", "", "", "",
3453 + "", "", "", "", "", "", "", "",
3454 + "", "", "", "", "", "", "", "",
3455 + "", "", "", "", "", "", "", "",
3456 + "", "", "", "", "", "", "", ""
3457 +};
3458 +
3459 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
3460 {
3461 { 16, 1, "c0_config1" },
3462 @@ -471,6 +604,54 @@
3463 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3464 };
3465
3466 +static const char * const vfpu_cond_names[16] = {
3467 + "FL", "EQ", "LT", "LE", "TR", "NE", "GE", "GT",
3468 + "EZ", "EN", "EI", "ES", "NZ", "NN", "NI", "NS"
3469 +};
3470 +
3471 +static const char * const vfpu_const_names[20] = {
3472 + "",
3473 + "VFPU_HUGE",
3474 + "VFPU_SQRT2",
3475 + "VFPU_SQRT1_2",
3476 + "VFPU_2_SQRTPI",
3477 + "VFPU_2_PI",
3478 + "VFPU_1_PI",
3479 + "VFPU_PI_4",
3480 + "VFPU_PI_2",
3481 + "VFPU_PI",
3482 + "VFPU_E",
3483 + "VFPU_LOG2E",
3484 + "VFPU_LOG10E",
3485 + "VFPU_LN2",
3486 + "VFPU_LN10",
3487 + "VFPU_2PI",
3488 + "VFPU_PI_6",
3489 + "VFPU_LOG10TWO",
3490 + "VFPU_LOG2TEN",
3491 + "VFPU_SQRT3_2"
3492 +};
3493 +
3494 +#define VFPU_NUM_CONSTANTS \
3495 + ((sizeof vfpu_const_names) / (sizeof (vfpu_const_names[0])))
3496 +const unsigned int vfpu_num_constants = VFPU_NUM_CONSTANTS;
3497 +
3498 +static const char * const vfpu_rwb_names[4] = {
3499 + "wt", "wb", "", ""
3500 +};
3501 +
3502 +static const char * const pfx_cst_names[8] = {
3503 + "0", "1", "2", "1/2", "3", "1/3", "1/4", "1/6"
3504 +};
3505 +
3506 +static const char * const pfx_swz_names[4] = {
3507 + "x", "y", "z", "w"
3508 +};
3509 +
3510 +static const char * const pfx_sat_names[4] = {
3511 + "", "[0:1]", "", "[-1:1]"
3512 +};
3513 +
3514 struct mips_abi_choice
3515 {
3516 const char * name;
3517 @@ -550,6 +731,8 @@
3518 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3519 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3520 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3521 + { "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, ISA_MIPS2,
3522 + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3523
3524 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3525 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
3526 @@ -938,7 +1121,7 @@
3527 const fprintf_ftype infprintf = info->fprintf_func;
3528 unsigned int lsb, msb, msbd;
3529 void *is = info->stream;
3530 - int op;
3531 + int delta, op;
3532
3533 lsb = 0;
3534
3535 @@ -1406,6 +1589,349 @@
3536 infprintf (is, "$v%d", GET_OP (l, FT));
3537 break;
3538
3539 + case '?':
3540 + /* VFPU extensions. */
3541 + d++;
3542 + switch (*d)
3543 + {
3544 + case '\0':
3545 + /* xgettext:c-format */
3546 + infprintf (is,
3547 + _("# internal error, incomplete VFPU extension sequence (?)"));
3548 + return;
3549 +
3550 + case 'o':
3551 + delta = (l >> OP_SH_VFPU_DELTA) & OP_MASK_VFPU_DELTA;
3552 + if (delta & 0x8000)
3553 + delta |= ~0xffff;
3554 + infprintf (is, "%d",
3555 + delta);
3556 + break;
3557 +
3558 + case '0':
3559 + case '1':
3560 + case '2':
3561 + case '3':
3562 + {
3563 + unsigned int pos = *d, base = '0';
3564 + unsigned int negation = (l >> (pos - (base - VFPU_SH_PFX_NEG))) & VFPU_MASK_PFX_NEG;
3565 + unsigned int constant = (l >> (pos - (base - VFPU_SH_PFX_CST))) & VFPU_MASK_PFX_CST;
3566 + unsigned int abs_consthi =
3567 + (l >> (pos - (base - VFPU_SH_PFX_ABS_CSTHI))) & VFPU_MASK_PFX_ABS_CSTHI;
3568 + unsigned int swz_constlo = (l >> ((pos - base) * 2)) & VFPU_MASK_PFX_SWZ_CSTLO;
3569 +
3570 + if (negation)
3571 + infprintf (is, "-");
3572 + if (constant)
3573 + {
3574 + infprintf (is, "%s",
3575 + pfx_cst_names[(abs_consthi << 2) | swz_constlo]);
3576 + }
3577 + else
3578 + {
3579 + if (abs_consthi)
3580 + infprintf (is, "|%s|",
3581 + pfx_swz_names[swz_constlo]);
3582 + else
3583 + infprintf (is, "%s",
3584 + pfx_swz_names[swz_constlo]);
3585 + }
3586 + }
3587 + break;
3588 +
3589 + case '4':
3590 + case '5':
3591 + case '6':
3592 + case '7':
3593 + {
3594 + unsigned int pos = *d, base = '4';
3595 + unsigned int mask = (l >> (pos - (base - VFPU_SH_PFX_MASK))) & VFPU_MASK_PFX_MASK;
3596 + unsigned int saturation = (l >> ((pos - base) * 2)) & VFPU_MASK_PFX_SAT;
3597 +
3598 + if (mask)
3599 + infprintf (is, "m");
3600 + else
3601 + infprintf (is, "%s",
3602 + pfx_sat_names[saturation]);
3603 + }
3604 + break;
3605 +
3606 + case 'a':
3607 + {
3608 + unsigned int c = (l >> OP_SH_VFPU_CONST) & OP_MASK_VFPU_CONST;
3609 + if (c < vfpu_num_constants)
3610 + {
3611 + infprintf (is, "%s",
3612 + vfpu_const_names[c]);
3613 + }
3614 + break;
3615 + }
3616 +
3617 + case 'b':
3618 + /* 5-bit immediate value. */
3619 + infprintf (is, "%d",
3620 + (l >> OP_SH_VFPU_IMM5) & OP_MASK_VFPU_IMM5);
3621 + break;
3622 +
3623 + case 'c':
3624 + /* VFPU condition code. */
3625 + infprintf (is, "%d",
3626 + (l >> OP_SH_VFPU_CC) & OP_MASK_VFPU_CC);
3627 + break;
3628 +
3629 + case 'e':
3630 + /* 3-bit immediate value. */
3631 + infprintf (is, "%d",
3632 + (l >> OP_SH_VFPU_IMM3) & OP_MASK_VFPU_IMM3);
3633 + break;
3634 +
3635 + case 'f':
3636 + /* Conditional compare. */
3637 + infprintf (is, "%s",
3638 + vfpu_cond_names[(l >> OP_SH_VFPU_COND) & OP_MASK_VFPU_COND]);
3639 + /* Apparently this specifier is unused. */
3640 + d++;
3641 + break;
3642 +
3643 + case 'i':
3644 + /* 8-bit immediate value. */
3645 + infprintf (is, "0x%02x",
3646 + (l >> OP_SH_VFPU_IMM8) & OP_MASK_VFPU_IMM8);
3647 + break;
3648 +
3649 + case 'q':
3650 + /* VFPU control register (vmtvc). */
3651 + infprintf (is, "$%d",
3652 + (l >> OP_SH_VFPU_VMTVC) & OP_MASK_VFPU_VMTVC);
3653 + break;
3654 +
3655 + case 'r':
3656 + /* VFPU control register (vmfvc). */
3657 + infprintf (is, "$%d",
3658 + (l >> OP_SH_VFPU_VMFVC) & OP_MASK_VFPU_VMFVC);
3659 + break;
3660 +
3661 + case 'u':
3662 + /* Convert a VFPU 16-bit floating-point number to IEEE754. */
3663 + {
3664 + union float2int {
3665 + unsigned int i;
3666 + float f;
3667 + } float2int;
3668 + unsigned short float16 = (l >> OP_SH_VFPU_FLOAT16) & OP_MASK_VFPU_FLOAT16;
3669 + unsigned int sign = (float16 >> VFPU_SH_FLOAT16_SIGN) & VFPU_MASK_FLOAT16_SIGN;
3670 + int exponent = (float16 >> VFPU_SH_FLOAT16_EXP) & VFPU_MASK_FLOAT16_EXP;
3671 + unsigned int fraction = float16 & VFPU_MASK_FLOAT16_FRAC;
3672 + char signchar = '+' + ((sign == 1) * 2);
3673 +
3674 + if (exponent == VFPU_FLOAT16_EXP_MAX)
3675 + {
3676 + if (fraction == 0)
3677 + infprintf (is, "%cInf", signchar);
3678 + else
3679 + infprintf (is, "%cNaN", signchar);
3680 + }
3681 + else if (exponent == 0 && fraction == 0)
3682 + {
3683 + infprintf (is, "%c0", signchar);
3684 + }
3685 + else
3686 + {
3687 + if (exponent == 0)
3688 + {
3689 + do
3690 + {
3691 + fraction <<= 1;
3692 + exponent--;
3693 + }
3694 + while (!(fraction & (VFPU_MASK_FLOAT16_FRAC + 1)));
3695 +
3696 + fraction &= VFPU_MASK_FLOAT16_FRAC;
3697 + }
3698 +
3699 + /* Convert to 32-bit single-precision IEEE754. */
3700 + float2int.i = sign << 31;
3701 + float2int.i |= (exponent + 112) << 23;
3702 + float2int.i |= fraction << 13;
3703 + infprintf (is, "%g", float2int.f);
3704 + }
3705 + }
3706 + break;
3707 +
3708 + case 'w':
3709 + {
3710 + const char *elements[4];
3711 + unsigned int opcode = l & VFPU_MASK_OP_SIZE;
3712 + unsigned int rotators = (l >> OP_SH_VFPU_ROT) & OP_MASK_VFPU_ROT;
3713 + unsigned int opsize, rothi, rotlo, negation, i;
3714 +
3715 + /* Determine the operand size so we'll know how many elements to output. */
3716 + if (opcode == VFPU_OP_SIZE_PAIR)
3717 + opsize = 2;
3718 + else if (opcode == VFPU_OP_SIZE_TRIPLE)
3719 + opsize = 3;
3720 + else
3721 + opsize = (opcode == VFPU_OP_SIZE_QUAD) * 4; /* Sanity check. */
3722 +
3723 + rothi = (rotators >> VFPU_SH_ROT_HI) & VFPU_MASK_ROT_HI;
3724 + rotlo = (rotators >> VFPU_SH_ROT_LO) & VFPU_MASK_ROT_LO;
3725 + negation = (rotators >> VFPU_SH_ROT_NEG) & VFPU_MASK_ROT_NEG;
3726 +
3727 + if (rothi == rotlo)
3728 + {
3729 + if (negation)
3730 + {
3731 + elements[0] = "-s";
3732 + elements[1] = "-s";
3733 + elements[2] = "-s";
3734 + elements[3] = "-s";
3735 + }
3736 + else
3737 + {
3738 + elements[0] = "s";
3739 + elements[1] = "s";
3740 + elements[2] = "s";
3741 + elements[3] = "s";
3742 + }
3743 + }
3744 + else
3745 + {
3746 + elements[0] = "0";
3747 + elements[1] = "0";
3748 + elements[2] = "0";
3749 + elements[3] = "0";
3750 + }
3751 + if (negation)
3752 + elements[rothi] = "-s";
3753 + else
3754 + elements[rothi] = "s";
3755 + elements[rotlo] = "c";
3756 +
3757 + infprintf (is, "[");
3758 + i = 0;
3759 + for (;;)
3760 + {
3761 + infprintf (is, "%s",
3762 + elements[i++]);
3763 + if (i >= opsize)
3764 + break;
3765 + infprintf (is, ",");
3766 + }
3767 + infprintf (is, "]");
3768 + }
3769 + break;
3770 +
3771 + case 'd':
3772 + case 'm':
3773 + case 'n':
3774 + case 's':
3775 + case 't':
3776 + case 'v':
3777 + case 'x':
3778 + {
3779 + unsigned int vreg = 0;
3780 +
3781 + /* The first char specifies the bitfield that contains the register number. */
3782 + switch (*d)
3783 + {
3784 + case 'd':
3785 + case 'v':
3786 + case 'x':
3787 + vreg = (l >> OP_SH_VFPU_VD) & OP_MASK_VFPU_VD;
3788 + break;
3789 +
3790 + case 'm':
3791 + /* Combine bits 0-4 of vt with bits 5-6 of vt. */
3792 + vreg = ((l >> OP_SH_VFPU_VT_LO) & OP_MASK_VFPU_VT_LO)
3793 + | ((l & OP_MASK_VFPU_VT_HI2) << OP_SH_VFPU_VT_HI);
3794 + break;
3795 +
3796 + case 'n':
3797 + /* Combine bits 0-4 of vt with bit 5 of vt. */
3798 + vreg = ((l >> OP_SH_VFPU_VT_LO) & OP_MASK_VFPU_VT_LO)
3799 + | ((l & OP_MASK_VFPU_VT_HI1) << OP_SH_VFPU_VT_HI);
3800 + break;
3801 +
3802 + case 's':
3803 + {
3804 + unsigned int temp_vreg = l >> OP_SH_VFPU_VS;
3805 +
3806 + vreg = temp_vreg & OP_MASK_VFPU_VS;
3807 + if ((l & VFPU_OP_VT_VS_VD) == VFPU_OPCODE_VMMUL)
3808 + {
3809 + /* vmmul instructions have the RXC bit (bit 13) inverted. */
3810 + if (temp_vreg & 0x20)
3811 + vreg = temp_vreg & 0x5f;
3812 + else
3813 + vreg |= 0x20;
3814 + }
3815 + }
3816 + break;
3817 +
3818 + case 't':
3819 + vreg = (l >> OP_SH_VFPU_VT) & OP_MASK_VFPU_VT;
3820 + break;
3821 + }
3822 +
3823 + /* The next char is the register set vreg comes from. */
3824 + d++;
3825 + switch (*d)
3826 + {
3827 + case '0':
3828 + infprintf (is, "%s.s",
3829 + vfpu_sreg_names[vreg]);
3830 + break;
3831 +
3832 + case '1':
3833 + infprintf (is, "%s.p",
3834 + vfpu_vpreg_names[vreg]);
3835 + break;
3836 +
3837 + case '2':
3838 + infprintf (is, "%s.t",
3839 + vfpu_vtreg_names[vreg]);
3840 + break;
3841 +
3842 + case '3':
3843 + infprintf (is, "%s.q",
3844 + vfpu_vqreg_names[vreg]);
3845 + break;
3846 +
3847 + case '5':
3848 + infprintf (is, "%s.p",
3849 + vfpu_mpreg_names[vreg]);
3850 + break;
3851 +
3852 + case '6':
3853 + infprintf (is, "%s.t",
3854 + vfpu_mtreg_names[vreg]);
3855 + break;
3856 +
3857 + case '7':
3858 + infprintf (is, "%s.q",
3859 + vfpu_mqreg_names[vreg]);
3860 + break;
3861 +
3862 + default:
3863 + /* xgettext:c-format */
3864 + infprintf (is,
3865 + _("# internal error, undefined vreg modifier(%c)"),
3866 + *d);
3867 + break;
3868 + }
3869 +
3870 + /* The last char is unused for disassembly. */
3871 + d++;
3872 + }
3873 + break;
3874 +
3875 + case 'z':
3876 + infprintf (is, "%s",
3877 + vfpu_rwb_names[(l >> OP_SH_VFPU_RWB) & OP_MASK_VFPU_RWB]);
3878 + break;
3879 + }
3880 + break;
3881 +
3882 default:
3883 /* xgettext:c-format */
3884 infprintf (is, _("# internal error, undefined modifier (%c)"), *d);
3885 diff -NrU3 binutils-2.23.2/opcodes/mips-opc.c binutils-2.23.2-patched/opcodes/mips-opc.c
3886 --- binutils-2.23.2/opcodes/mips-opc.c 2012-09-04 16:21:10.000000000 +0200
3887 +++ binutils-2.23.2-patched/opcodes/mips-opc.c 2020-04-23 17:57:30.331522776 +0200
3888 @@ -122,9 +122,10 @@
3889 #define N5 (INSN_5400 | INSN_5500)
3890 #define N54 INSN_5400
3891 #define N55 INSN_5500
3892 +#define AL INSN_ALLEGREX
3893 #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
3894 -#define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
3895 -#define IOCT2 INSN_OCTEON2
3896 +#define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
3897 +#define IOCT2 (INSN_OCTEON2)
3898 #define XLR INSN_XLR
3899
3900 #define G1 (T3 \
3901 @@ -405,6 +406,7 @@
3902 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
3903 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
3904 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
3905 +{"break", "B", 0x0000000d, 0xfc00003f, TRAP, 0, AL },
3906 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
3907 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
3908 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
3909 @@ -587,7 +589,7 @@
3910 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
3911 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
3912 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
3913 -{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3},
3914 +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3|AL},
3915 {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3},
3916 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
3917 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
3918 @@ -605,7 +607,9 @@
3919 {"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */
3920 {"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
3921 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
3922 +{"clo", "d,s", 0x00000017, 0xfc1f07ff, WR_d|RD_s, 0, AL },
3923 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
3924 +{"clz", "d,s", 0x00000016, 0xfc1f07ff, WR_d|RD_s, 0, AL },
3925 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
3926 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
3927 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
3928 @@ -630,16 +634,16 @@
3929 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33 },
3930 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
3931 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
3932 +{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
3933 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
3934 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
3935 -{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
3936 -{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
3937 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
3938 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
3939 +{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
3940 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
3941 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
3942 {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR },
3943 -{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
3944 +{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL },
3945 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
3946 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
3947 /* dctr and dctw are used on the r5000. */
3948 @@ -728,7 +732,7 @@
3949 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
3950 {"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
3951 {"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
3952 -{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
3953 +{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5|AL },
3954 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
3955 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
3956 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
3957 @@ -777,10 +781,10 @@
3958 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
3959 {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
3960 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
3961 -{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
3962 +{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32|AL },
3963 {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
3964 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
3965 -{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
3966 +{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33|AL },
3967 {"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT },
3968 {"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */
3969 {"exts", "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT },
3970 @@ -789,7 +793,7 @@
3971 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
3972 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
3973 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
3974 -{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
3975 +{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33|AL },
3976 {"iret", "", 0x42000038, 0xffffffff, NODS, 0, MC },
3977 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
3978 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
3979 @@ -851,18 +855,10 @@
3980 {"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
3981 {"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
3982 {"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
3983 -{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
3984 -{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
3985 -{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
3986 -{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
3987 -{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
3988 -{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
3989 -{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
3990 -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
3991 -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
3992 -{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
3993 -{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
3994 -{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
3995 +/* ldc1 is at the bottom of the table. */
3996 +/* ldc2 is at the bottom of the table. */
3997 +/* ldc3 is at the bottom of the table. */
3998 +{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL },
3999 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
4000 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
4001 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
4002 @@ -892,8 +888,7 @@
4003 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
4004 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
4005 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
4006 -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
4007 -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
4008 +/* lwc2 is at the bottom of the table. */
4009 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
4010 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
4011 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
4012 @@ -933,12 +928,14 @@
4013 {"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
4014 {"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
4015 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
4016 +{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
4017 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
4018 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
4019 {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
4020 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
4021 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
4022 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
4023 +{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
4024 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
4025 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
4026 {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
4027 @@ -979,7 +976,7 @@
4028 /* mfc2 is at the bottom of the table. */
4029 /* mfhc2 is at the bottom of the table. */
4030 /* mfc3 is at the bottom of the table. */
4031 -{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
4032 +{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5|AL },
4033 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
4034 {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
4035 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
4036 @@ -1001,7 +998,7 @@
4037 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
4038 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
4039 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
4040 -{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F },
4041 +{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|AL },
4042 {"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A },
4043 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
4044 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
4045 @@ -1015,7 +1012,7 @@
4046 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
4047 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
4048 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
4049 -{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F },
4050 +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|AL },
4051 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
4052 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
4053 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
4054 @@ -1043,9 +1040,11 @@
4055 {"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
4056 {"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
4057 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
4058 +{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
4059 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
4060 {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
4061 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
4062 +{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
4063 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
4064 {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
4065 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
4066 @@ -1060,7 +1059,7 @@
4067 /* mtc2 is at the bottom of the table. */
4068 /* mthc2 is at the bottom of the table. */
4069 /* mtc3 is at the bottom of the table. */
4070 -{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
4071 +{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5|AL },
4072 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
4073 {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
4074 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
4075 @@ -1254,13 +1253,13 @@
4076 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
4077 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
4078 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
4079 -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT },
4080 -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT },
4081 -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT },
4082 -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT },
4083 -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT },
4084 -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT },
4085 -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT },
4086 +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT|AL },
4087 +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT|AL },
4088 +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT|AL },
4089 +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT|AL },
4090 +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT|AL },
4091 +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT|AL },
4092 +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT|AL },
4093 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
4094 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
4095 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
4096 @@ -1299,24 +1298,17 @@
4097 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
4098 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 },
4099 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
4100 -{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
4101 -{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
4102 -{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
4103 -{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
4104 -{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
4105 -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
4106 -{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
4107 -{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
4108 -{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
4109 -{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
4110 -{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
4111 -{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
4112 +/* sdc1 is at the bottom of the table. */
4113 +/* sdc2 is at the bottom of the table. */
4114 +/* sdc3 is at the bottom of the table. */
4115 +/* s.d (sdc1 is at the bottom of the table. */
4116 +{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3|AL },
4117 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
4118 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
4119 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
4120 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33 },
4121 -{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
4122 -{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
4123 +{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
4124 +{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
4125 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
4126 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
4127 {"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
4128 @@ -1436,8 +1428,7 @@
4129 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
4130 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
4131 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
4132 -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
4133 -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
4134 +/* swc2 is at the bottom of the table. */
4135 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
4136 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
4137 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
4138 @@ -1534,7 +1525,8 @@
4139 {"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55 },
4140 {"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1 },
4141 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
4142 -{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
4143 +{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
4144 +{"wsbw", "d,t", 0x7c0000e0, 0xffe007ff, WR_d|RD_t, 0, AL },
4145 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
4146 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
4147 {"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
4148 @@ -1550,6 +1542,321 @@
4149 {"zcb", "(b)", 0x7000071f, 0xfc1fffff, SM|RD_b, 0, IOCT2 },
4150 {"zcbt", "(b)", 0x7000075f, 0xfc1fffff, SM|RD_b, 0, IOCT2 },
4151
4152 +/* Sony Allegrex CPU core. */
4153 +{"bitrev", "d,t", 0x7c000520, 0xffe007ff, WR_d|RD_t, 0, AL },
4154 +/* From "MIPS DSP ASU", because instructions with the same name need to be next to each other */
4155 +{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
4156 +{"mfic", "t,G", 0x70000024, 0xffe007ff, LCD|WR_t|RD_C0, 0, AL },
4157 +{"mtic", "t,G", 0x70000026, 0xffe007ff, COD|RD_t|WR_C0, 0, AL },
4158 +
4159 +/* Sony Allegrex VFPU instructions. */
4160 +{"bvf", "?c,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, AL },
4161 +{"bvfl", "?c,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, AL },
4162 +{"bvt", "?c,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, AL },
4163 +{"bvtl", "?c,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, AL },
4164 +{"lv.s", "?m0x,?o(b)", 0xc8000000, 0xfc000000, CLD|RD_s|WR_CC, 0, AL },
4165 +{"lv.s", "?m0x,A(b)", 0, (int) M_LV_Q_AB, INSN_MACRO, 0, AL },
4166 +{"ulv.s", "?m0x,o(b)", 0, (int) M_ULV_S, INSN_MACRO, 0, AL },
4167 +{"lv.q", "?n3x,?o(b)", 0xd8000000, 0xfc000002, CLD|RD_s|WR_CC, 0, AL },
4168 +{"lv.q", "?n3x,A(b)", 0, (int) M_LV_Q_AB_2, INSN_MACRO, 0, AL },
4169 +{"ulv.q", "?n3x,?o(b)", 0, (int) M_ULV_Q, INSN_MACRO, 0, AL },
4170 +{"ulv.q", "?n3x,A(b)", 0, (int) M_ULV_Q_AB, INSN_MACRO, 0, AL },
4171 +{"lvi.s", "?t0x,l?y0", 0, (int) M_LVI_S, INSN_MACRO, 0, AL },
4172 +{"lvi.p", "?t1x,?[l?y0,l?y1?]", 0, (int) M_LVI_P, INSN_MACRO, 0, AL },
4173 +{"lvi.t", "?t2x,?[l?y0,l?y1,l?y2?]", 0, (int) M_LVI_T, INSN_MACRO, 0, AL },
4174 +{"lvi.q", "?t3x,?[l?y0,l?y1,l?y2,l?y3?]", 0, (int) M_LVI_Q, INSN_MACRO, 0, AL },
4175 +{"lvhi.s", "?t0x,?[?u?y0,?u?y1?]", 0, (int) M_LVHI_S, INSN_MACRO, 0, AL },
4176 +{"lvhi.p", "?t1x,?[?u?y0,?u?y1,?u?y2,?u?y3?]", 0, (int) M_LVHI_P, INSN_MACRO, 0, AL },
4177 +{"sv.s", "?m0x,?o(b)", 0xe8000000, 0xfc000000, SM|RD_s|RD_C2, 0, AL },
4178 +{"sv.s", "?m0x,A(b)", 0, (int) M_SV_S_AB, INSN_MACRO, 0, AL },
4179 +{"usv.s", "?m0x,o(b)", 0, (int) M_USV_S, INSN_MACRO, 0, AL },
4180 +{"sv.q", "?n3x,?o(b)", 0xf8000000, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
4181 +{"sv.q", "?n3x,?o(b),?z", 0xf8000000, 0xfc000000, SM|RD_s|RD_C2, 0, AL },
4182 +{"sv.q", "?n3x,A(b)", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL },
4183 +{"sv.q", "?n3x,A(b),?z", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL },
4184 +{"sv.q", "?n3x,A,?z", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL },
4185 +{"usv.q", "?n3x,?o(b)", 0, (int) M_USV_Q, INSN_MACRO, 0, AL },
4186 +{"usv.q", "?n3x,A(b)", 0, (int) M_USV_Q_AB, INSN_MACRO, 0, AL },
4187 +{"vwb.q", "?n3x,?o(b)", 0xf8000002, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
4188 +{"lvl.q", "?n3x,?o(b)", 0xd4000000, 0xfc000002, CLD|RD_s|WR_CC, 0, AL },
4189 +{"lvl.q", "?n3x,A(b)", 0, (int) M_LVL_Q_AB, INSN_MACRO, 0, AL },
4190 +{"lvr.q", "?n3x,?o(b)", 0xd4000002, 0xfc000002, CLD|RD_s|WR_CC, 0, AL },
4191 +{"lvr.q", "?n3x,A(b)", 0, (int) M_LVR_Q_AB, INSN_MACRO, 0, AL },
4192 +{"svl.q", "?n3x,?o(b)", 0xf4000000, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
4193 +{"svl.q", "?n3x,A(b)", 0, (int) M_SVL_Q_AB, INSN_MACRO, 0, AL },
4194 +{"svr.q", "?n3x,?o(b)", 0xf4000002, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
4195 +{"svr.q", "?n3x,A(b)", 0, (int) M_SVR_Q_AB, INSN_MACRO, 0, AL },
4196 +{"mtv", "t,?d0z", 0x48e00000, 0xffe0ff80, LCD|WR_t|WR_C2, 0, AL },
4197 +{"mfv", "t,?d0z", 0x48600000, 0xffe0ff80, COD|RD_t|WR_CC|RD_C2, 0, AL },
4198 +{"mtvc", "t,?q", 0x48e00000, 0xffe0ff00, LCD|WR_t|WR_C2, 0, AL },
4199 +{"mfvc", "t,?q", 0x48600000, 0xffe0ff00, COD|RD_t|WR_CC|RD_C2, 0, AL },
4200 +{"vmtvc", "?q,?s0y", 0xd0510000, 0xffff8000, WR_C2, 0, AL },
4201 +{"vmfvc", "?d0z,?r", 0xd0500000, 0xffff0080, RD_C2, 0, AL },
4202 +{"vadd.q", "?d3d,?s3s,?t3t", 0x60008080, 0xff808080, RD_C2, 0, AL },
4203 +{"vsub.q", "?d3d,?s3s,?t3t", 0x60808080, 0xff808080, RD_C2, 0, AL },
4204 +{"vdiv.q", "?x3z,?s3y,?t3x", 0x63808080, 0xff808080, RD_C2, 0, AL },
4205 +{"vmul.q", "?d3d,?s3s,?t3t", 0x64008080, 0xff808080, RD_C2, 0, AL },
4206 +{"vdot.q", "?d0d,?s3s,?t3t", 0x64808080, 0xff808080, RD_C2, 0, AL },
4207 +{"vscl.q", "?d3d,?s3s,?t0x", 0x65008080, 0xff808080, RD_C2, 0, AL },
4208 +{"vhdp.q", "?d0d,?s3y,?t3t", 0x66008080, 0xff808080, RD_C2, 0, AL },
4209 +{"vcmp.q", "?f2,?s3s,?t3t", 0x6c008080, 0xff8080f0, RD_C2, 0, AL },
4210 +{"vcmp.q", "?f1,?s3s", 0x6c008080, 0xffff80f0, RD_C2, 0, AL },
4211 +{"vcmp.q", "?f0", 0x6c008080, 0xfffffff0, RD_C2, 0, AL },
4212 +{"vmin.q", "?d3d,?s3s,?t3t", 0x6d008080, 0xff808080, RD_C2, 0, AL },
4213 +{"vmax.q", "?d3d,?s3s,?t3t", 0x6d808080, 0xff808080, RD_C2, 0, AL },
4214 +{"vsgn.q", "?d3d,?s3s", 0xd04a8080, 0xffff8080, RD_C2, 0, AL },
4215 +{"vcst.q", "?d3d,?a", 0xd0608080, 0xffe0ff80, RD_C2, 0, AL },
4216 +{"vscmp.q", "?d3d,?s3s,?t3t", 0x6e808080, 0xff808080, RD_C2, 0, AL },
4217 +{"vsge.q", "?d3d,?s3s,?t3t", 0x6f008080, 0xff808080, RD_C2, 0, AL },
4218 +{"vslt.q", "?d3d,?s3s,?t3t", 0x6f808080, 0xff808080, RD_C2, 0, AL },
4219 +{"vi2uc.q", "?d0m,?s3w", 0xd03c8080, 0xffff8080, RD_C2, 0, AL },
4220 +{"vi2c.q", "?d0m,?s3w", 0xd03d8080, 0xffff8080, RD_C2, 0, AL },
4221 +{"vi2us.q", "?d1m,?s3w", 0xd03e8080, 0xffff8080, RD_C2, 0, AL },
4222 +{"vi2s.q", "?d1m,?s3w", 0xd03f8080, 0xffff8080, RD_C2, 0, AL },
4223 +{"vmov.q", "?d3d,?s3s", 0xd0008080, 0xffff8080, RD_C2, 0, AL },
4224 +{"vabs.q", "?d3d,?s3w", 0xd0018080, 0xffff8080, RD_C2, 0, AL },
4225 +{"vneg.q", "?d3d,?s3w", 0xd0028080, 0xffff8080, RD_C2, 0, AL },
4226 +{"vidt.q", "?d3d", 0xd0038080, 0xffffff80, RD_C2, 0, AL },
4227 +{"vsat0.q", "?d3z,?s3s", 0xd0048080, 0xffff8080, RD_C2, 0, AL },
4228 +{"vsat1.q", "?d3z,?s3s", 0xd0058080, 0xffff8080, RD_C2, 0, AL },
4229 +{"vzero.q", "?d3d", 0xd0068080, 0xffffff80, RD_C2, 0, AL },
4230 +{"vone.q", "?d3d", 0xd0078080, 0xffffff80, RD_C2, 0, AL },
4231 +{"vrcp.q", "?x3z,?s3y", 0xd0108080, 0xffff8080, RD_C2, 0, AL },
4232 +{"vrsq.q", "?x3z,?s3y", 0xd0118080, 0xffff8080, RD_C2, 0, AL },
4233 +{"vsin.q", "?x3z,?s3y", 0xd0128080, 0xffff8080, RD_C2, 0, AL },
4234 +{"vcos.q", "?x3z,?s3y", 0xd0138080, 0xffff8080, RD_C2, 0, AL },
4235 +{"vexp2.q", "?x3z,?s3y", 0xd0148080, 0xffff8080, RD_C2, 0, AL },
4236 +{"vlog2.q", "?x3z,?s3y", 0xd0158080, 0xffff8080, RD_C2, 0, AL },
4237 +{"vsqrt.q", "?x3z,?s3y", 0xd0168080, 0xffff8080, RD_C2, 0, AL },
4238 +{"vasin.q", "?x3z,?s3y", 0xd0178080, 0xffff8080, RD_C2, 0, AL },
4239 +{"vnrcp.q", "?x3z,?s3y", 0xd0188080, 0xffff8080, RD_C2, 0, AL },
4240 +{"vnsin.q", "?x3z,?s3y", 0xd01a8080, 0xffff8080, RD_C2, 0, AL },
4241 +{"vrexp2.q", "?x3z,?s3y", 0xd01c8080, 0xffff8080, RD_C2, 0, AL },
4242 +{"vrndi.q", "?d3z", 0xd0218080, 0xffffff80, RD_C2, 0, AL },
4243 +{"vrndf1.q", "?d3z", 0xd0228080, 0xffffff80, RD_C2, 0, AL },
4244 +{"vrndf2.q", "?d3z", 0xd0238080, 0xffffff80, RD_C2, 0, AL },
4245 +{"vf2h.q", "?d1m,?s3s", 0xd0328080, 0xffff8080, RD_C2, 0, AL },
4246 +{"vsrt1.q", "?d3d,?s3s", 0xd0408080, 0xffff8080, RD_C2, 0, AL },
4247 +{"vsrt2.q", "?d3d,?s3s", 0xd0418080, 0xffff8080, RD_C2, 0, AL },
4248 +{"vsrt3.q", "?d3d,?s3s", 0xd0488080, 0xffff8080, RD_C2, 0, AL },
4249 +{"vsrt4.q", "?d3d,?s3s", 0xd0498080, 0xffff8080, RD_C2, 0, AL },
4250 +{"vbfy1.q", "?d3d,?s3s", 0xd0428080, 0xffff8080, RD_C2, 0, AL },
4251 +{"vbfy2.q", "?d3d,?s3s", 0xd0438080, 0xffff8080, RD_C2, 0, AL },
4252 +{"vocp.q", "?d3d,?s3y", 0xd0448080, 0xffff8080, RD_C2, 0, AL },
4253 +{"vfad.q", "?d0d,?s3s", 0xd0468080, 0xffff8080, RD_C2, 0, AL },
4254 +{"vavg.q", "?d0d,?s3s", 0xd0478080, 0xffff8080, RD_C2, 0, AL },
4255 +{"vf2in.q", "?d3m,?s3s,?b", 0xd2008080, 0xffe08080, RD_C2, 0, AL },
4256 +{"vf2iz.q", "?d3m,?s3s,?b", 0xd2208080, 0xffe08080, RD_C2, 0, AL },
4257 +{"vf2iu.q", "?d3m,?s3s,?b", 0xd2408080, 0xffe08080, RD_C2, 0, AL },
4258 +{"vf2id.q", "?d3m,?s3s,?b", 0xd2608080, 0xffe08080, RD_C2, 0, AL },
4259 +{"vi2f.q", "?d3d,?s3w,?b", 0xd2808080, 0xffe08080, RD_C2, 0, AL },
4260 +{"vcmov.q", "?d3d,?s3s,?e", 0, (int) M_VCMOV_Q, INSN_MACRO, 0, AL },
4261 +{"vcmovt.q", "?d3d,?s3s,?e", 0xd2a08080, 0xfff88080, RD_C2, 0, AL },
4262 +{"vcmovf.q", "?d3d,?s3s,?e", 0xd2a88080, 0xfff88080, RD_C2, 0, AL },
4263 +{"vmmul.q", "?v7z,?s7y,?t7x", 0xf0008080, 0xff808080, RD_C2, 0, AL },
4264 +{"vtfm4.q", "?v3z,?s7y,?t3x", 0xf1808080, 0xff808080, RD_C2, 0, AL },
4265 +{"vhtfm4.q", "?v3z,?s7y,?t3x", 0xf1808000, 0xff808080, RD_C2, 0, AL },
4266 +{"vmscl.q", "?x7z,?s7y,?t0x", 0xf2008080, 0xff808080, RD_C2, 0, AL },
4267 +{"vqmul.q", "?v3z,?s3y,?t3x", 0xf2808080, 0xff808080, RD_C2, 0, AL },
4268 +{"vmmov.q", "?x7z,?s7y", 0xf3808080, 0xffff8080, RD_C2, 0, AL },
4269 +{"vmidt.q", "?d7z", 0xf3838080, 0xffffff80, RD_C2, 0, AL },
4270 +{"vmzero.q", "?d7z", 0xf3868080, 0xffffff80, RD_C2, 0, AL },
4271 +{"vmone.q", "?d7z", 0xf3878080, 0xffffff80, RD_C2, 0, AL },
4272 +{"vrot.q", "?x3z,?s0y,?w", 0xf3a08080, 0xffe08080, RD_C2, 0, AL },
4273 +{"vt4444.q", "?d1z,?s3w", 0xd0598080, 0xffff8080, RD_C2, 0, AL },
4274 +{"vt5551.q", "?d1z,?s3w", 0xd05a8080, 0xffff8080, RD_C2, 0, AL },
4275 +{"vt5650.q", "?d1z,?s3w", 0xd05b8080, 0xffff8080, RD_C2, 0, AL },
4276 +{"vadd.t", "?d2d,?s2s,?t2t", 0x60008000, 0xff808080, RD_C2, 0, AL },
4277 +{"vsub.t", "?d2d,?s2s,?t2t", 0x60808000, 0xff808080, RD_C2, 0, AL },
4278 +{"vdiv.t", "?x2z,?s2y,?t2x", 0x63808000, 0xff808080, RD_C2, 0, AL },
4279 +{"vmul.t", "?d2d,?s2s,?t2t", 0x64008000, 0xff808080, RD_C2, 0, AL },
4280 +{"vdot.t", "?d0d,?s2s,?t2t", 0x64808000, 0xff808080, RD_C2, 0, AL },
4281 +{"vscl.t", "?d2d,?s2s,?t0x", 0x65008000, 0xff808080, RD_C2, 0, AL },
4282 +{"vhdp.t", "?d0d,?s2y,?t2t", 0x66008000, 0xff808080, RD_C2, 0, AL },
4283 +{"vcrs.t", "?d2d,?s2y,?t2x", 0x66808000, 0xff808080, RD_C2, 0, AL },
4284 +{"vcmp.t", "?f2,?s2s,?t2t", 0x6c008000, 0xff8080f0, RD_C2, 0, AL },
4285 +{"vcmp.t", "?f1,?s2s", 0x6c008000, 0xffff80f0, RD_C2, 0, AL },
4286 +{"vcmp.t", "?f0", 0x6c008000, 0xfffffff0, RD_C2, 0, AL },
4287 +{"vmin.t", "?d2d,?s2s,?t2t", 0x6d008000, 0xff808080, RD_C2, 0, AL },
4288 +{"vmax.t", "?d2d,?s2s,?t2t", 0x6d808000, 0xff808080, RD_C2, 0, AL },
4289 +{"vsgn.t", "?d2d,?s2s", 0xd04a8000, 0xffff8080, RD_C2, 0, AL },
4290 +{"vcst.t", "?d2d,?a", 0xd0608000, 0xffe0ff80, RD_C2, 0, AL },
4291 +{"vscmp.t", "?d2d,?s2s,?t2t", 0x6e808000, 0xff808080, RD_C2, 0, AL },
4292 +{"vsge.t", "?d2d,?s2s,?t2t", 0x6f008000, 0xff808080, RD_C2, 0, AL },
4293 +{"vslt.t", "?d2d,?s2s,?t2t", 0x6f808000, 0xff808080, RD_C2, 0, AL },
4294 +{"vmov.t", "?d2d,?s2s", 0xd0008000, 0xffff8080, RD_C2, 0, AL },
4295 +{"vabs.t", "?d2d,?s2w", 0xd0018000, 0xffff8080, RD_C2, 0, AL },
4296 +{"vneg.t", "?d2d,?s2w", 0xd0028000, 0xffff8080, RD_C2, 0, AL },
4297 +{"vsat0.t", "?d2z,?s2s", 0xd0048000, 0xffff8080, RD_C2, 0, AL },
4298 +{"vsat1.t", "?d2z,?s2s", 0xd0058000, 0xffff8080, RD_C2, 0, AL },
4299 +{"vzero.t", "?d2d", 0xd0068000, 0xffffff80, RD_C2, 0, AL },
4300 +{"vone.t", "?d2d", 0xd0078000, 0xffffff80, RD_C2, 0, AL },
4301 +{"vrcp.t", "?x2z,?s2y", 0xd0108000, 0xffff8080, RD_C2, 0, AL },
4302 +{"vrsq.t", "?x2z,?s2y", 0xd0118000, 0xffff8080, RD_C2, 0, AL },
4303 +{"vsin.t", "?x2z,?s2y", 0xd0128000, 0xffff8080, RD_C2, 0, AL },
4304 +{"vcos.t", "?x2z,?s2y", 0xd0138000, 0xffff8080, RD_C2, 0, AL },
4305 +{"vexp2.t", "?x2z,?s2y", 0xd0148000, 0xffff8080, RD_C2, 0, AL },
4306 +{"vlog2.t", "?x2z,?s2y", 0xd0158000, 0xffff8080, RD_C2, 0, AL },
4307 +{"vsqrt.t", "?x2z,?s2y", 0xd0168000, 0xffff8080, RD_C2, 0, AL },
4308 +{"vasin.t", "?x2z,?s2y", 0xd0178000, 0xffff8080, RD_C2, 0, AL },
4309 +{"vnrcp.t", "?x2z,?s2y", 0xd0188000, 0xffff8080, RD_C2, 0, AL },
4310 +{"vnsin.t", "?x2z,?s2y", 0xd01a8000, 0xffff8080, RD_C2, 0, AL },
4311 +{"vrexp2.t", "?x2z,?s2y", 0xd01c8000, 0xffff8080, RD_C2, 0, AL },
4312 +{"vrndi.t", "?d2z", 0xd0218000, 0xffffff80, RD_C2, 0, AL },
4313 +{"vrndf1.t", "?d2z", 0xd0228000, 0xffffff80, RD_C2, 0, AL },
4314 +{"vrndf2.t", "?d2z", 0xd0238000, 0xffffff80, RD_C2, 0, AL },
4315 +{"vocp.t", "?d2d,?s2y", 0xd0448000, 0xffff8080, RD_C2, 0, AL },
4316 +{"vfad.t", "?d0d,?s2s", 0xd0468000, 0xffff8080, RD_C2, 0, AL },
4317 +{"vavg.t", "?d0d,?s2s", 0xd0478000, 0xffff8080, RD_C2, 0, AL },
4318 +{"vf2in.t", "?d2m,?s2s,?b", 0xd2008000, 0xffe08080, RD_C2, 0, AL },
4319 +{"vf2iz.t", "?d2m,?s2s,?b", 0xd2208000, 0xffe08080, RD_C2, 0, AL },
4320 +{"vf2iu.t", "?d2m,?s2s,?b", 0xd2408000, 0xffe08080, RD_C2, 0, AL },
4321 +{"vf2id.t", "?d2m,?s2s,?b", 0xd2608000, 0xffe08080, RD_C2, 0, AL },
4322 +{"vi2f.t", "?d2d,?s2w,?b", 0xd2808000, 0xffe08080, RD_C2, 0, AL },
4323 +{"vcmov.t", "?d2d,?s2s,?e", 0, (int) M_VCMOV_T, INSN_MACRO, 0, AL },
4324 +{"vcmovt.t", "?d2d,?s2s,?e", 0xd2a08000, 0xfff88080, RD_C2, 0, AL },
4325 +{"vcmovf.t", "?d2d,?s2s,?e", 0xd2a88000, 0xfff88080, RD_C2, 0, AL },
4326 +{"vmmul.t", "?v6z,?s6y,?t6x", 0xf0008000, 0xff808080, RD_C2, 0, AL },
4327 +{"vtfm3.t", "?v2z,?s6y,?t2x", 0xf1008000, 0xff808080, RD_C2, 0, AL },
4328 +{"vhtfm3.t", "?v2z,?s6y,?t2x", 0xf1000080, 0xff808080, RD_C2, 0, AL },
4329 +{"vmscl.t", "?x6z,?s6y,?t0x", 0xf2008000, 0xff808080, RD_C2, 0, AL },
4330 +{"vmmov.t", "?x6z,?s6y", 0xf3808000, 0xffff8080, RD_C2, 0, AL },
4331 +{"vmidt.t", "?d6z", 0xf3838000, 0xffffff80, RD_C2, 0, AL },
4332 +{"vmzero.t", "?d6z", 0xf3868000, 0xffffff80, RD_C2, 0, AL },
4333 +{"vmone.t", "?d6z", 0xf3878000, 0xffffff80, RD_C2, 0, AL },
4334 +{"vrot.t", "?x2z,?s0y,?w", 0xf3a08000, 0xffe08080, RD_C2, 0, AL },
4335 +{"vcrsp.t", "?d2z,?s2y,?t2x", 0xf2808000, 0xff808080, RD_C2, 0, AL },
4336 +{"vadd.p", "?d1d,?s1s,?t1t", 0x60000080, 0xff808080, RD_C2, 0, AL },
4337 +{"vsub.p", "?d1d,?s1s,?t1t", 0x60800080, 0xff808080, RD_C2, 0, AL },
4338 +{"vdiv.p", "?x1z,?s1y,?t1x", 0x63800080, 0xff808080, RD_C2, 0, AL },
4339 +{"vmul.p", "?d1d,?s1s,?t1t", 0x64000080, 0xff808080, RD_C2, 0, AL },
4340 +{"vdot.p", "?d0d,?s1s,?t1t", 0x64800080, 0xff808080, RD_C2, 0, AL },
4341 +{"vscl.p", "?d1d,?s1s,?t0x", 0x65000080, 0xff808080, RD_C2, 0, AL },
4342 +{"vhdp.p", "?d0d,?s1y,?t1t", 0x66000080, 0xff808080, RD_C2, 0, AL },
4343 +{"vdet.p", "?d0d,?s1s,?t1x", 0x67000080, 0xff808080, RD_C2, 0, AL },
4344 +{"vcmp.p", "?f2,?s1s,?t1t", 0x6c000080, 0xff8080f0, RD_C2, 0, AL },
4345 +{"vcmp.p", "?f1,?s1s", 0x6c000080, 0xffff80f0, RD_C2, 0, AL },
4346 +{"vcmp.p", "?f0", 0x6c000080, 0xfffffff0, RD_C2, 0, AL },
4347 +{"vmin.p", "?d1d,?s1s,?t1t", 0x6d000080, 0xff808080, RD_C2, 0, AL },
4348 +{"vmax.p", "?d1d,?s1s,?t1t", 0x6d800080, 0xff808080, RD_C2, 0, AL },
4349 +{"vsgn.p", "?d1d,?s1s", 0xd04a0080, 0xffff8080, RD_C2, 0, AL },
4350 +{"vcst.p", "?d1d,?a", 0xd0600080, 0xffe0ff80, RD_C2, 0, AL },
4351 +{"vscmp.p", "?d1d,?s1s,?t1t", 0x6e800080, 0xff808080, RD_C2, 0, AL },
4352 +{"vsge.p", "?d1d,?s1s,?t1t", 0x6f000080, 0xff808080, RD_C2, 0, AL },
4353 +{"vslt.p", "?d1d,?s1s,?t1t", 0x6f800080, 0xff808080, RD_C2, 0, AL },
4354 +{"vus2i.p", "?d3m,?s1y", 0xd03a0080, 0xffff8080, RD_C2, 0, AL },
4355 +{"vs2i.p", "?d3m,?s1y", 0xd03b0080, 0xffff8080, RD_C2, 0, AL },
4356 +{"vi2us.p", "?d0m,?s1w", 0xd03e0080, 0xffff8080, RD_C2, 0, AL },
4357 +{"vi2s.p", "?d0m,?s1w", 0xd03f0080, 0xffff8080, RD_C2, 0, AL },
4358 +{"vmov.p", "?d1d,?s1s", 0xd0000080, 0xffff8080, RD_C2, 0, AL },
4359 +{"vabs.p", "?d1d,?s1w", 0xd0010080, 0xffff8080, RD_C2, 0, AL },
4360 +{"vneg.p", "?d1d,?s1w", 0xd0020080, 0xffff8080, RD_C2, 0, AL },
4361 +{"vidt.p", "?d1d", 0xd0030080, 0xffffff80, RD_C2, 0, AL },
4362 +{"vsat0.p", "?d1z,?s1s", 0xd0040080, 0xffff8080, RD_C2, 0, AL },
4363 +{"vsat1.p", "?d1z,?s1s", 0xd0050080, 0xffff8080, RD_C2, 0, AL },
4364 +{"vzero.p", "?d1d", 0xd0060080, 0xffffff80, RD_C2, 0, AL },
4365 +{"vone.p", "?d1d", 0xd0070080, 0xffffff80, RD_C2, 0, AL },
4366 +{"vrcp.p", "?x1z,?s1y", 0xd0100080, 0xffff8080, RD_C2, 0, AL },
4367 +{"vrsq.p", "?x1z,?s1y", 0xd0110080, 0xffff8080, RD_C2, 0, AL },
4368 +{"vsin.p", "?x1z,?s1y", 0xd0120080, 0xffff8080, RD_C2, 0, AL },
4369 +{"vcos.p", "?x1z,?s1y", 0xd0130080, 0xffff8080, RD_C2, 0, AL },
4370 +{"vexp2.p", "?x1z,?s1y", 0xd0140080, 0xffff8080, RD_C2, 0, AL },
4371 +{"vlog2.p", "?x1z,?s1y", 0xd0150080, 0xffff8080, RD_C2, 0, AL },
4372 +{"vsqrt.p", "?x1z,?s1y", 0xd0160080, 0xffff8080, RD_C2, 0, AL },
4373 +{"vasin.p", "?x1z,?s1y", 0xd0170080, 0xffff8080, RD_C2, 0, AL },
4374 +{"vnrcp.p", "?x1z,?s1y", 0xd0180080, 0xffff8080, RD_C2, 0, AL },
4375 +{"vnsin.p", "?x1z,?s1y", 0xd01a0080, 0xffff8080, RD_C2, 0, AL },
4376 +{"vrexp2.p", "?x1z,?s1y", 0xd01c0080, 0xffff8080, RD_C2, 0, AL },
4377 +{"vrndi.p", "?d1z", 0xd0210080, 0xffffff80, RD_C2, 0, AL },
4378 +{"vrndf1.p", "?d1z", 0xd0220080, 0xffffff80, RD_C2, 0, AL },
4379 +{"vrndf2.p", "?d1z", 0xd0230080, 0xffffff80, RD_C2, 0, AL },
4380 +{"vf2h.p", "?d0m,?s1s", 0xd0320080, 0xffff8080, RD_C2, 0, AL },
4381 +{"vh2f.p", "?d3d,?s1y", 0xd0330080, 0xffff8080, RD_C2, 0, AL },
4382 +{"vbfy1.p", "?d1d,?s1s", 0xd0420080, 0xffff8080, RD_C2, 0, AL },
4383 +{"vocp.p", "?d1d,?s1y", 0xd0440080, 0xffff8080, RD_C2, 0, AL },
4384 +{"vsocp.p", "?d3z,?s1y", 0xd0450080, 0xffff8080, RD_C2, 0, AL },
4385 +{"vfad.p", "?d0d,?s1s", 0xd0460080, 0xffff8080, RD_C2, 0, AL },
4386 +{"vavg.p", "?d0d,?s1s", 0xd0470080, 0xffff8080, RD_C2, 0, AL },
4387 +{"vf2in.p", "?d1m,?s1s,?b", 0xd2000080, 0xffe08080, RD_C2, 0, AL },
4388 +{"vf2iz.p", "?d1m,?s1s,?b", 0xd2200080, 0xffe08080, RD_C2, 0, AL },
4389 +{"vf2iu.p", "?d1m,?s1s,?b", 0xd2400080, 0xffe08080, RD_C2, 0, AL },
4390 +{"vf2id.p", "?d1m,?s1s,?b", 0xd2600080, 0xffe08080, RD_C2, 0, AL },
4391 +{"vi2f.p", "?d1d,?s1w,?b", 0xd2800080, 0xffe08080, RD_C2, 0, AL },
4392 +{"vcmov.p", "?d1d,?s1s,?e", 0, (int) M_VCMOV_P, INSN_MACRO, 0, AL },
4393 +{"vcmovt.p", "?d1d,?s1s,?e", 0xd2a00080, 0xfff88080, RD_C2, 0, AL },
4394 +{"vcmovf.p", "?d1d,?s1s,?e", 0xd2a80080, 0xfff88080, RD_C2, 0, AL },
4395 +{"vmmul.p", "?v5z,?s5y,?t5x", 0xf0000080, 0xff808080, RD_C2, 0, AL },
4396 +{"vtfm2.p", "?v1z,?s5y,?t1x", 0xf0800080, 0xff808080, RD_C2, 0, AL },
4397 +{"vhtfm2.p", "?v1z,?s5y,?t1x", 0xf0800000, 0xff808080, RD_C2, 0, AL },
4398 +{"vmscl.p", "?x5z,?s5y,?t0x", 0xf2000080, 0xff808080, RD_C2, 0, AL },
4399 +{"vmmov.p", "?x5z,?s5y", 0xf3800080, 0xffff8080, RD_C2, 0, AL },
4400 +{"vmidt.p", "?d5z", 0xf3830080, 0xffffff80, RD_C2, 0, AL },
4401 +{"vmzero.p", "?d5z", 0xf3860080, 0xffffff80, RD_C2, 0, AL },
4402 +{"vmone.p", "?d5z", 0xf3870080, 0xffffff80, RD_C2, 0, AL },
4403 +{"vrot.p", "?x1z,?s0y,?w", 0xf3a00080, 0xffe08080, RD_C2, 0, AL },
4404 +{"vadd.s", "?d0d,?s0s,?t0t", 0x60000000, 0xff808080, RD_C2, 0, AL },
4405 +{"vsub.s", "?d0d,?s0s,?t0t", 0x60800000, 0xff808080, RD_C2, 0, AL },
4406 +{"vdiv.s", "?x0d,?s0s,?t0t", 0x63800000, 0xff808080, RD_C2, 0, AL },
4407 +{"vmul.s", "?d0d,?s0s,?t0t", 0x64000000, 0xff808080, RD_C2, 0, AL },
4408 +{"vcmp.s", "?f2,?s0s,?t0t", 0x6c000000, 0xff8080f0, RD_C2, 0, AL },
4409 +{"vcmp.s", "?f1,?s0s", 0x6c000000, 0xffff80f0, RD_C2, 0, AL },
4410 +{"vcmp.s", "?f0", 0x6c000000, 0xfffffff0, RD_C2, 0, AL },
4411 +{"vmin.s", "?d0d,?s0s,?t0t", 0x6d000000, 0xff808080, RD_C2, 0, AL },
4412 +{"vmax.s", "?d0d,?s0s,?t0t", 0x6d800000, 0xff808080, RD_C2, 0, AL },
4413 +{"vsgn.s", "?d0d,?s0s", 0xd04a0000, 0xffff8080, RD_C2, 0, AL },
4414 +{"vcst.s", "?d0d,?a", 0xd0600000, 0xffe0ff80, RD_C2, 0, AL },
4415 +{"vscmp.s", "?d0d,?s0s,?t0t", 0x6e800000, 0xff808080, RD_C2, 0, AL },
4416 +{"vsge.s", "?d0d,?s0s,?t0t", 0x6f000000, 0xff808080, RD_C2, 0, AL },
4417 +{"vslt.s", "?d0d,?s0s,?t0t", 0x6f800000, 0xff808080, RD_C2, 0, AL },
4418 +{"vus2i.s", "?d1m,?s0y", 0xd03a0000, 0xffff8080, RD_C2, 0, AL },
4419 +{"vs2i.s", "?d1m,?s0y", 0xd03b0000, 0xffff8080, RD_C2, 0, AL },
4420 +{"vmov.s", "?d0d,?s0s", 0xd0000000, 0xffff8080, RD_C2, 0, AL },
4421 +{"vabs.s", "?d0d,?s0w", 0xd0010000, 0xffff8080, RD_C2, 0, AL },
4422 +{"vneg.s", "?d0d,?s0w", 0xd0020000, 0xffff8080, RD_C2, 0, AL },
4423 +{"vsat0.s", "?d0z,?s0s", 0xd0040000, 0xffff8080, RD_C2, 0, AL },
4424 +{"vsat1.s", "?d0z,?s0s", 0xd0050000, 0xffff8080, RD_C2, 0, AL },
4425 +{"vzero.s", "?d0d", 0xd0060000, 0xffffff80, RD_C2, 0, AL },
4426 +{"vone.s", "?d0d", 0xd0070000, 0xffffff80, RD_C2, 0, AL },
4427 +{"vrcp.s", "?x0d,?s0s", 0xd0100000, 0xffff8080, RD_C2, 0, AL },
4428 +{"vrsq.s", "?x0d,?s0s", 0xd0110000, 0xffff8080, RD_C2, 0, AL },
4429 +{"vsin.s", "?x0d,?s0s", 0xd0120000, 0xffff8080, RD_C2, 0, AL },
4430 +{"vcos.s", "?x0d,?s0s", 0xd0130000, 0xffff8080, RD_C2, 0, AL },
4431 +{"vexp2.s", "?x0d,?s0s", 0xd0140000, 0xffff8080, RD_C2, 0, AL },
4432 +{"vlog2.s", "?x0d,?s0s", 0xd0150000, 0xffff8080, RD_C2, 0, AL },
4433 +{"vsqrt.s", "?x0d,?s0s", 0xd0160000, 0xffff8080, RD_C2, 0, AL },
4434 +{"vasin.s", "?x0d,?s0s", 0xd0170000, 0xffff8080, RD_C2, 0, AL },
4435 +{"vnrcp.s", "?x0d,?s0y", 0xd0180000, 0xffff8080, RD_C2, 0, AL },
4436 +{"vnsin.s", "?x0d,?s0y", 0xd01a0000, 0xffff8080, RD_C2, 0, AL },
4437 +{"vrexp2.s", "?x0d,?s0y", 0xd01c0000, 0xffff8080, RD_C2, 0, AL },
4438 +{"vrnds.s", "?s0y", 0xd0200000, 0xffff80ff, RD_C2, 0, AL },
4439 +{"vrndi.s", "?d0d", 0xd0210000, 0xffffff80, RD_C2, 0, AL },
4440 +{"vrndf1.s", "?d0d", 0xd0220000, 0xffffff80, RD_C2, 0, AL },
4441 +{"vrndf2.s", "?d0d", 0xd0230000, 0xffffff80, RD_C2, 0, AL },
4442 +{"vh2f.s", "?d1d,?s0y", 0xd0330000, 0xffff8080, RD_C2, 0, AL },
4443 +{"vsbz.s", "?d0d,?s0s", 0xd0360000, 0xffff8080, RD_C2, 0, AL },
4444 +{"vsbn.s", "?d0d,?s0s,?t0t", 0x61000000, 0xff808080, RD_C2, 0, AL },
4445 +{"vlgb.s", "?d0d,?s0s", 0xd0370000, 0xffff8080, RD_C2, 0, AL },
4446 +{"vocp.s", "?d0d,?s0y", 0xd0440000, 0xffff8080, RD_C2, 0, AL },
4447 +{"vsocp.s", "?d1z,?s0y", 0xd0450000, 0xffff8080, RD_C2, 0, AL },
4448 +{"vf2in.s", "?d0m,?s0s,?b", 0xd2000000, 0xffe08080, RD_C2, 0, AL },
4449 +{"vf2iz.s", "?d0m,?s0s,?b", 0xd2200000, 0xffe08080, RD_C2, 0, AL },
4450 +{"vf2iu.s", "?d0m,?s0s,?b", 0xd2400000, 0xffe08080, RD_C2, 0, AL },
4451 +{"vf2id.s", "?d0m,?s0s,?b", 0xd2600000, 0xffe08080, RD_C2, 0, AL },
4452 +{"vi2f.s", "?d0d,?s0w,?b", 0xd2800000, 0xffe08080, RD_C2, 0, AL },
4453 +{"vcmov.s", "?d0d,?s0s,?e", 0, (int) M_VCMOV_S, INSN_MACRO, 0, AL },
4454 +{"vcmovt.s", "?d0d,?s0s,?e", 0xd2a00000, 0xfff88080, RD_C2, 0, AL },
4455 +{"vcmovf.s", "?d0d,?s0s,?e", 0xd2a80000, 0xfff88080, RD_C2, 0, AL },
4456 +{"vwbn.s", "?d0d,?s0s,?i", 0xd3000000, 0xff008080, RD_C2, 0, AL },
4457 +{"vpfxs", "?0,?1,?2,?3", 0xdc000000, 0xff000000, RD_C2, 0, AL },
4458 +{"vpfxt", "?0,?1,?2,?3", 0xdd000000, 0xff000000, RD_C2, 0, AL },
4459 +{"vpfxd", "?4,?5,?6,?7", 0xde000000, 0xff000000, RD_C2, 0, AL },
4460 +{"viim.s", "?t0d,j", 0xdf000000, 0xff800000, RD_C2, 0, AL },
4461 +{"vfim.s", "?t0d,?u", 0xdf800000, 0xff800000, RD_C2, 0, AL },
4462 +{"vnop", "", 0xffff0000, 0xffffffff, RD_C2, 0, AL },
4463 +{"vflush", "", 0xffff040d, 0xffffffff, RD_C2, 0, AL },
4464 +{"vsync", "", 0xffff0320, 0xffffffff, RD_C2, 0, AL },
4465 +{"vsync", "i", 0xffff0000, 0xffff0000, RD_C2, 0, AL },
4466 +
4467 /* User Defined Instruction. */
4468 {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
4469 {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
4470 @@ -1645,6 +1952,36 @@
4471 {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
4472 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
4473
4474 +/* Coprocessor 2 load/store operations overlap with the Allegrex VFPU
4475 + instructions so they are here for the latters to take precedence. */
4476 +/* COP1 ldc1 and sdc1 and COP3 ldc3 and sdc3 also overlap with the VFPU. */
4477 +{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
4478 +{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
4479 +{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
4480 +{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
4481 +{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
4482 +{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
4483 +{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
4484 +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
4485 +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
4486 +{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
4487 +{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
4488 +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
4489 +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
4490 +{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
4491 +{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
4492 +{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
4493 +{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
4494 +{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
4495 +{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
4496 +{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
4497 +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
4498 +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
4499 +{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
4500 +{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
4501 +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
4502 +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
4503 +
4504 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
4505 instructions, so they are here for the latters to take precedence. */
4506 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
4507 @@ -1682,7 +2019,6 @@
4508 {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
4509 {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
4510 {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
4511 -{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
4512 {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 },
4513 {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 },
4514 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 },