| blob | a3f0593762d86e8cd6348a5eb1593fe0b297b6eb |
1 From 03d848526a3dab8a243582a604c8cf29115a2cc7 Mon Sep 17 00:00:00 2001
2 From: Carsten Teibes <dev@f4ke.de>
3 Date: Thu, 9 Jul 2020 21:45:46 +0200
4 Subject: [PATCH] Add gcc-4.6.4-PSP.patch
6 ---
7 config.sub | 6 +
8 gcc/config.gcc | 12 ++
9 gcc/config/mips/allegrex.md | 191 ++++++++++++++++++++++++++++++++
10 gcc/config/mips/mips-ftypes.def | 4 +
11 gcc/config/mips/mips.c | 120 +++++++++++++++++++-
12 gcc/config/mips/mips.h | 20 +++-
13 gcc/config/mips/mips.md | 68 ++++++++++--
14 gcc/config/mips/mips.opt | 4 +
15 gcc/config/mips/psp.h | 31 ++++++
16 gcc/config/mips/t-allegrex | 29 +++++
17 gcc/crtstuff.c | 2 +-
18 libcpp/Makefile.in | 4 +-
19 libgcc/config.host | 2 +
20 13 files changed, 479 insertions(+), 14 deletions(-)
21 create mode 100644 gcc/config/mips/allegrex.md
22 create mode 100644 gcc/config/mips/psp.h
23 create mode 100644 gcc/config/mips/t-allegrex
25 diff --git a/config.sub b/config.sub
26 index 204218c0738..697bf7e2f10 100755
27 --- a/config.sub
28 +++ b/config.sub
29 @@ -279,6 +279,7 @@ case $basic_machine in
30 | mipsisa64sb1 | mipsisa64sb1el \
31 | mipsisa64sr71k | mipsisa64sr71kel \
32 | mipstx39 | mipstx39el \
33 + | mipsallegrex | mipsallegrexel \
34 | mn10200 | mn10300 \
35 | moxie \
36 | mt \
37 @@ -375,6 +376,7 @@ case $basic_machine in
38 | mipsisa64sb1-* | mipsisa64sb1el-* \
39 | mipsisa64sr71k-* | mipsisa64sr71kel-* \
40 | mipstx39-* | mipstx39el-* \
41 + | mipsallegrex-* | mipsallegrexel-* \
42 | mmix-* \
43 | mt-* \
44 | msp430-* \
45 @@ -771,6 +773,10 @@ case $basic_machine in
46 basic_machine=m68k-atari
47 os=-mint
48 ;;
49 + psp)
50 + basic_machine=mipsallegrexel-psp
51 + os=-elf
52 + ;;
53 mips3*-*)
54 basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
55 ;;
56 diff --git a/gcc/config.gcc b/gcc/config.gcc
57 index 6dc2427bc7c..fc2dc873723 100644
58 --- a/gcc/config.gcc
59 +++ b/gcc/config.gcc
60 @@ -2037,6 +2037,18 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
61 tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
62 tmake_file="mips/t-r3900 mips/t-libgcc-mips16"
63 ;;
64 +mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
65 + tm_file="elfos.h ${tm_file} mips/elf.h"
66 + tmake_file=mips/t-allegrex
67 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
68 + tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
69 + case ${target} in
70 + mipsallegrex*-psp-elf*)
71 + tm_file="${tm_file} mips/psp.h"
72 + ;;
73 + esac
74 + use_fixproto=yes
75 + ;;
76 mmix-knuth-mmixware)
77 tm_file="${tm_file} newlib-stdint.h"
78 need_64bit_hwint=yes
79 diff --git a/gcc/config/mips/allegrex.md b/gcc/config/mips/allegrex.md
80 new file mode 100644
81 index 00000000000..f5a7d798ba3
82 --- /dev/null
83 +++ b/gcc/config/mips/allegrex.md
84 @@ -0,0 +1,191 @@
85 +;; Sony ALLEGREX instructions.
86 +;; Copyright (C) 2005 Free Software Foundation, Inc.
87 +;;
88 +;; This file is part of GCC.
89 +;;
90 +;; GCC is free software; you can redistribute it and/or modify
91 +;; it under the terms of the GNU General Public License as published by
92 +;; the Free Software Foundation; either version 2, or (at your option)
93 +;; any later version.
94 +;;
95 +;; GCC is distributed in the hope that it will be useful,
96 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
97 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
98 +;; GNU General Public License for more details.
99 +;;
100 +;; You should have received a copy of the GNU General Public License
101 +;; along with GCC; see the file COPYING. If not, write to
102 +;; the Free Software Foundation, 59 Temple Place - Suite 330,
103 +;; Boston, MA 02111-1307, USA.
104 +
105 +(define_c_enum "unspec" [
106 + UNSPEC_WSBH
107 + UNSPEC_CLO
108 + UNSPEC_CTO
109 + UNSPEC_CACHE
110 + UNSPEC_CEIL_W_S
111 + UNSPEC_FLOOR_W_S
112 + UNSPEC_ROUND_W_S
113 +])
114 +
115 +;; Multiply Add and Subtract.
116 +;; Note: removed clobbering for madd and msub (testing needed)
117 +
118 +(define_insn "allegrex_madd"
119 + [(set (match_operand:SI 0 "register_operand" "+l")
120 + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
121 + (match_operand:SI 2 "register_operand" "d"))
122 + (match_dup 0)))]
123 + "TARGET_ALLEGREX"
124 + "madd\t%1,%2"
125 + [(set_attr "type" "imadd")
126 + (set_attr "mode" "SI")])
127 +
128 +(define_insn "allegrex_msub"
129 + [(set (match_operand:SI 0 "register_operand" "+l")
130 + (minus:SI (match_dup 0)
131 + (mult:SI (match_operand:SI 1 "register_operand" "d")
132 + (match_operand:SI 2 "register_operand" "d"))))]
133 + "TARGET_ALLEGREX"
134 + "msub\t%1,%2"
135 + [(set_attr "type" "imadd")
136 + (set_attr "mode" "SI")])
137 +
138 +
139 +;; Min and max.
140 +
141 +(define_insn "sminsi3"
142 + [(set (match_operand:SI 0 "register_operand" "=d")
143 + (smin:SI (match_operand:SI 1 "register_operand" "d")
144 + (match_operand:SI 2 "register_operand" "d")))]
145 + "TARGET_ALLEGREX"
146 + "min\t%0,%1,%2"
147 + [(set_attr "type" "arith")
148 + (set_attr "mode" "SI")])
149 +
150 +(define_insn "smaxsi3"
151 + [(set (match_operand:SI 0 "register_operand" "=d")
152 + (smax:SI (match_operand:SI 1 "register_operand" "d")
153 + (match_operand:SI 2 "register_operand" "d")))]
154 + "TARGET_ALLEGREX"
155 + "max\t%0,%1,%2"
156 + [(set_attr "type" "arith")
157 + (set_attr "mode" "SI")])
158 +
159 +
160 +;; Extended shift instructions.
161 +
162 +(define_insn "allegrex_bitrev"
163 + [(set (match_operand:SI 0 "register_operand" "=d")
164 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
165 + UNSPEC_BITREV))]
166 + "TARGET_ALLEGREX"
167 + "bitrev\t%0,%1"
168 + [(set_attr "type" "arith")
169 + (set_attr "mode" "SI")])
170 +
171 +(define_insn "allegrex_wsbh"
172 + [(set (match_operand:SI 0 "register_operand" "=d")
173 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
174 + UNSPEC_WSBH))]
175 + "TARGET_ALLEGREX"
176 + "wsbh\t%0,%1"
177 + [(set_attr "type" "arith")
178 + (set_attr "mode" "SI")])
179 +
180 +(define_insn "bswapsi2"
181 + [(set (match_operand:SI 0 "register_operand" "=d")
182 + (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
183 + "TARGET_ALLEGREX"
184 + "wsbw\t%0,%1"
185 + [(set_attr "type" "shift")
186 + (set_attr "mode" "SI")])
187 +
188 +
189 +;; Count leading ones, count trailing zeros, and count trailing ones (clz is
190 +;; already defined).
191 +
192 +(define_insn "allegrex_clo"
193 + [(set (match_operand:SI 0 "register_operand" "=d")
194 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
195 + UNSPEC_CLO))]
196 + "TARGET_ALLEGREX"
197 + "clo\t%0,%1"
198 + [(set_attr "type" "clz")
199 + (set_attr "mode" "SI")])
200 +
201 +(define_expand "ctzsi2"
202 + [(set (match_operand:SI 0 "register_operand")
203 + (ctz:SI (match_operand:SI 1 "register_operand")))]
204 + "TARGET_ALLEGREX"
205 +{
206 + rtx r1;
207 +
208 + r1 = gen_reg_rtx (SImode);
209 + emit_insn (gen_allegrex_bitrev (r1, operands[1]));
210 + emit_insn (gen_clzsi2 (operands[0], r1));
211 + DONE;
212 +})
213 +
214 +(define_expand "allegrex_cto"
215 + [(set (match_operand:SI 0 "register_operand")
216 + (unspec:SI [(match_operand:SI 1 "register_operand")]
217 + UNSPEC_CTO))]
218 + "TARGET_ALLEGREX"
219 +{
220 + rtx r1;
221 +
222 + r1 = gen_reg_rtx (SImode);
223 + emit_insn (gen_allegrex_bitrev (r1, operands[1]));
224 + emit_insn (gen_allegrex_clo (operands[0], r1));
225 + DONE;
226 +})
227 +
228 +
229 +;; Misc.
230 +
231 +(define_insn "allegrex_sync"
232 + [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
233 + "TARGET_ALLEGREX"
234 + "sync"
235 + [(set_attr "type" "unknown")
236 + (set_attr "mode" "none")])
237 +
238 +(define_insn "allegrex_cache"
239 + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
240 + (match_operand:SI 1 "register_operand" "d")]
241 + UNSPEC_CACHE)]
242 + "TARGET_ALLEGREX"
243 + "cache\t%0,0(%1)"
244 + [(set_attr "type" "unknown")
245 + (set_attr "mode" "none")])
246 +
247 +
248 +;; Floating-point builtins.
249 +
250 +(define_insn "allegrex_ceil_w_s"
251 + [(set (match_operand:SI 0 "register_operand" "=f")
252 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
253 + UNSPEC_CEIL_W_S))]
254 + "TARGET_ALLEGREX"
255 + "ceil.w.s\t%0,%1"
256 + [(set_attr "type" "fcvt")
257 + (set_attr "mode" "SF")])
258 +
259 +(define_insn "allegrex_floor_w_s"
260 + [(set (match_operand:SI 0 "register_operand" "=f")
261 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
262 + UNSPEC_FLOOR_W_S))]
263 + "TARGET_ALLEGREX"
264 + "floor.w.s\t%0,%1"
265 + [(set_attr "type" "fcvt")
266 + (set_attr "mode" "SF")])
267 +
268 +(define_insn "allegrex_round_w_s"
269 + [(set (match_operand:SI 0 "register_operand" "=f")
270 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
271 + UNSPEC_ROUND_W_S))]
272 + "TARGET_ALLEGREX"
273 + "round.w.s\t%0,%1"
274 + [(set_attr "type" "fcvt")
275 + (set_attr "mode" "SF")])
276 diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
277 index 0357aa64935..f356a68186a 100644
278 --- a/gcc/config/mips/mips-ftypes.def
279 +++ b/gcc/config/mips/mips-ftypes.def
280 @@ -53,9 +53,12 @@ DEF_MIPS_FTYPE (4, (INT, V2SF, V2SF, V2SF, V2SF))
282 DEF_MIPS_FTYPE (2, (SI, DI, SI))
283 DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
284 +DEF_MIPS_FTYPE (1, (SI, HI))
285 +DEF_MIPS_FTYPE (1, (SI, SF))
286 DEF_MIPS_FTYPE (1, (SI, SI))
287 DEF_MIPS_FTYPE (2, (SI, SI, SI))
288 DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
289 +DEF_MIPS_FTYPE (1, (SI, QI))
290 DEF_MIPS_FTYPE (1, (SI, V2HI))
291 DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
292 DEF_MIPS_FTYPE (1, (SI, V4QI))
293 @@ -124,3 +127,4 @@ DEF_MIPS_FTYPE (2, (VOID, SI, CVPOINTER))
294 DEF_MIPS_FTYPE (2, (VOID, SI, SI))
295 DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
296 DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
297 +DEF_MIPS_FTYPE (1, (VOID, VOID))
298 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
299 index 87bf18e6c8e..00489b543e5 100644
300 --- a/gcc/config/mips/mips.c
301 +++ b/gcc/config/mips/mips.c
302 @@ -239,7 +239,12 @@ enum mips_builtin_type {
303 MIPS_BUILTIN_CMP_SINGLE,
305 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
306 - MIPS_BUILTIN_BPOSGE32
307 + MIPS_BUILTIN_BPOSGE32,
308 +
309 + /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
310 + is the function code (must be less than 32) and operand 1 is the base
311 + address. */
312 + MIPS_BUILTIN_CACHE
313 };
315 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
316 @@ -516,6 +521,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
317 normal branch. */
318 static bool mips_branch_likely;
320 +/* Preferred stack boundary for proper stack vars alignment */
321 +unsigned int mips_preferred_stack_boundary;
322 +unsigned int mips_preferred_stack_align;
323 +
324 /* The current instruction-set architecture. */
325 enum processor mips_arch;
326 const struct mips_cpu_info *mips_arch_info;
327 @@ -691,6 +700,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = {
329 /* MIPS II processors. */
330 { "r6000", PROCESSOR_R6000, 2, 0 },
331 + { "allegrex", PROCESSOR_ALLEGREX, 2, 0 },
333 /* MIPS III processors. */
334 { "r4000", PROCESSOR_R4000, 3, 0 },
335 @@ -969,6 +979,9 @@ static const struct mips_rtx_cost_data
336 1, /* branch_cost */
337 4 /* memory_latency */
338 },
339 + { /* Allegrex */
340 + DEFAULT_COSTS
341 + },
342 { /* Loongson-2E */
343 DEFAULT_COSTS
344 },
345 @@ -12605,6 +12618,7 @@ AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
346 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
347 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
348 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
349 +AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
351 /* Construct a mips_builtin_description from the given arguments.
353 @@ -12701,6 +12715,30 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
354 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
355 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
357 +/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
358 + FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
359 +#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
360 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
361 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
362 +
363 +/* Same as the above, but mapped to an instruction that doesn't share the
364 + NAME. NAME is the name of the builtin without the builtin prefix. */
365 +#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
366 + { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
367 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
368 +
369 +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
370 + CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
371 + builtin_description fields. */
372 +#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
373 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
374 + MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
375 +
376 +/* Define a builtin with a specific function TYPE. */
377 +#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
378 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
379 + MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
380 +
381 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
382 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
383 builtin_description field. */
384 @@ -12945,6 +12983,40 @@ static const struct mips_builtin_description mips_builtins[] = {
385 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
386 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
388 +/* Builtin functions for the Sony ALLEGREX processor.
389 +
390 + These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
391 + to maintain compatibility with Sony's ALLEGREX GCC port.
392 +
393 + Some of the builtins may seem redundant, but they are the same as the
394 + builtins defined in the Sony compiler. I chose to map redundant and
395 + trivial builtins to the original instruction instead of creating
396 + duplicate patterns specifically for the ALLEGREX (as Sony does). */
397 +
398 + DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
399 + DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
400 + DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
401 + DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
402 + DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
403 + DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
404 + DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
405 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
406 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
407 +
408 + DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
409 + DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
410 + DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
411 + DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
412 +
413 + DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
414 + SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
415 +
416 + DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
417 + DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
418 + DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
419 + DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
420 + DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
421 +
422 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
423 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
424 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
425 @@ -13096,6 +13168,8 @@ mips_build_cvpointer_type (void)
426 /* Standard mode-based argument types. */
427 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
428 #define MIPS_ATYPE_SI intSI_type_node
429 +#define MIPS_ATYPE_HI intHI_type_node
430 +#define MIPS_ATYPE_QI intQI_type_node
431 #define MIPS_ATYPE_USI unsigned_intSI_type_node
432 #define MIPS_ATYPE_DI intDI_type_node
433 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
434 @@ -13270,6 +13344,9 @@ mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
436 switch (opno)
437 {
438 + case 0:
439 + emit_insn (GEN_FCN (icode) (0));
440 + break;
441 case 2:
442 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
443 break;
444 @@ -13439,6 +13516,28 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
445 const1_rtx, const0_rtx);
446 }
448 +/* Expand a __builtin_allegrex_cache() function. Make sure the passed
449 + cache function code is less than 32. */
450 +
451 +static rtx
452 +mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
453 +{
454 + rtx op0, op1;
455 +
456 + op0 = mips_prepare_builtin_arg (icode, 0, exp, 0);
457 + op1 = mips_prepare_builtin_arg (icode, 1, exp, 1);
458 +
459 + if (GET_CODE (op0) == CONST_INT)
460 + if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)
461 + {
462 + error ("invalid function code '%d'", INTVAL (op0));
463 + return const0_rtx;
464 + }
465 +
466 + emit_insn (GEN_FCN (icode) (op0, op1));
467 + return target;
468 +}
469 +
470 /* Implement TARGET_EXPAND_BUILTIN. */
472 static rtx
473 @@ -13484,6 +13583,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
475 case MIPS_BUILTIN_BPOSGE32:
476 return mips_expand_builtin_bposge (d->builtin_type, target);
477 +
478 + case MIPS_BUILTIN_CACHE:
479 + return mips_expand_builtin_cache (d->icode, target, exp);
480 }
481 gcc_unreachable ();
482 }
483 @@ -15921,6 +16023,22 @@ mips_option_override (void)
484 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
485 MIPS16 mode afterwards if need be. */
486 mips_set_mips16_mode (false);
487 +
488 + /* Validate -mpreferred-stack-boundary= value, or provide default.
489 + The default of 128-bit is for newABI else 64-bit. */
490 + mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
491 + mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
492 + if (mips_preferred_stack_boundary_string)
493 + {
494 + i = atoi (mips_preferred_stack_boundary_string);
495 + if (i < 2 || i > 12)
496 + error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
497 + else
498 + {
499 + mips_preferred_stack_align = (1 << i);
500 + mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
501 + }
502 + }
503 }
505 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
506 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
507 index 9600dcb28fd..8bb981c82e5 100644
508 --- a/gcc/config/mips/mips.h
509 +++ b/gcc/config/mips/mips.h
510 @@ -231,6 +231,7 @@ enum mips_code_readable_setting {
511 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
512 || mips_arch == PROCESSOR_SB1A)
513 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
514 +#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
516 /* Scheduling target defines. */
517 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
518 @@ -258,6 +259,7 @@ enum mips_code_readable_setting {
519 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
520 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
521 || mips_tune == PROCESSOR_SB1A)
522 +#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
524 /* Whether vector modes and intrinsics for ST Microelectronics
525 Loongson-2E/2F processors should be enabled. In o32 pairs of
526 @@ -852,6 +854,9 @@ enum mips_code_readable_setting {
527 /* ISA has LDC1 and SDC1. */
528 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
530 +/* ISA has just the integer condition move instructions (movn,movz) */
531 +#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
532 +
533 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
534 branch on CC, and move (both FP and non-FP) on CC. */
535 #define ISA_HAS_8CC (ISA_MIPS4 \
536 @@ -874,6 +879,7 @@ enum mips_code_readable_setting {
538 /* ISA has conditional trap instructions. */
539 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
540 + && !TARGET_ALLEGREX \
541 && !TARGET_MIPS16)
543 /* ISA has integer multiply-accumulate instructions, madd and msub. */
544 @@ -910,6 +916,7 @@ enum mips_code_readable_setting {
545 /* ISA has count leading zeroes/ones instruction (not implemented). */
546 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
547 || ISA_MIPS32R2 \
548 + || TARGET_ALLEGREX \
549 || ISA_MIPS64 \
550 || ISA_MIPS64R2) \
551 && !TARGET_MIPS16)
552 @@ -955,6 +962,7 @@ enum mips_code_readable_setting {
553 || TARGET_MIPS5400 \
554 || TARGET_MIPS5500 \
555 || TARGET_SR71K \
556 + || TARGET_ALLEGREX \
557 || TARGET_SMARTMIPS) \
558 && !TARGET_MIPS16)
560 @@ -984,11 +992,13 @@ enum mips_code_readable_setting {
562 /* ISA includes the MIPS32r2 seb and seh instructions. */
563 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
564 + || TARGET_ALLEGREX \
565 || ISA_MIPS64R2) \
566 && !TARGET_MIPS16)
568 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
569 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
570 + || TARGET_ALLEGREX \
571 || ISA_MIPS64R2) \
572 && !TARGET_MIPS16)
574 @@ -1038,7 +1048,8 @@ enum mips_code_readable_setting {
575 || ISA_MIPS64 \
576 || ISA_MIPS64R2 \
577 || TARGET_MIPS5500 \
578 - || TARGET_LOONGSON_2EF)
579 + || TARGET_LOONGSON_2EF \
580 + || TARGET_ALLEGREX)
582 /* ISA includes synci, jr.hb and jalr.hb. */
583 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
584 @@ -2133,7 +2144,7 @@ enum reg_class
585 `crtl->outgoing_args_size'. */
586 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
588 -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
589 +#define STACK_BOUNDARY (mips_preferred_stack_boundary)
590 \f
591 /* Symbolic macros for the registers used to return integer and floating
592 point values. */
593 @@ -2259,7 +2270,7 @@ typedef struct mips_args {
594 /* Treat LOC as a byte offset from the stack pointer and round it up
595 to the next fully-aligned offset. */
596 #define MIPS_STACK_ALIGN(LOC) \
597 - (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
598 + (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
600 \f
601 /* Output assembler code to FILE to increment profiler label # LABELNO
602 @@ -2911,6 +2922,9 @@ while (0)
603 #endif
604 #endif
606 +extern unsigned int mips_preferred_stack_boundary;
607 +extern unsigned int mips_preferred_stack_align;
608 +
609 #ifndef HAVE_AS_TLS
610 #define HAVE_AS_TLS 0
611 #endif
612 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
613 index e629db7a768..7032e9e8605 100644
614 --- a/gcc/config/mips/mips.md
615 +++ b/gcc/config/mips/mips.md
616 @@ -37,6 +37,7 @@
617 74kf2_1
618 74kf1_1
619 74kf3_2
620 + allegrex
621 loongson_2e
622 loongson_2f
623 loongson_3a
624 @@ -598,7 +599,7 @@
625 ;; This mode iterator allows :MOVECC to be used anywhere that a
626 ;; conditional-move-type condition is needed.
627 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
628 - (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
629 + (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF && !TARGET_ALLEGREX")])
631 ;; 32-bit integer moves for which we provide move patterns.
632 (define_mode_iterator IMOVE32
633 @@ -1885,11 +1886,11 @@
634 (mult:DI
635 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
636 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
637 - "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
638 + "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
639 {
640 if (ISA_HAS_DSP_MULT)
641 return "msub<u>\t%q0,%1,%2";
642 - else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
643 + else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
644 return "msub<u>\t%1,%2";
645 else
646 return "msac<u>\t$0,%1,%2";
647 @@ -2066,14 +2067,14 @@
648 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
649 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
650 (match_operand:DI 3 "register_operand" "0")))]
651 - "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
652 + "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
653 && !TARGET_64BIT"
654 {
655 if (TARGET_MAD)
656 return "mad<u>\t%1,%2";
657 else if (ISA_HAS_DSP_MULT)
658 return "madd<u>\t%q0,%1,%2";
659 - else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
660 + else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
661 return "madd<u>\t%1,%2";
662 else
663 /* See comment in *macc. */
664 @@ -2497,6 +2498,33 @@
665 [(set_attr "type" "pop")
666 (set_attr "mode" "<MODE>")])
667 \f
668 +;;
669 +;; ....................
670 +;;
671 +;; FIND FIRST BIT INSTRUCTION
672 +;;
673 +;; ....................
674 +;;
675 +
676 +(define_expand "ffs<mode>2"
677 + [(set (match_operand:GPR 0 "register_operand" "")
678 + (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
679 + "ISA_HAS_CLZ_CLO"
680 +{
681 + rtx r1, r2, r3, r4;
682 +
683 + r1 = gen_reg_rtx (<MODE>mode);
684 + r2 = gen_reg_rtx (<MODE>mode);
685 + r3 = gen_reg_rtx (<MODE>mode);
686 + r4 = gen_reg_rtx (<MODE>mode);
687 + emit_insn (gen_neg<mode>2 (r1, operands[1]));
688 + emit_insn (gen_and<mode>3 (r2, operands[1], r1));
689 + emit_insn (gen_clz<mode>2 (r3, r2));
690 + emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
691 + emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
692 + DONE;
693 +})
694 +
695 ;;
696 ;; ....................
697 ;;
698 @@ -2550,6 +2578,25 @@
699 [(set_attr "alu_type" "not")
700 (set_attr "mode" "<MODE>")])
701 \f
702 +(define_expand "rotl<mode>3"
703 + [(set (match_operand:GPR 0 "register_operand")
704 + (rotate:GPR (match_operand:GPR 1 "register_operand")
705 + (match_operand:SI 2 "arith_operand")))]
706 + "ISA_HAS_ROR"
707 +{
708 + rtx temp;
709 +
710 + if (GET_CODE (operands[2]) == CONST_INT)
711 + temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
712 + else
713 + {
714 + temp = gen_reg_rtx (<MODE>mode);
715 + emit_insn (gen_neg<mode>2 (temp, operands[2]));
716 + }
717 + emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
718 + DONE;
719 +})
720 +\f
721 ;;
722 ;; ....................
723 ;;
724 @@ -6301,7 +6348,7 @@
725 (const_int 0)])
726 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
727 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
728 - "ISA_HAS_CONDMOVE"
729 + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
730 "@
731 mov%T4\t%0,%z2,%1
732 mov%t4\t%0,%z3,%1"
733 @@ -6331,8 +6378,12 @@
734 (if_then_else:GPR (match_dup 5)
735 (match_operand:GPR 2 "reg_or_0_operand")
736 (match_operand:GPR 3 "reg_or_0_operand")))]
737 - "ISA_HAS_CONDMOVE"
738 + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
739 {
740 + if (ISA_HAS_INT_CONDMOVE
741 + && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
742 + FAIL;
743 +
744 mips_expand_conditional_move (operands);
745 DONE;
746 })
747 @@ -6481,6 +6532,9 @@
748 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
749 (include "loongson.md")
751 +; Sony ALLEGREX instructions.
752 +(include "allegrex.md")
753 +
754 (define_c_enum "unspec" [
755 UNSPEC_ADDRESS_FIRST
756 ])
757 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
758 index 20b0b6cde6a..281c4148ff6 100644
759 --- a/gcc/config/mips/mips.opt
760 +++ b/gcc/config/mips/mips.opt
761 @@ -306,5 +306,9 @@ mxgot
762 Target Report Var(TARGET_XGOT)
763 Lift restrictions on GOT size
765 +mpreferred-stack-boundary=
766 +Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
767 +Attempt to keep stack aligned to this power of 2
768 +
769 noasmopt
770 Driver
771 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
772 new file mode 100644
773 index 00000000000..c5e4b5d93d0
774 --- /dev/null
775 +++ b/gcc/config/mips/psp.h
776 @@ -0,0 +1,31 @@
777 +/* Support for Sony's Playstation Portable (PSP).
778 + Copyright (C) 2005 Free Software Foundation, Inc.
779 + Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
780 +
781 +This file is part of GCC.
782 +
783 +GCC is free software; you can redistribute it and/or modify
784 +it under the terms of the GNU General Public License as published by
785 +the Free Software Foundation; either version 2, or (at your option)
786 +any later version.
787 +
788 +GCC is distributed in the hope that it will be useful,
789 +but WITHOUT ANY WARRANTY; without even the implied warranty of
790 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
791 +GNU General Public License for more details.
792 +
793 +You should have received a copy of the GNU General Public License
794 +along with GCC; see the file COPYING. If not, write to
795 +the Free Software Foundation, 59 Temple Place - Suite 330,
796 +Boston, MA 02111-1307, USA. */
797 +
798 +/* Override the startfile spec to include crt0.o. */
799 +#undef STARTFILE_SPEC
800 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
801 +
802 +#undef SUBTARGET_CPP_SPEC
803 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1 -D__INTPTR_TYPE__=int -D__INT32_TYPE__=int -D__INT8_TYPE__=char -D__INT16_TYPE__=short"
804 +
805 +/* Get rid of the .pdr section. */
806 +#undef SUBTARGET_ASM_SPEC
807 +#define SUBTARGET_ASM_SPEC "-mno-pdr"
808 diff --git a/gcc/config/mips/t-allegrex b/gcc/config/mips/t-allegrex
809 new file mode 100644
810 index 00000000000..89450d118c3
811 --- /dev/null
812 +++ b/gcc/config/mips/t-allegrex
813 @@ -0,0 +1,29 @@
814 +# Suppress building libgcc1.a, since the MIPS compiler port is complete
815 +# and does not need anything from libgcc1.a.
816 +LIBGCC1 =
817 +CROSS_LIBGCC1 =
818 +
819 +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
820 +# Don't let CTOR_LIST end up in sdata section.
821 +CRTSTUFF_T_CFLAGS = -G 0
822 +
823 +# Assemble startup files.
824 +$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
825 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
826 + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
827 +
828 +$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
829 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
830 + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
831 +
832 +# We must build libgcc2.a with -G 0, in case the user wants to link
833 +# without the $gp register.
834 +TARGET_LIBGCC2_CFLAGS = -G 0
835 +
836 +# Build the libraries for both hard and soft floating point
837 +
838 +MULTILIB_OPTIONS =
839 +MULTILIB_DIRNAMES =
840 +
841 +LIBGCC = stmp-multilib
842 +INSTALL_LIBGCC = install-multilib
843 diff --git a/gcc/crtstuff.c b/gcc/crtstuff.c
844 index b65f490da66..093944937e5 100644
845 --- a/gcc/crtstuff.c
846 +++ b/gcc/crtstuff.c
847 @@ -48,7 +48,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
849 /* Target machine header files require this define. */
850 #define IN_LIBGCC2
851 -
852 +#define USED_FOR_TARGET
853 /* FIXME: Including auto-host is incorrect, but until we have
854 identified the set of defines that need to go into auto-target.h,
855 this will have to do. */
856 diff --git a/libcpp/Makefile.in b/libcpp/Makefile.in
857 index 33c44b542df..d23e35eeebb 100644
858 --- a/libcpp/Makefile.in
859 +++ b/libcpp/Makefile.in
860 @@ -212,8 +212,8 @@ ifeq ($(DEPMODE),depmode=gcc3)
861 # Note that we put the dependencies into a .Tpo file, then move them
862 # into place if the compile succeeds. We need this because gcc does
863 # not atomically write the dependency output file.
864 -COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Tpo
865 -POSTCOMPILE = @mv $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
866 +COMPILE = $(COMPILE.base) -o $@
867 +POSTCOMPILE =
868 else
869 COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
870 $(depcomp) $(COMPILE.base)
871 diff --git a/libgcc/config.host b/libgcc/config.host
872 index 25e949e0fe3..3b28a9f4028 100644
873 --- a/libgcc/config.host
874 +++ b/libgcc/config.host
875 @@ -436,6 +436,8 @@ mips-wrs-vxworks)
876 ;;
877 mipstx39-*-elf* | mipstx39el-*-elf*)
878 ;;
879 +mips*-psp-elf*)
880 + ;;
881 mmix-knuth-mmixware)
882 extra_parts="crti.o crtn.o crtbegin.o crtend.o"
883 tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"